1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5; RUN:   | FileCheck %s -check-prefix=RV64I
6
7; Test for handling of AND with constant. If this constant exceeds simm12 and
8; also is a non-empty sequence of ones starting at the least significant bit
9; with the remainder zero, we can replace it with SLLI + SLRI
10
11define i32 @and32_0x7ff(i32 %x) {
12; RV32I-LABEL: and32_0x7ff:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    andi a0, a0, 2047
15; RV32I-NEXT:    ret
16;
17; RV64I-LABEL: and32_0x7ff:
18; RV64I:       # %bb.0:
19; RV64I-NEXT:    andi a0, a0, 2047
20; RV64I-NEXT:    ret
21  %a = and i32 %x, 2047
22  ret i32 %a
23}
24
25define i32 @and32_0xfff(i32 %x) {
26; RV32I-LABEL: and32_0xfff:
27; RV32I:       # %bb.0:
28; RV32I-NEXT:    slli a0, a0, 20
29; RV32I-NEXT:    srli a0, a0, 20
30; RV32I-NEXT:    ret
31;
32; RV64I-LABEL: and32_0xfff:
33; RV64I:       # %bb.0:
34; RV64I-NEXT:    slli a0, a0, 52
35; RV64I-NEXT:    srli a0, a0, 52
36; RV64I-NEXT:    ret
37  %a = and i32 %x, 4095
38  ret i32 %a
39}
40
41define i64 @and64_0x7ff(i64 %x) {
42; RV32I-LABEL: and64_0x7ff:
43; RV32I:       # %bb.0:
44; RV32I-NEXT:    andi a0, a0, 2047
45; RV32I-NEXT:    li a1, 0
46; RV32I-NEXT:    ret
47;
48; RV64I-LABEL: and64_0x7ff:
49; RV64I:       # %bb.0:
50; RV64I-NEXT:    andi a0, a0, 2047
51; RV64I-NEXT:    ret
52  %a = and i64 %x, 2047
53  ret i64 %a
54}
55
56define i64 @and64_0xfff(i64 %x) {
57; RV32I-LABEL: and64_0xfff:
58; RV32I:       # %bb.0:
59; RV32I-NEXT:    slli a0, a0, 20
60; RV32I-NEXT:    srli a0, a0, 20
61; RV32I-NEXT:    li a1, 0
62; RV32I-NEXT:    ret
63;
64; RV64I-LABEL: and64_0xfff:
65; RV64I:       # %bb.0:
66; RV64I-NEXT:    slli a0, a0, 52
67; RV64I-NEXT:    srli a0, a0, 52
68; RV64I-NEXT:    ret
69  %a = and i64 %x, 4095
70  ret i64 %a
71}
72
73