1; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
2; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
3; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
4; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
5; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
6; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
7; RUN:     -check-prefix=CHECK-REG %s
8; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
9; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \
10; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
11; RUN:     -check-prefix=CHECK-FISL %s
12; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
13; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
14; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
15; RUN:     -check-prefix=CHECK-LE %s
16
17define double @test1(double %a, double %b) {
18entry:
19  %v = fmul double %a, %b
20  ret double %v
21
22; CHECK-LABEL: @test1
23; CHECK: xsmuldp f1, f1, f2
24; CHECK: blr
25
26; CHECK-LE-LABEL: @test1
27; CHECK-LE: xsmuldp f1, f1, f2
28; CHECK-LE: blr
29}
30
31define double @test2(double %a, double %b) {
32entry:
33  %v = fdiv double %a, %b
34  ret double %v
35
36; CHECK-LABEL: @test2
37; CHECK: xsdivdp f1, f1, f2
38; CHECK: blr
39
40; CHECK-LE-LABEL: @test2
41; CHECK-LE: xsdivdp f1, f1, f2
42; CHECK-LE: blr
43}
44
45define double @test3(double %a, double %b) {
46entry:
47  %v = fadd double %a, %b
48  ret double %v
49
50; CHECK-LABEL: @test3
51; CHECK: xsadddp f1, f1, f2
52; CHECK: blr
53
54; CHECK-LE-LABEL: @test3
55; CHECK-LE: xsadddp f1, f1, f2
56; CHECK-LE: blr
57}
58
59define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
60entry:
61  %v = fadd <2 x double> %a, %b
62  ret <2 x double> %v
63
64; CHECK-LABEL: @test4
65; CHECK: xvadddp v2, v2, v3
66; CHECK: blr
67
68; CHECK-LE-LABEL: @test4
69; CHECK-LE: xvadddp v2, v2, v3
70; CHECK-LE: blr
71}
72
73define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
74entry:
75  %v = xor <4 x i32> %a, %b
76  ret <4 x i32> %v
77
78; CHECK-REG-LABEL: @test5
79; CHECK-REG: xxlxor v2, v2, v3
80; CHECK-REG: blr
81
82; CHECK-FISL-LABEL: @test5
83; CHECK-FISL: xxlxor v2, v2, v3
84; CHECK-FISL: blr
85
86; CHECK-LE-LABEL: @test5
87; CHECK-LE: xxlxor v2, v2, v3
88; CHECK-LE: blr
89}
90
91define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
92entry:
93  %v = xor <8 x i16> %a, %b
94  ret <8 x i16> %v
95
96; CHECK-REG-LABEL: @test6
97; CHECK-REG: xxlxor v2, v2, v3
98; CHECK-REG: blr
99
100; CHECK-FISL-LABEL: @test6
101; CHECK-FISL: xxlxor v2, v2, v3
102; CHECK-FISL: blr
103
104; CHECK-LE-LABEL: @test6
105; CHECK-LE: xxlxor v2, v2, v3
106; CHECK-LE: blr
107}
108
109define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
110entry:
111  %v = xor <16 x i8> %a, %b
112  ret <16 x i8> %v
113
114; CHECK-REG-LABEL: @test7
115; CHECK-REG: xxlxor v2, v2, v3
116; CHECK-REG: blr
117
118; CHECK-FISL-LABEL: @test7
119; CHECK-FISL: xxlxor v2, v2, v3
120; CHECK-FISL: blr
121
122; CHECK-LE-LABEL: @test7
123; CHECK-LE: xxlxor v2, v2, v3
124; CHECK-LE: blr
125}
126
127define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
128entry:
129  %v = or <4 x i32> %a, %b
130  ret <4 x i32> %v
131
132; CHECK-REG-LABEL: @test8
133; CHECK-REG: xxlor v2, v2, v3
134; CHECK-REG: blr
135
136; CHECK-FISL-LABEL: @test8
137; CHECK-FISL: xxlor v2, v2, v3
138; CHECK-FISL: blr
139
140; CHECK-LE-LABEL: @test8
141; CHECK-LE: xxlor v2, v2, v3
142; CHECK-LE: blr
143}
144
145define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
146entry:
147  %v = or <8 x i16> %a, %b
148  ret <8 x i16> %v
149
150; CHECK-REG-LABEL: @test9
151; CHECK-REG: xxlor v2, v2, v3
152; CHECK-REG: blr
153
154; CHECK-FISL-LABEL: @test9
155; CHECK-FISL: xxlor v2, v2, v3
156; CHECK-FISL: blr
157
158; CHECK-LE-LABEL: @test9
159; CHECK-LE: xxlor v2, v2, v3
160; CHECK-LE: blr
161}
162
163define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
164entry:
165  %v = or <16 x i8> %a, %b
166  ret <16 x i8> %v
167
168; CHECK-REG-LABEL: @test10
169; CHECK-REG: xxlor v2, v2, v3
170; CHECK-REG: blr
171
172; CHECK-FISL-LABEL: @test10
173; CHECK-FISL: xxlor v2, v2, v3
174; CHECK-FISL: blr
175
176; CHECK-LE-LABEL: @test10
177; CHECK-LE: xxlor v2, v2, v3
178; CHECK-LE: blr
179}
180
181define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
182entry:
183  %v = and <4 x i32> %a, %b
184  ret <4 x i32> %v
185
186; CHECK-REG-LABEL: @test11
187; CHECK-REG: xxland v2, v2, v3
188; CHECK-REG: blr
189
190; CHECK-FISL-LABEL: @test11
191; CHECK-FISL: xxland v2, v2, v3
192; CHECK-FISL: blr
193
194; CHECK-LE-LABEL: @test11
195; CHECK-LE: xxland v2, v2, v3
196; CHECK-LE: blr
197}
198
199define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
200entry:
201  %v = and <8 x i16> %a, %b
202  ret <8 x i16> %v
203
204; CHECK-REG-LABEL: @test12
205; CHECK-REG: xxland v2, v2, v3
206; CHECK-REG: blr
207
208; CHECK-FISL-LABEL: @test12
209; CHECK-FISL: xxland v2, v2, v3
210; CHECK-FISL: blr
211
212; CHECK-LE-LABEL: @test12
213; CHECK-LE: xxland v2, v2, v3
214; CHECK-LE: blr
215}
216
217define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
218entry:
219  %v = and <16 x i8> %a, %b
220  ret <16 x i8> %v
221
222; CHECK-REG-LABEL: @test13
223; CHECK-REG: xxland v2, v2, v3
224; CHECK-REG: blr
225
226; CHECK-FISL-LABEL: @test13
227; CHECK-FISL: xxland v2, v2, v3
228; CHECK-FISL: blr
229
230; CHECK-LE-LABEL: @test13
231; CHECK-LE: xxland v2, v2, v3
232; CHECK-LE: blr
233}
234
235define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
236entry:
237  %v = or <4 x i32> %a, %b
238  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
239  ret <4 x i32> %w
240
241; CHECK-REG-LABEL: @test14
242; CHECK-REG: xxlnor v2, v2, v3
243; CHECK-REG: blr
244
245; CHECK-FISL-LABEL: @test14
246; CHECK-FISL: xxlor vs0, v2, v3
247; CHECK-FISL: xxlnor v2, v2, v3
248; CHECK-FISL-NOT: lis
249; CHECK-FISL-NOT: ori
250; CHECK-FISL: li r3, -16
251; CHECK-FISL-NOT: lis
252; CHECK-FISL-NOT: ori
253; CHECK-FISL: stxvd2x vs0, r1, r3
254; CHECK-FISL: blr
255
256; CHECK-LE-LABEL: @test14
257; CHECK-LE: xxlnor v2, v2, v3
258; CHECK-LE: blr
259}
260
261define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
262entry:
263  %v = or <8 x i16> %a, %b
264  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
265  ret <8 x i16> %w
266
267; CHECK-REG-LABEL: @test15
268; CHECK-REG: xxlnor v2, v2, v3
269; CHECK-REG: blr
270
271; CHECK-FISL-LABEL: @test15
272; CHECK-FISL: xxlor vs0, v2, v3
273; CHECK-FISL: xxlor v4, vs0, vs0
274; CHECK-FISL: xxlnor vs0, v2, v3
275; CHECK-FISL: xxlor v2, vs0, vs0
276; CHECK-FISL-NOT: lis
277; CHECK-FISL-NOT: ori
278; CHECK-FISL: li r3, -16
279; CHECK-FISL-NOT: lis
280; CHECK-FISL-NOT: ori
281; CHECK-FISL: stxvd2x v4, r1, r3
282; CHECK-FISL: blr
283
284; CHECK-LE-LABEL: @test15
285; CHECK-LE: xxlnor v2, v2, v3
286; CHECK-LE: blr
287}
288
289define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
290entry:
291  %v = or <16 x i8> %a, %b
292  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
293  ret <16 x i8> %w
294
295; CHECK-REG-LABEL: @test16
296; CHECK-REG: xxlnor v2, v2, v3
297; CHECK-REG: blr
298
299; CHECK-FISL-LABEL: @test16
300; CHECK-FISL: xxlor vs0, v2, v3
301; CHECK-FISL: xxlor v4, vs0, vs0
302; CHECK-FISL: xxlnor vs0, v2, v3
303; CHECK-FISL: xxlor v2, vs0, vs0
304; CHECK-FISL-NOT: lis
305; CHECK-FISL-NOT: ori
306; CHECK-FISL: li r3, -16
307; CHECK-FISL-NOT: lis
308; CHECK-FISL-NOT: ori
309; CHECK-FISL: stxvd2x v4, r1, r3
310; CHECK-FISL: blr
311
312; CHECK-LE-LABEL: @test16
313; CHECK-LE: xxlnor v2, v2, v3
314; CHECK-LE: blr
315}
316
317define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
318entry:
319  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
320  %v = and <4 x i32> %a, %w
321  ret <4 x i32> %v
322
323; CHECK-REG-LABEL: @test17
324; CHECK-REG: xxlandc v2, v2, v3
325; CHECK-REG: blr
326
327; CHECK-FISL-LABEL: @test17
328; CHECK-FISL: xxlnor v3, v3, v3
329; CHECK-FISL: xxland v2, v2, v3
330; CHECK-FISL: blr
331
332; CHECK-LE-LABEL: @test17
333; CHECK-LE: xxlandc v2, v2, v3
334; CHECK-LE: blr
335}
336
337define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
338entry:
339  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
340  %v = and <8 x i16> %a, %w
341  ret <8 x i16> %v
342
343; CHECK-REG-LABEL: @test18
344; CHECK-REG: xxlandc v2, v2, v3
345; CHECK-REG: blr
346
347; CHECK-FISL-LABEL: @test18
348; CHECK-FISL: xxlnor vs0, v3, v3
349; CHECK-FISL: xxlor v4, vs0, vs0
350; CHECK-FISL: xxlandc vs0, v2, v3
351; CHECK-FISL: xxlor v2, vs0, vs0
352; CHECK-FISL-NOT: lis
353; CHECK-FISL-NOT: ori
354; CHECK-FISL: li r3, -16
355; CHECK-FISL-NOT: lis
356; CHECK-FISL-NOT: ori
357; CHECK-FISL: stxvd2x v4, r1, r3
358; CHECK-FISL: blr
359
360; CHECK-LE-LABEL: @test18
361; CHECK-LE: xxlandc v2, v2, v3
362; CHECK-LE: blr
363}
364
365define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
366entry:
367  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
368  %v = and <16 x i8> %a, %w
369  ret <16 x i8> %v
370
371; CHECK-REG-LABEL: @test19
372; CHECK-REG: xxlandc v2, v2, v3
373; CHECK-REG: blr
374
375; CHECK-FISL-LABEL: @test19
376; CHECK-FISL: xxlnor vs0, v3, v3
377; CHECK-FISL: xxlor v4, vs0, vs0
378; CHECK-FISL: xxlandc vs0, v2, v3
379; CHECK-FISL: xxlor v2, vs0, vs0
380; CHECK-FISL-NOT: lis
381; CHECK-FISL-NOT: ori
382; CHECK-FISL: li r3, -16
383; CHECK-FISL-NOT: lis
384; CHECK-FISL-NOT: ori
385; CHECK-FISL: stxvd2x v4, r1, r3
386; CHECK-FISL: blr
387
388; CHECK-LE-LABEL: @test19
389; CHECK-LE: xxlandc v2, v2, v3
390; CHECK-LE: blr
391}
392
393define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
394entry:
395  %m = icmp eq <4 x i32> %c, %d
396  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
397  ret <4 x i32> %v
398
399; CHECK-REG-LABEL: @test20
400; CHECK-REG: vcmpequw v4, v4, v5
401; CHECK-REG: xxsel v2, v3, v2, v4
402; CHECK-REG: blr
403
404; CHECK-FISL-LABEL: @test20
405; CHECK-FISL: vcmpequw v4, v4, v5
406; CHECK-FISL: xxsel v2, v3, v2, v4
407; CHECK-FISL: blr
408
409; CHECK-LE-LABEL: @test20
410; CHECK-LE: vcmpequw v4, v4, v5
411; CHECK-LE: xxsel v2, v3, v2, v4
412; CHECK-LE: blr
413}
414
415define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
416entry:
417  %m = fcmp oeq <4 x float> %c, %d
418  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
419  ret <4 x float> %v
420
421; CHECK-REG-LABEL: @test21
422; CHECK-REG: xvcmpeqsp vs0, v4, v5
423; CHECK-REG: xxsel v2, v3, v2, vs0
424; CHECK-REG: blr
425
426; CHECK-FISL-LABEL: @test21
427; CHECK-FISL: xvcmpeqsp v4, v4, v5
428; CHECK-FISL: xxsel v2, v3, v2, v4
429; CHECK-FISL: blr
430
431; CHECK-LE-LABEL: @test21
432; CHECK-LE: xvcmpeqsp vs0, v4, v5
433; CHECK-LE: xxsel v2, v3, v2, vs0
434; CHECK-LE: blr
435}
436
437define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
438entry:
439  %m = fcmp ueq <4 x float> %c, %d
440  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
441  ret <4 x float> %v
442
443; CHECK-REG-LABEL: @test22
444; CHECK-REG-DAG: xvcmpeqsp vs0, v5, v5
445; CHECK-REG-DAG: xvcmpeqsp vs1, v4, v4
446; CHECK-REG-DAG: xvcmpeqsp vs2, v4, v5
447; CHECK-REG-DAG: xxlnor vs0, vs0, vs0
448; CHECK-REG-DAG: xxlnor vs1, vs1, vs1
449; CHECK-REG-DAG: xxlor vs0, vs1, vs0
450; CHECK-REG-DAG: xxlor vs0, vs2, vs0
451; CHECK-REG: xxsel v2, v3, v2, vs0
452; CHECK-REG: blr
453
454; CHECK-FISL-LABEL: @test22
455; CHECK-FISL-DAG: xvcmpeqsp vs0, v4, v5
456; CHECK-FISL-DAG: xvcmpeqsp v5, v5, v5
457; CHECK-FISL-DAG: xvcmpeqsp v4, v4, v4
458; CHECK-FISL-DAG: xxlnor v5, v5, v5
459; CHECK-FISL-DAG: xxlnor v4, v4, v4
460; CHECK-FISL-DAG: xxlor v4, v4, v5
461; CHECK-FISL-DAG: xxlor vs0, vs0, v4
462; CHECK-FISL: xxsel v2, v3, v2, vs0
463; CHECK-FISL: blr
464
465; CHECK-LE-LABEL: @test22
466; CHECK-LE-DAG: xvcmpeqsp vs0, v5, v5
467; CHECK-LE-DAG: xvcmpeqsp vs1, v4, v4
468; CHECK-LE-DAG: xvcmpeqsp vs2, v4, v5
469; CHECK-LE-DAG: xxlnor vs0, vs0, vs0
470; CHECK-LE-DAG: xxlnor vs1, vs1, vs1
471; CHECK-LE-DAG: xxlor vs0, vs1, vs0
472; CHECK-LE-DAG: xxlor vs0, vs2, vs0
473; CHECK-LE: xxsel v2, v3, v2, vs0
474; CHECK-LE: blr
475}
476
477define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
478entry:
479  %m = icmp eq <8 x i16> %c, %d
480  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
481  ret <8 x i16> %v
482
483; CHECK-REG-LABEL: @test23
484; CHECK-REG: vcmpequh v4, v4, v5
485; CHECK-REG: xxsel v2, v3, v2, v4
486; CHECK-REG: blr
487
488; CHECK-FISL-LABEL: @test23
489; CHECK-FISL: vcmpequh v4, v4, v5
490; CHECK-FISL: xxsel v2, v3, v2, v4
491; CHECK-FISL: blr
492
493; CHECK-LE-LABEL: @test23
494; CHECK-LE: vcmpequh v4, v4, v5
495; CHECK-LE: xxsel v2, v3, v2, v4
496; CHECK-LE: blr
497}
498
499define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
500entry:
501  %m = icmp eq <16 x i8> %c, %d
502  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
503  ret <16 x i8> %v
504
505; CHECK-REG-LABEL: @test24
506; CHECK-REG: vcmpequb v4, v4, v5
507; CHECK-REG: xxsel v2, v3, v2, v4
508; CHECK-REG: blr
509
510; CHECK-FISL-LABEL: @test24
511; CHECK-FISL: vcmpequb v4, v4, v5
512; CHECK-FISL: xxsel v2, v3, v2, v4
513; CHECK-FISL: blr
514
515; CHECK-LE-LABEL: @test24
516; CHECK-LE: vcmpequb v4, v4, v5
517; CHECK-LE: xxsel v2, v3, v2, v4
518; CHECK-LE: blr
519}
520
521define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
522entry:
523  %m = fcmp oeq <2 x double> %c, %d
524  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
525  ret <2 x double> %v
526
527; CHECK-LABEL: @test25
528; CHECK: xvcmpeqdp vs0, v4, v5
529; CHECK: xxsel v2, v3, v2, vs0
530; CHECK: blr
531
532; CHECK-LE-LABEL: @test25
533; CHECK-LE: xvcmpeqdp v4, v4, v5
534; CHECK-LE: xxsel v2, v3, v2, v4
535; CHECK-LE: blr
536}
537
538define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
539  %v = add <2 x i64> %a, %b
540  ret <2 x i64> %v
541
542; CHECK-LABEL: @test26
543
544; Make sure we use only two stores (one for each operand).
545; CHECK: stxvd2x v3, 0, r3
546; CHECK: stxvd2x v2, 0, r4
547; CHECK-NOT: stxvd2x
548
549; FIXME: The code quality here is not good; just make sure we do something for now.
550; CHECK: add r3, r4, r3
551; CHECK: add r3, r4, r3
552; CHECK: blr
553
554; CHECK-LE: vaddudm v2, v2, v3
555; CHECK-LE: blr
556}
557
558define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
559  %v = and <2 x i64> %a, %b
560  ret <2 x i64> %v
561
562; CHECK-LABEL: @test27
563; CHECK: xxland v2, v2, v3
564; CHECK: blr
565
566; CHECK-LE-LABEL: @test27
567; CHECK-LE: xxland v2, v2, v3
568; CHECK-LE: blr
569}
570
571define <2 x double> @test28(<2 x double>* %a) {
572  %v = load <2 x double>, <2 x double>* %a, align 16
573  ret <2 x double> %v
574
575; CHECK-LABEL: @test28
576; CHECK: lxvd2x v2, 0, r3
577; CHECK: blr
578
579; CHECK-LE-LABEL: @test28
580; CHECK-LE: lxvd2x vs0, 0, r3
581; CHECK-LE: xxswapd v2, vs0
582; CHECK-LE: blr
583}
584
585define void @test29(<2 x double>* %a, <2 x double> %b) {
586  store <2 x double> %b, <2 x double>* %a, align 16
587  ret void
588
589; CHECK-LABEL: @test29
590; CHECK: stxvd2x v2, 0, r3
591; CHECK: blr
592
593; CHECK-LE-LABEL: @test29
594; CHECK-LE: xxswapd vs0, v2
595; CHECK-LE: stxvd2x vs0, 0, r3
596; CHECK-LE: blr
597}
598
599define <2 x double> @test28u(<2 x double>* %a) {
600  %v = load <2 x double>, <2 x double>* %a, align 8
601  ret <2 x double> %v
602
603; CHECK-LABEL: @test28u
604; CHECK: lxvd2x v2, 0, r3
605; CHECK: blr
606
607; CHECK-LE-LABEL: @test28u
608; CHECK-LE: lxvd2x vs0, 0, r3
609; CHECK-LE: xxswapd v2, vs0
610; CHECK-LE: blr
611}
612
613define void @test29u(<2 x double>* %a, <2 x double> %b) {
614  store <2 x double> %b, <2 x double>* %a, align 8
615  ret void
616
617; CHECK-LABEL: @test29u
618; CHECK: stxvd2x v2, 0, r3
619; CHECK: blr
620
621; CHECK-LE-LABEL: @test29u
622; CHECK-LE: xxswapd vs0, v2
623; CHECK-LE: stxvd2x vs0, 0, r3
624; CHECK-LE: blr
625}
626
627define <2 x i64> @test30(<2 x i64>* %a) {
628  %v = load <2 x i64>, <2 x i64>* %a, align 16
629  ret <2 x i64> %v
630
631; CHECK-REG-LABEL: @test30
632; CHECK-REG: lxvd2x v2, 0, r3
633; CHECK-REG: blr
634
635; CHECK-FISL-LABEL: @test30
636; CHECK-FISL: lxvd2x vs0, 0, r3
637; CHECK-FISL: xxlor v2, vs0, vs0
638; CHECK-FISL: blr
639
640; CHECK-LE-LABEL: @test30
641; CHECK-LE: lxvd2x vs0, 0, r3
642; CHECK-LE: xxswapd v2, vs0
643; CHECK-LE: blr
644}
645
646define void @test31(<2 x i64>* %a, <2 x i64> %b) {
647  store <2 x i64> %b, <2 x i64>* %a, align 16
648  ret void
649
650; CHECK-LABEL: @test31
651; CHECK: stxvd2x v2, 0, r3
652; CHECK: blr
653
654; CHECK-LE-LABEL: @test31
655; CHECK-LE: xxswapd vs0, v2
656; CHECK-LE: stxvd2x vs0, 0, r3
657; CHECK-LE: blr
658}
659
660define <4 x float> @test32(<4 x float>* %a) {
661  %v = load <4 x float>, <4 x float>* %a, align 16
662  ret <4 x float> %v
663
664; CHECK-REG-LABEL: @test32
665; CHECK-REG: lxvw4x v2, 0, r3
666; CHECK-REG: blr
667
668; CHECK-FISL-LABEL: @test32
669; CHECK-FISL: lxvw4x v2, 0, r3
670; CHECK-FISL: blr
671
672; CHECK-LE-LABEL: @test32
673; CHECK-LE: lvx v2, 0, r3
674; CHECK-LE-NOT: xxswapd
675; CHECK-LE: blr
676}
677
678define void @test33(<4 x float>* %a, <4 x float> %b) {
679  store <4 x float> %b, <4 x float>* %a, align 16
680  ret void
681
682; CHECK-REG-LABEL: @test33
683; CHECK-REG: stxvw4x v2, 0, r3
684; CHECK-REG: blr
685
686; CHECK-FISL-LABEL: @test33
687; CHECK-FISL: stxvw4x v2, 0, r3
688; CHECK-FISL: blr
689
690; CHECK-LE-LABEL: @test33
691; CHECK-LE-NOT: xxswapd
692; CHECK-LE: stvx v2, 0, r3
693; CHECK-LE: blr
694}
695
696define <4 x float> @test32u(<4 x float>* %a) {
697  %v = load <4 x float>, <4 x float>* %a, align 8
698  ret <4 x float> %v
699
700; CHECK-LABEL: @test32u
701; CHECK-DAG: lvsl v3, 0, r3
702; CHECK-DAG: lvx v2, r3, r4
703; CHECK-DAG: lvx v4, 0, r3
704; CHECK: vperm v2, v4, v2, v3
705; CHECK: blr
706
707; CHECK-LE-LABEL: @test32u
708; CHECK-LE: lxvd2x vs0, 0, r3
709; CHECK-LE: xxswapd v2, vs0
710; CHECK-LE: blr
711}
712
713define void @test33u(<4 x float>* %a, <4 x float> %b) {
714  store <4 x float> %b, <4 x float>* %a, align 8
715  ret void
716
717; CHECK-REG-LABEL: @test33u
718; CHECK-REG: stxvw4x v2, 0, r3
719; CHECK-REG: blr
720
721; CHECK-FISL-LABEL: @test33u
722; CHECK-FISL: stxvw4x v2, 0, r3
723; CHECK-FISL: blr
724
725; CHECK-LE-LABEL: @test33u
726; CHECK-LE: xxswapd vs0, v2
727; CHECK-LE: stxvd2x vs0, 0, r3
728; CHECK-LE: blr
729}
730
731define <4 x i32> @test34(<4 x i32>* %a) {
732  %v = load <4 x i32>, <4 x i32>* %a, align 16
733  ret <4 x i32> %v
734
735; CHECK-REG-LABEL: @test34
736; CHECK-REG: lxvw4x v2, 0, r3
737; CHECK-REG: blr
738
739; CHECK-FISL-LABEL: @test34
740; CHECK-FISL: lxvw4x v2, 0, r3
741; CHECK-FISL: blr
742
743; CHECK-LE-LABEL: @test34
744; CHECK-LE: lvx v2, 0, r3
745; CHECK-LE-NOT: xxswapd
746; CHECK-LE: blr
747}
748
749define void @test35(<4 x i32>* %a, <4 x i32> %b) {
750  store <4 x i32> %b, <4 x i32>* %a, align 16
751  ret void
752
753; CHECK-REG-LABEL: @test35
754; CHECK-REG: stxvw4x v2, 0, r3
755; CHECK-REG: blr
756
757; CHECK-FISL-LABEL: @test35
758; CHECK-FISL: stxvw4x v2, 0, r3
759; CHECK-FISL: blr
760
761; CHECK-LE-LABEL: @test35
762; CHECK-LE-NOT: xxswapd
763; CHECK-LE: stvx v2, 0, r3
764; CHECK-LE: blr
765}
766
767define <2 x double> @test40(<2 x i64> %a) {
768  %v = uitofp <2 x i64> %a to <2 x double>
769  ret <2 x double> %v
770
771; CHECK-LABEL: @test40
772; CHECK: xvcvuxddp v2, v2
773; CHECK: blr
774
775; CHECK-LE-LABEL: @test40
776; CHECK-LE: xvcvuxddp v2, v2
777; CHECK-LE: blr
778}
779
780define <2 x double> @test41(<2 x i64> %a) {
781  %v = sitofp <2 x i64> %a to <2 x double>
782  ret <2 x double> %v
783
784; CHECK-LABEL: @test41
785; CHECK: xvcvsxddp v2, v2
786; CHECK: blr
787
788; CHECK-LE-LABEL: @test41
789; CHECK-LE: xvcvsxddp v2, v2
790; CHECK-LE: blr
791}
792
793define <2 x i64> @test42(<2 x double> %a) {
794  %v = fptoui <2 x double> %a to <2 x i64>
795  ret <2 x i64> %v
796
797; CHECK-LABEL: @test42
798; CHECK: xvcvdpuxds v2, v2
799; CHECK: blr
800
801; CHECK-LE-LABEL: @test42
802; CHECK-LE: xvcvdpuxds v2, v2
803; CHECK-LE: blr
804}
805
806define <2 x i64> @test43(<2 x double> %a) {
807  %v = fptosi <2 x double> %a to <2 x i64>
808  ret <2 x i64> %v
809
810; CHECK-LABEL: @test43
811; CHECK: xvcvdpsxds v2, v2
812; CHECK: blr
813
814; CHECK-LE-LABEL: @test43
815; CHECK-LE: xvcvdpsxds v2, v2
816; CHECK-LE: blr
817}
818
819define <2 x float> @test44(<2 x i64> %a) {
820  %v = uitofp <2 x i64> %a to <2 x float>
821  ret <2 x float> %v
822
823; CHECK-LABEL: @test44
824; FIXME: The code quality here looks pretty bad.
825; CHECK: blr
826}
827
828define <2 x float> @test45(<2 x i64> %a) {
829  %v = sitofp <2 x i64> %a to <2 x float>
830  ret <2 x float> %v
831
832; CHECK-LABEL: @test45
833; FIXME: The code quality here looks pretty bad.
834; CHECK: blr
835}
836
837define <2 x i64> @test46(<2 x float> %a) {
838  %v = fptoui <2 x float> %a to <2 x i64>
839  ret <2 x i64> %v
840
841; CHECK-LABEL: @test46
842; FIXME: The code quality here looks pretty bad.
843; CHECK: blr
844}
845
846define <2 x i64> @test47(<2 x float> %a) {
847  %v = fptosi <2 x float> %a to <2 x i64>
848  ret <2 x i64> %v
849
850; CHECK-LABEL: @test47
851; FIXME: The code quality here looks pretty bad.
852; CHECK: blr
853}
854
855define <2 x double> @test50(double* %a) {
856  %v = load double, double* %a, align 8
857  %w = insertelement <2 x double> undef, double %v, i32 0
858  %x = insertelement <2 x double> %w, double %v, i32 1
859  ret <2 x double> %x
860
861; CHECK-LABEL: @test50
862; CHECK: lxvdsx v2, 0, r3
863; CHECK: blr
864
865; CHECK-LE-LABEL: @test50
866; CHECK-LE: lxvdsx v2, 0, r3
867; CHECK-LE: blr
868}
869
870define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
871  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
872  ret <2 x double> %v
873
874; CHECK-LABEL: @test51
875; CHECK: xxspltd v2, v2, 0
876; CHECK: blr
877
878; CHECK-LE-LABEL: @test51
879; CHECK-LE: xxspltd v2, v2, 1
880; CHECK-LE: blr
881}
882
883define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
884  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
885  ret <2 x double> %v
886
887; CHECK-LABEL: @test52
888; CHECK: xxmrghd v2, v2, v3
889; CHECK: blr
890
891; CHECK-LE-LABEL: @test52
892; CHECK-LE: xxmrgld v2, v3, v2
893; CHECK-LE: blr
894}
895
896define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
897  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
898  ret <2 x double> %v
899
900; CHECK-LABEL: @test53
901; CHECK: xxmrghd v2, v3, v2
902; CHECK: blr
903
904; CHECK-LE-LABEL: @test53
905; CHECK-LE: xxmrgld v2, v2, v3
906; CHECK-LE: blr
907}
908
909define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
910  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
911  ret <2 x double> %v
912
913; CHECK-LABEL: @test54
914; CHECK: xxpermdi v2, v2, v3, 2
915; CHECK: blr
916
917; CHECK-LE-LABEL: @test54
918; CHECK-LE: xxpermdi v2, v3, v2, 2
919; CHECK-LE: blr
920}
921
922define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
923  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
924  ret <2 x double> %v
925
926; CHECK-LABEL: @test55
927; CHECK: xxmrgld v2, v2, v3
928; CHECK: blr
929
930; CHECK-LE-LABEL: @test55
931; CHECK-LE: xxmrghd v2, v3, v2
932; CHECK-LE: blr
933}
934
935define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
936  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
937  ret <2 x i64> %v
938
939; CHECK-LABEL: @test56
940; CHECK: xxmrgld v2, v2, v3
941; CHECK: blr
942
943; CHECK-LE-LABEL: @test56
944; CHECK-LE: xxmrghd v2, v3, v2
945; CHECK-LE: blr
946}
947
948define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
949  %v = shl <2 x i64> %a, %b
950  ret <2 x i64> %v
951
952; CHECK-LABEL: @test60
953; This should scalarize, and the current code quality is not good.
954; CHECK: stxvd2x v3, 0, r3
955; CHECK: stxvd2x v2, 0, r4
956; CHECK: sld r3, r4, r3
957; CHECK: sld r3, r4, r3
958; CHECK: lxvd2x v2, 0, r3
959; CHECK: blr
960}
961
962define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
963  %v = lshr <2 x i64> %a, %b
964  ret <2 x i64> %v
965
966; CHECK-LABEL: @test61
967; This should scalarize, and the current code quality is not good.
968; CHECK: stxvd2x v3, 0, r3
969; CHECK: stxvd2x v2, 0, r4
970; CHECK: srd r3, r4, r3
971; CHECK: srd r3, r4, r3
972; CHECK: lxvd2x v2, 0, r3
973; CHECK: blr
974}
975
976define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
977  %v = ashr <2 x i64> %a, %b
978  ret <2 x i64> %v
979
980; CHECK-LABEL: @test62
981; This should scalarize, and the current code quality is not good.
982; CHECK: stxvd2x v3, 0, r3
983; CHECK: stxvd2x v2, 0, r4
984; CHECK: srad r3, r4, r3
985; CHECK: srad r3, r4, r3
986; CHECK: lxvd2x v2, 0, r3
987; CHECK: blr
988}
989
990define double @test63(<2 x double> %a) {
991  %v = extractelement <2 x double> %a, i32 0
992  ret double %v
993
994; CHECK-REG-LABEL: @test63
995; CHECK-REG: xxlor f1, v2, v2
996; CHECK-REG: blr
997
998; CHECK-FISL-LABEL: @test63
999; CHECK-FISL: xxlor f0, v2, v2
1000; CHECK-FISL: fmr f1, f0
1001; CHECK-FISL: blr
1002
1003; CHECK-LE-LABEL: @test63
1004; CHECK-LE: xxswapd vs1, v2
1005; CHECK-LE: blr
1006}
1007
1008define double @test64(<2 x double> %a) {
1009  %v = extractelement <2 x double> %a, i32 1
1010  ret double %v
1011
1012; CHECK-REG-LABEL: @test64
1013; CHECK-REG: xxswapd vs1, v2
1014; CHECK-REG: blr
1015
1016; CHECK-FISL-LABEL: @test64
1017; CHECK-FISL: xxswapd  v2, v2
1018; CHECK-FISL: xxlor f0, v2, v2
1019; CHECK-FISL: fmr f1, f0
1020; CHECK-FISL: blr
1021
1022; CHECK-LE-LABEL: @test64
1023; CHECK-LE: xxlor f1, v2, v2
1024}
1025
1026define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
1027  %w = icmp eq <2 x i64> %a, %b
1028  ret <2 x i1> %w
1029
1030; CHECK-REG-LABEL: @test65
1031; CHECK-REG: vcmpequw v2, v2, v3
1032; CHECK-REG: blr
1033
1034; CHECK-FISL-LABEL: @test65
1035; CHECK-FISL: vcmpequw v2, v2, v3
1036; CHECK-FISL: blr
1037
1038; CHECK-LE-LABEL: @test65
1039; CHECK-LE: vcmpequd v2, v2, v3
1040; CHECK-LE: blr
1041}
1042
1043define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
1044  %w = icmp ne <2 x i64> %a, %b
1045  ret <2 x i1> %w
1046
1047; CHECK-REG-LABEL: @test66
1048; CHECK-REG: vcmpequw v2, v2, v3
1049; CHECK-REG: xxlnor v2, v2, v2
1050; CHECK-REG: blr
1051
1052; CHECK-FISL-LABEL: @test66
1053; CHECK-FISL: vcmpequw v2, v2, v3
1054; CHECK-FISL: xxlnor v2, v2, v2
1055; CHECK-FISL: blr
1056
1057; CHECK-LE-LABEL: @test66
1058; CHECK-LE: vcmpequd v2, v2, v3
1059; CHECK-LE: xxlnor v2, v2, v2
1060; CHECK-LE: blr
1061}
1062
1063define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
1064  %w = icmp ult <2 x i64> %a, %b
1065  ret <2 x i1> %w
1066
1067; CHECK-LABEL: @test67
1068; This should scalarize, and the current code quality is not good.
1069; CHECK: stxvd2x v3, 0, r3
1070; CHECK: stxvd2x v2, 0, r4
1071; CHECK: cmpld r4, r3
1072; CHECK: cmpld r6, r5
1073; CHECK: lxvd2x v2, 0, r3
1074; CHECK: blr
1075
1076; CHECK-LE-LABEL: @test67
1077; CHECK-LE: vcmpgtud v2, v3, v2
1078; CHECK-LE: blr
1079}
1080
1081define <2 x double> @test68(<2 x i32> %a) {
1082  %w = sitofp <2 x i32> %a to <2 x double>
1083  ret <2 x double> %w
1084
1085; CHECK-LABEL: @test68
1086; CHECK: xxmrghw vs0, v2, v2
1087; CHECK: xvcvsxwdp v2, vs0
1088; CHECK: blr
1089
1090; CHECK-LE-LABEL: @test68
1091; CHECK-LE: xxmrglw v2, v2, v2
1092; CHECK-LE: xvcvsxwdp v2, v2
1093; CHECK-LE: blr
1094}
1095
1096; This gets scalarized so the code isn't great
1097define <2 x double> @test69(<2 x i16> %a) {
1098  %w = sitofp <2 x i16> %a to <2 x double>
1099  ret <2 x double> %w
1100
1101; CHECK-LABEL: @test69
1102; CHECK-DAG: lxvd2x v2, 0, r3
1103; CHECK-DAG: xvcvsxddp v2, v2
1104; CHECK: blr
1105
1106; CHECK-LE-LABEL: @test69
1107; CHECK-LE: vperm
1108; CHECK-LE: vsld
1109; CHECK-LE: vsrad
1110; CHECK-LE: xvcvsxddp v2, v2
1111; CHECK-LE: blr
1112}
1113
1114; This gets scalarized so the code isn't great
1115define <2 x double> @test70(<2 x i8> %a) {
1116  %w = sitofp <2 x i8> %a to <2 x double>
1117  ret <2 x double> %w
1118
1119; CHECK-LABEL: @test70
1120; CHECK-DAG: lxvd2x v2, 0, r3
1121; CHECK-DAG: xvcvsxddp v2, v2
1122; CHECK: blr
1123
1124; CHECK-LE-LABEL: @test70
1125; CHECK-LE: vperm
1126; CHECK-LE: vsld
1127; CHECK-LE: vsrad
1128; CHECK-LE: xvcvsxddp v2, v2
1129; CHECK-LE: blr
1130}
1131
1132; This gets scalarized so the code isn't great
1133define <2 x i32> @test80(i32 %v) {
1134  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
1135  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
1136  %i = add <2 x i32> %b2, <i32 2, i32 3>
1137  ret <2 x i32> %i
1138
1139; CHECK-REG-LABEL: @test80
1140; CHECK-REG-DAG: stw r3, -16(r1)
1141; CHECK-REG-DAG: addi r4, r1, -16
1142; CHECK-REG: addis r3, r2, .LCPI65_0@toc@ha
1143; CHECK-REG-DAG: addi r3, r3, .LCPI65_0@toc@l
1144; CHECK-REG-DAG: lxvw4x vs0, 0, r4
1145; CHECK-REG-DAG: lxvw4x v3, 0, r3
1146; CHECK-REG: xxspltw v2, vs0, 0
1147; CHECK-REG: vadduwm v2, v2, v3
1148; CHECK-REG-NOT: stxvw4x
1149; CHECK-REG: blr
1150
1151; CHECK-FISL-LABEL: @test80
1152; CHECK-FISL: mr r4, r3
1153; CHECK-FISL: stw r4, -16(r1)
1154; CHECK-FISL: addi r3, r1, -16
1155; CHECK-FISL-DAG: lxvw4x vs0, 0, r3
1156; CHECK-FISL-DAG: xxspltw v2, vs0, 0
1157; CHECK-FISL: addis r3, r2, .LCPI65_0@toc@ha
1158; CHECK-FISL: addi r3, r3, .LCPI65_0@toc@l
1159; CHECK-FISL-DAG: lxvw4x v3, 0, r3
1160; CHECK-FISL: vadduwm
1161; CHECK-FISL-NOT: stxvw4x
1162; CHECK-FISL: blr
1163
1164; CHECK-LE-LABEL: @test80
1165; CHECK-LE-DAG: mtvsrd f0, r3
1166; CHECK-LE-DAG: xxswapd  vs0, vs0
1167; CHECK-LE-DAG: addi r3, r4, .LCPI65_0@toc@l
1168; CHECK-LE-DAG: lvx v3, 0, r3
1169; CHECK-LE-DAG: xxspltw v2, vs0, 3
1170; CHECK-LE-NOT: xxswapd v3,
1171; CHECK-LE: vadduwm v2, v2, v3
1172; CHECK-LE: blr
1173}
1174
1175define <2 x double> @test81(<4 x float> %b) {
1176  %w = bitcast <4 x float> %b to <2 x double>
1177  ret <2 x double> %w
1178
1179; CHECK-LABEL: @test81
1180; CHECK: blr
1181
1182; CHECK-LE-LABEL: @test81
1183; CHECK-LE: blr
1184}
1185
1186define double @test82(double %a, double %b, double %c, double %d) {
1187entry:
1188  %m = fcmp oeq double %c, %d
1189  %v = select i1 %m, double %a, double %b
1190  ret double %v
1191
1192; CHECK-REG-LABEL: @test82
1193; CHECK-REG: xscmpudp cr0, f3, f4
1194; CHECK-REG: beqlr cr0
1195
1196; CHECK-FISL-LABEL: @test82
1197; CHECK-FISL: xscmpudp cr0, f3, f4
1198; CHECK-FISL: beq cr0
1199
1200; CHECK-LE-LABEL: @test82
1201; CHECK-LE: xscmpudp cr0, f3, f4
1202; CHECK-LE: beqlr cr0
1203}
1204