1; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
2; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
3; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
4; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
5; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s
6
7define double @test1(double %a, double %b) {
8entry:
9  %v = fmul double %a, %b
10  ret double %v
11
12; CHECK-LABEL: @test1
13; CHECK: xsmuldp 1, 1, 2
14; CHECK: blr
15
16; CHECK-LE-LABEL: @test1
17; CHECK-LE: xsmuldp 1, 1, 2
18; CHECK-LE: blr
19}
20
21define double @test2(double %a, double %b) {
22entry:
23  %v = fdiv double %a, %b
24  ret double %v
25
26; CHECK-LABEL: @test2
27; CHECK: xsdivdp 1, 1, 2
28; CHECK: blr
29
30; CHECK-LE-LABEL: @test2
31; CHECK-LE: xsdivdp 1, 1, 2
32; CHECK-LE: blr
33}
34
35define double @test3(double %a, double %b) {
36entry:
37  %v = fadd double %a, %b
38  ret double %v
39
40; CHECK-LABEL: @test3
41; CHECK: xsadddp 1, 1, 2
42; CHECK: blr
43
44; CHECK-LE-LABEL: @test3
45; CHECK-LE: xsadddp 1, 1, 2
46; CHECK-LE: blr
47}
48
49define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
50entry:
51  %v = fadd <2 x double> %a, %b
52  ret <2 x double> %v
53
54; CHECK-LABEL: @test4
55; CHECK: xvadddp 34, 34, 35
56; CHECK: blr
57
58; CHECK-LE-LABEL: @test4
59; CHECK-LE: xvadddp 34, 34, 35
60; CHECK-LE: blr
61}
62
63define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
64entry:
65  %v = xor <4 x i32> %a, %b
66  ret <4 x i32> %v
67
68; CHECK-REG-LABEL: @test5
69; CHECK-REG: xxlxor 34, 34, 35
70; CHECK-REG: blr
71
72; CHECK-FISL-LABEL: @test5
73; CHECK-FISL: vor 4, 2, 2
74; CHECK-FISL: vor 5, 3, 3
75; CHECK-FISL: xxlxor 36, 36, 37
76; CHECK-FISL: vor 2, 4, 4
77; CHECK-FISL: blr
78
79; CHECK-LE-LABEL: @test5
80; CHECK-LE: xxlxor 34, 34, 35
81; CHECK-LE: blr
82}
83
84define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
85entry:
86  %v = xor <8 x i16> %a, %b
87  ret <8 x i16> %v
88
89; CHECK-REG-LABEL: @test6
90; CHECK-REG: xxlxor 34, 34, 35
91; CHECK-REG: blr
92
93; CHECK-FISL-LABEL: @test6
94; CHECK-FISL: vor 4, 2, 2
95; CHECK-FISL: vor 5, 3, 3
96; CHECK-FISL: xxlxor 36, 36, 37
97; CHECK-FISL: vor 2, 4, 4
98; CHECK-FISL: blr
99
100; CHECK-LE-LABEL: @test6
101; CHECK-LE: xxlxor 34, 34, 35
102; CHECK-LE: blr
103}
104
105define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
106entry:
107  %v = xor <16 x i8> %a, %b
108  ret <16 x i8> %v
109
110; CHECK-REG-LABEL: @test7
111; CHECK-REG: xxlxor 34, 34, 35
112; CHECK-REG: blr
113
114; CHECK-FISL-LABEL: @test7
115; CHECK-FISL: vor 4, 2, 2
116; CHECK-FISL: vor 5, 3, 3
117; CHECK-FISL: xxlxor 36, 36, 37
118; CHECK-FISL: vor 2, 4, 4
119; CHECK-FISL: blr
120
121; CHECK-LE-LABEL: @test7
122; CHECK-LE: xxlxor 34, 34, 35
123; CHECK-LE: blr
124}
125
126define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
127entry:
128  %v = or <4 x i32> %a, %b
129  ret <4 x i32> %v
130
131; CHECK-REG-LABEL: @test8
132; CHECK-REG: xxlor 34, 34, 35
133; CHECK-REG: blr
134
135; CHECK-FISL-LABEL: @test8
136; CHECK-FISL: vor 4, 2, 2
137; CHECK-FISL: vor 5, 3, 3
138; CHECK-FISL: xxlor 36, 36, 37
139; CHECK-FISL: vor 2, 4, 4
140; CHECK-FISL: blr
141
142; CHECK-LE-LABEL: @test8
143; CHECK-LE: xxlor 34, 34, 35
144; CHECK-LE: blr
145}
146
147define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
148entry:
149  %v = or <8 x i16> %a, %b
150  ret <8 x i16> %v
151
152; CHECK-REG-LABEL: @test9
153; CHECK-REG: xxlor 34, 34, 35
154; CHECK-REG: blr
155
156; CHECK-FISL-LABEL: @test9
157; CHECK-FISL: vor 4, 2, 2
158; CHECK-FISL: vor 5, 3, 3
159; CHECK-FISL: xxlor 36, 36, 37
160; CHECK-FISL: vor 2, 4, 4
161; CHECK-FISL: blr
162
163; CHECK-LE-LABEL: @test9
164; CHECK-LE: xxlor 34, 34, 35
165; CHECK-LE: blr
166}
167
168define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
169entry:
170  %v = or <16 x i8> %a, %b
171  ret <16 x i8> %v
172
173; CHECK-REG-LABEL: @test10
174; CHECK-REG: xxlor 34, 34, 35
175; CHECK-REG: blr
176
177; CHECK-FISL-LABEL: @test10
178; CHECK-FISL: vor 4, 2, 2
179; CHECK-FISL: vor 5, 3, 3
180; CHECK-FISL: xxlor 36, 36, 37
181; CHECK-FISL: vor 2, 4, 4
182; CHECK-FISL: blr
183
184; CHECK-LE-LABEL: @test10
185; CHECK-LE: xxlor 34, 34, 35
186; CHECK-LE: blr
187}
188
189define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
190entry:
191  %v = and <4 x i32> %a, %b
192  ret <4 x i32> %v
193
194; CHECK-REG-LABEL: @test11
195; CHECK-REG: xxland 34, 34, 35
196; CHECK-REG: blr
197
198; CHECK-FISL-LABEL: @test11
199; CHECK-FISL: vor 4, 2, 2
200; CHECK-FISL: vor 5, 3, 3
201; CHECK-FISL: xxland 36, 36, 37
202; CHECK-FISL: vor 2, 4, 4
203; CHECK-FISL: blr
204
205; CHECK-LE-LABEL: @test11
206; CHECK-LE: xxland 34, 34, 35
207; CHECK-LE: blr
208}
209
210define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
211entry:
212  %v = and <8 x i16> %a, %b
213  ret <8 x i16> %v
214
215; CHECK-REG-LABEL: @test12
216; CHECK-REG: xxland 34, 34, 35
217; CHECK-REG: blr
218
219; CHECK-FISL-LABEL: @test12
220; CHECK-FISL: vor 4, 2, 2
221; CHECK-FISL: vor 5, 3, 3
222; CHECK-FISL: xxland 36, 36, 37
223; CHECK-FISL: vor 2, 4, 4
224; CHECK-FISL: blr
225
226; CHECK-LE-LABEL: @test12
227; CHECK-LE: xxland 34, 34, 35
228; CHECK-LE: blr
229}
230
231define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
232entry:
233  %v = and <16 x i8> %a, %b
234  ret <16 x i8> %v
235
236; CHECK-REG-LABEL: @test13
237; CHECK-REG: xxland 34, 34, 35
238; CHECK-REG: blr
239
240; CHECK-FISL-LABEL: @test13
241; CHECK-FISL: vor 4, 2, 2
242; CHECK-FISL: vor 5, 3, 3
243; CHECK-FISL: xxland 36, 36, 37
244; CHECK-FISL: vor 2, 4, 4
245; CHECK-FISL: blr
246
247; CHECK-LE-LABEL: @test13
248; CHECK-LE: xxland 34, 34, 35
249; CHECK-LE: blr
250}
251
252define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
253entry:
254  %v = or <4 x i32> %a, %b
255  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
256  ret <4 x i32> %w
257
258; CHECK-REG-LABEL: @test14
259; CHECK-REG: xxlnor 34, 34, 35
260; CHECK-REG: blr
261
262; CHECK-FISL-LABEL: @test14
263; CHECK-FISL: vor 4, 2, 2
264; CHECK-FISL: vor 5, 3, 3
265; CHECK-FISL: xxlor 36, 36, 37
266; CHECK-FISL: vor 0, 4, 4
267; CHECK-FISL: vor 4, 2, 2
268; CHECK-FISL: vor 5, 3, 3
269; CHECK-FISL: xxlnor 36, 36, 37
270; CHECK-FISL: vor 2, 4, 4
271; CHECK-FISL: lis 0, -1
272; CHECK-FISL: ori 0, 0, 65520
273; CHECK-FISL: stvx 0, 1, 0
274; CHECK-FISL: blr
275
276; CHECK-LE-LABEL: @test14
277; CHECK-LE: xxlnor 34, 34, 35
278; CHECK-LE: blr
279}
280
281define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
282entry:
283  %v = or <8 x i16> %a, %b
284  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
285  ret <8 x i16> %w
286
287; CHECK-REG-LABEL: @test15
288; CHECK-REG: xxlnor 34, 34, 35
289; CHECK-REG: blr
290
291; CHECK-FISL-LABEL: @test15
292; CHECK-FISL: vor 4, 2, 2
293; CHECK-FISL: vor 5, 3, 3
294; CHECK-FISL: xxlor 36, 36, 37
295; CHECK-FISL: vor 0, 4, 4
296; CHECK-FISL: vor 4, 2, 2
297; CHECK-FISL: vor 5, 3, 3
298; CHECK-FISL: xxlnor 36, 36, 37
299; CHECK-FISL: vor 2, 4, 4
300; CHECK-FISL: lis 0, -1
301; CHECK-FISL: ori 0, 0, 65520
302; CHECK-FISL: stvx 0, 1, 0
303; CHECK-FISL: blr
304
305; CHECK-LE-LABEL: @test15
306; CHECK-LE: xxlnor 34, 34, 35
307; CHECK-LE: blr
308}
309
310define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
311entry:
312  %v = or <16 x i8> %a, %b
313  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
314  ret <16 x i8> %w
315
316; CHECK-REG-LABEL: @test16
317; CHECK-REG: xxlnor 34, 34, 35
318; CHECK-REG: blr
319
320; CHECK-FISL-LABEL: @test16
321; CHECK-FISL: vor 4, 2, 2
322; CHECK-FISL: vor 5, 3, 3
323; CHECK-FISL: xxlor 36, 36, 37
324; CHECK-FISL: vor 0, 4, 4
325; CHECK-FISL: vor 4, 2, 2
326; CHECK-FISL: vor 5, 3, 3
327; CHECK-FISL: xxlnor 36, 36, 37
328; CHECK-FISL: vor 2, 4, 4
329; CHECK-FISL: lis 0, -1
330; CHECK-FISL: ori 0, 0, 65520
331; CHECK-FISL: stvx 0, 1, 0
332; CHECK-FISL: blr
333
334; CHECK-LE-LABEL: @test16
335; CHECK-LE: xxlnor 34, 34, 35
336; CHECK-LE: blr
337}
338
339define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
340entry:
341  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
342  %v = and <4 x i32> %a, %w
343  ret <4 x i32> %v
344
345; CHECK-REG-LABEL: @test17
346; CHECK-REG: xxlandc 34, 34, 35
347; CHECK-REG: blr
348
349; CHECK-FISL-LABEL: @test17
350; CHECK-FISL: vspltisb 4, -1
351; CHECK-FISL: vor 5, 3, 3
352; CHECK-FISL: vor 0, 4, 4
353; CHECK-FISL: xxlxor 37, 37, 32
354; CHECK-FISL: vor 3, 5, 5
355; CHECK-FISL: vor 5, 2, 2
356; CHECK-FISL: vor 0, 3, 3
357; CHECK-FISL: xxland 37, 37, 32
358; CHECK-FISL: vor 2, 5, 5
359; CHECK-FISL: blr
360
361; CHECK-LE-LABEL: @test17
362; CHECK-LE: xxlandc 34, 34, 35
363; CHECK-LE: blr
364}
365
366define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
367entry:
368  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
369  %v = and <8 x i16> %a, %w
370  ret <8 x i16> %v
371
372; CHECK-REG-LABEL: @test18
373; CHECK-REG: xxlandc 34, 34, 35
374; CHECK-REG: blr
375
376; CHECK-FISL-LABEL: @test18
377; CHECK-FISL: vspltisb 4, -1
378; CHECK-FISL: vor 5, 3, 3
379; CHECK-FISL: vor 0, 4, 4
380; CHECK-FISL: xxlxor 37, 37, 32
381; CHECK-FISL: vor 4, 5, 5
382; CHECK-FISL: vor 5, 2, 2
383; CHECK-FISL: vor 0, 3, 3
384; CHECK-FISL: xxlandc 37, 37, 32
385; CHECK-FISL: vor 2, 5, 5
386; CHECK-FISL: lis 0, -1
387; CHECK-FISL: ori 0, 0, 65520
388; CHECK-FISL: stvx 4, 1, 0
389; CHECK-FISL: blr
390
391; CHECK-LE-LABEL: @test18
392; CHECK-LE: xxlandc 34, 34, 35
393; CHECK-LE: blr
394}
395
396define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
397entry:
398  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
399  %v = and <16 x i8> %a, %w
400  ret <16 x i8> %v
401
402; CHECK-REG-LABEL: @test19
403; CHECK-REG: xxlandc 34, 34, 35
404; CHECK-REG: blr
405
406; CHECK-FISL-LABEL: @test19
407; CHECK-FISL: vspltisb 4, -1
408; CHECK-FISL: vor 5, 3, 3
409; CHECK-FISL: vor 0, 4, 4
410; CHECK-FISL: xxlxor 37, 37, 32
411; CHECK-FISL: vor 4, 5, 5
412; CHECK-FISL: vor 5, 2, 2
413; CHECK-FISL: vor 0, 3, 3
414; CHECK-FISL: xxlandc 37, 37, 32
415; CHECK-FISL: vor 2, 5, 5
416; CHECK-FISL: lis 0, -1
417; CHECK-FISL: ori 0, 0, 65520
418; CHECK-FISL: stvx 4, 1, 0
419; CHECK-FISL: blr
420
421; CHECK-LE-LABEL: @test19
422; CHECK-LE: xxlandc 34, 34, 35
423; CHECK-LE: blr
424}
425
426define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
427entry:
428  %m = icmp eq <4 x i32> %c, %d
429  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
430  ret <4 x i32> %v
431
432; CHECK-REG-LABEL: @test20
433; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
434; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
435; CHECK-REG: blr
436
437; CHECK-FISL-LABEL: @test20
438; CHECK-FISL: vcmpequw 4, 4, 5
439; CHECK-FISL: vor 0, 3, 3
440; CHECK-FISL: vor 1, 2, 2
441; CHECK-FISL: vor 6, 4, 4
442; CHECK-FISL: xxsel 32, 32, 33, 38
443; CHECK-FISL: vor 2, 0, 0
444; CHECK-FISL: blr
445
446; CHECK-LE-LABEL: @test20
447; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
448; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
449; CHECK-LE: blr
450}
451
452define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
453entry:
454  %m = fcmp oeq <4 x float> %c, %d
455  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
456  ret <4 x float> %v
457
458; CHECK-REG-LABEL: @test21
459; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
460; CHECK-REG: xxsel 34, 35, 34, [[V1]]
461; CHECK-REG: blr
462
463; CHECK-FISL-LABEL: @test21
464; CHECK-FISL: vor 0, 5, 5
465; CHECK-FISL: vor 1, 4, 4
466; CHECK-FISL: vor 6, 3, 3
467; CHECK-FISL: vor 7, 2, 2
468; CHECK-FISL: xvcmpeqsp 32, 33, 32
469; CHECK-FISL: xxsel 32, 38, 39, 32
470; CHECK-FISL: vor 2, 0, 0
471; CHECK-FISL: blr
472
473; CHECK-LE-LABEL: @test21
474; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
475; CHECK-LE: xxsel 34, 35, 34, [[V1]]
476; CHECK-LE: blr
477}
478
479define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
480entry:
481  %m = fcmp ueq <4 x float> %c, %d
482  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
483  ret <4 x float> %v
484
485; CHECK-REG-LABEL: @test22
486; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
487; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
488; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
489; CHECK-REG-DAG: xxlnor
490; CHECK-REG-DAG: xxlnor
491; CHECK-REG-DAG: xxlor
492; CHECK-REG-DAG: xxlor
493; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
494; CHECK-REG: blr
495
496; CHECK-FISL-LABEL: @test22
497; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32
498; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32
499; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33
500; CHECK-FISL-DAG: xxlnor
501; CHECK-FISL-DAG: xxlnor
502; CHECK-FISL-DAG: xxlor
503; CHECK-FISL-DAG: xxlor
504; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}}
505; CHECK-FISL: blr
506
507; CHECK-LE-LABEL: @test22
508; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
509; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
510; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
511; CHECK-LE-DAG: xxlnor
512; CHECK-LE-DAG: xxlnor
513; CHECK-LE-DAG: xxlor
514; CHECK-LE-DAG: xxlor
515; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
516; CHECK-LE: blr
517}
518
519define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
520entry:
521  %m = icmp eq <8 x i16> %c, %d
522  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
523  ret <8 x i16> %v
524
525; CHECK-REG-LABEL: @test23
526; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
527; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
528; CHECK-REG: blr
529
530; CHECK-FISL-LABEL: @test23
531; CHECK-FISL: vcmpequh 4, 4, 5
532; CHECK-FISL: vor 0, 3, 3
533; CHECK-FISL: vor 1, 2, 2
534; CHECK-FISL: vor 6, 4, 4
535; CHECK-FISL: xxsel 32, 32, 33, 38
536; CHECK-FISL: vor 2, 0,
537; CHECK-FISL: blr
538
539; CHECK-LE-LABEL: @test23
540; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
541; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
542; CHECK-LE: blr
543}
544
545define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
546entry:
547  %m = icmp eq <16 x i8> %c, %d
548  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
549  ret <16 x i8> %v
550
551; CHECK-REG-LABEL: @test24
552; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
553; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
554; CHECK-REG: blr
555
556; CHECK-FISL-LABEL: @test24
557; CHECK-FISL: vcmpequb 4, 4, 5
558; CHECK-FISL: vor 0, 3, 3
559; CHECK-FISL: vor 1, 2, 2
560; CHECK-FISL: vor 6, 4, 4
561; CHECK-FISL: xxsel 32, 32, 33, 38
562; CHECK-FISL: vor 2, 0, 0
563; CHECK-FISL: blr
564
565; CHECK-LE-LABEL: @test24
566; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
567; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
568; CHECK-LE: blr
569}
570
571define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
572entry:
573  %m = fcmp oeq <2 x double> %c, %d
574  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
575  ret <2 x double> %v
576
577; CHECK-LABEL: @test25
578; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
579; CHECK: xxsel 34, 35, 34, [[V1]]
580; CHECK: blr
581
582; CHECK-LE-LABEL: @test25
583; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
584; CHECK-LE: xxsel 34, 35, 34, [[V1]]
585; CHECK-LE: blr
586}
587
588define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
589  %v = add <2 x i64> %a, %b
590  ret <2 x i64> %v
591
592; CHECK-LABEL: @test26
593
594; Make sure we use only two stores (one for each operand).
595; CHECK: stxvd2x 35,
596; CHECK: stxvd2x 34,
597; CHECK-NOT: stxvd2x
598
599; FIXME: The code quality here is not good; just make sure we do something for now.
600; CHECK: add
601; CHECK: add
602; CHECK: blr
603
604; CHECK-LE: vaddudm 2, 2, 3
605; CHECK-LE: blr
606}
607
608define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
609  %v = and <2 x i64> %a, %b
610  ret <2 x i64> %v
611
612; CHECK-LABEL: @test27
613; CHECK: xxland 34, 34, 35
614; CHECK: blr
615
616; CHECK-LE-LABEL: @test27
617; CHECK-LE: xxland 34, 34, 35
618; CHECK-LE: blr
619}
620
621define <2 x double> @test28(<2 x double>* %a) {
622  %v = load <2 x double>, <2 x double>* %a, align 16
623  ret <2 x double> %v
624
625; CHECK-LABEL: @test28
626; CHECK: lxvd2x 34, 0, 3
627; CHECK: blr
628
629; CHECK-LE-LABEL: @test28
630; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
631; CHECK-LE: xxswapd 34, [[V1]]
632; CHECK-LE: blr
633}
634
635define void @test29(<2 x double>* %a, <2 x double> %b) {
636  store <2 x double> %b, <2 x double>* %a, align 16
637  ret void
638
639; CHECK-LABEL: @test29
640; CHECK: stxvd2x 34, 0, 3
641; CHECK: blr
642
643; CHECK-LE-LABEL: @test29
644; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
645; CHECK-LE: stxvd2x [[V1]], 0, 3
646; CHECK-LE: blr
647}
648
649define <2 x double> @test28u(<2 x double>* %a) {
650  %v = load <2 x double>, <2 x double>* %a, align 8
651  ret <2 x double> %v
652
653; CHECK-LABEL: @test28u
654; CHECK: lxvd2x 34, 0, 3
655; CHECK: blr
656
657; CHECK-LE-LABEL: @test28u
658; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
659; CHECK-LE: xxswapd 34, [[V1]]
660; CHECK-LE: blr
661}
662
663define void @test29u(<2 x double>* %a, <2 x double> %b) {
664  store <2 x double> %b, <2 x double>* %a, align 8
665  ret void
666
667; CHECK-LABEL: @test29u
668; CHECK: stxvd2x 34, 0, 3
669; CHECK: blr
670
671; CHECK-LE-LABEL: @test29u
672; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
673; CHECK-LE: stxvd2x [[V1]], 0, 3
674; CHECK-LE: blr
675}
676
677define <2 x i64> @test30(<2 x i64>* %a) {
678  %v = load <2 x i64>, <2 x i64>* %a, align 16
679  ret <2 x i64> %v
680
681; CHECK-REG-LABEL: @test30
682; CHECK-REG: lxvd2x 34, 0, 3
683; CHECK-REG: blr
684
685; CHECK-FISL-LABEL: @test30
686; CHECK-FISL: lxvd2x 0, 0, 3
687; CHECK-FISL: xxlor 34, 0, 0
688; CHECK-FISL: vor 3, 2, 2
689; CHECK-FISL: vor 2, 3, 3
690; CHECK-FISL: blr
691
692; CHECK-LE-LABEL: @test30
693; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
694; CHECK-LE: xxswapd 34, [[V1]]
695; CHECK-LE: blr
696}
697
698define void @test31(<2 x i64>* %a, <2 x i64> %b) {
699  store <2 x i64> %b, <2 x i64>* %a, align 16
700  ret void
701
702; CHECK-LABEL: @test31
703; CHECK: stxvd2x 34, 0, 3
704; CHECK: blr
705
706; CHECK-LE-LABEL: @test31
707; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
708; CHECK-LE: stxvd2x [[V1]], 0, 3
709; CHECK-LE: blr
710}
711
712define <4 x float> @test32(<4 x float>* %a) {
713  %v = load <4 x float>, <4 x float>* %a, align 16
714  ret <4 x float> %v
715
716; CHECK-REG-LABEL: @test32
717; CHECK-REG: lxvw4x 34, 0, 3
718; CHECK-REG: blr
719
720; CHECK-FISL-LABEL: @test32
721; CHECK-FISL: lxvw4x 0, 0, 3
722; CHECK-FISL: xxlor 34, 0, 0
723; CHECK-FISL: blr
724
725; CHECK-LE-LABEL: @test32
726; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
727; CHECK-LE: xxswapd 34, [[V1]]
728; CHECK-LE: blr
729}
730
731define void @test33(<4 x float>* %a, <4 x float> %b) {
732  store <4 x float> %b, <4 x float>* %a, align 16
733  ret void
734
735; CHECK-REG-LABEL: @test33
736; CHECK-REG: stxvw4x 34, 0, 3
737; CHECK-REG: blr
738
739; CHECK-FISL-LABEL: @test33
740; CHECK-FISL: vor 3, 2, 2
741; CHECK-FISL: stxvw4x 35, 0, 3
742; CHECK-FISL: blr
743
744; CHECK-LE-LABEL: @test33
745; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
746; CHECK-LE: stxvd2x [[V1]], 0, 3
747; CHECK-LE: blr
748}
749
750define <4 x float> @test32u(<4 x float>* %a) {
751  %v = load <4 x float>, <4 x float>* %a, align 8
752  ret <4 x float> %v
753
754; CHECK-LABEL: @test32u
755; CHECK-DAG: lvsl
756; CHECK-DAG: lvx
757; CHECK-DAG: lvx
758; CHECK: vperm 2,
759; CHECK: blr
760
761; CHECK-LE-LABEL: @test32u
762; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
763; CHECK-LE: xxswapd 34, [[V1]]
764; CHECK-LE: blr
765}
766
767define void @test33u(<4 x float>* %a, <4 x float> %b) {
768  store <4 x float> %b, <4 x float>* %a, align 8
769  ret void
770
771; CHECK-REG-LABEL: @test33u
772; CHECK-REG: stxvw4x 34, 0, 3
773; CHECK-REG: blr
774
775; CHECK-FISL-LABEL: @test33u
776; CHECK-FISL: vor 3, 2, 2
777; CHECK-FISL: stxvw4x 35, 0, 3
778; CHECK-FISL: blr
779
780; CHECK-LE-LABEL: @test33u
781; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
782; CHECK-LE: stxvd2x [[V1]], 0, 3
783; CHECK-LE: blr
784}
785
786define <4 x i32> @test34(<4 x i32>* %a) {
787  %v = load <4 x i32>, <4 x i32>* %a, align 16
788  ret <4 x i32> %v
789
790; CHECK-REG-LABEL: @test34
791; CHECK-REG: lxvw4x 34, 0, 3
792; CHECK-REG: blr
793
794; CHECK-FISL-LABEL: @test34
795; CHECK-FISL: lxvw4x 0, 0, 3
796; CHECK-FISL: xxlor 34, 0, 0
797; CHECK-FISL: vor 3, 2, 2
798; CHECK-FISL: vor 2, 3, 3
799; CHECK-FISL: blr
800
801; CHECK-LE-LABEL: @test34
802; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
803; CHECK-LE: xxswapd 34, [[V1]]
804; CHECK-LE: blr
805}
806
807define void @test35(<4 x i32>* %a, <4 x i32> %b) {
808  store <4 x i32> %b, <4 x i32>* %a, align 16
809  ret void
810
811; CHECK-REG-LABEL: @test35
812; CHECK-REG: stxvw4x 34, 0, 3
813; CHECK-REG: blr
814
815; CHECK-FISL-LABEL: @test35
816; CHECK-FISL: vor 3, 2, 2
817; CHECK-FISL: stxvw4x 35, 0, 3
818; CHECK-FISL: blr
819
820; CHECK-LE-LABEL: @test35
821; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
822; CHECK-LE: stxvd2x [[V1]], 0, 3
823; CHECK-LE: blr
824}
825
826define <2 x double> @test40(<2 x i64> %a) {
827  %v = uitofp <2 x i64> %a to <2 x double>
828  ret <2 x double> %v
829
830; CHECK-LABEL: @test40
831; CHECK: xvcvuxddp 34, 34
832; CHECK: blr
833
834; CHECK-LE-LABEL: @test40
835; CHECK-LE: xvcvuxddp 34, 34
836; CHECK-LE: blr
837}
838
839define <2 x double> @test41(<2 x i64> %a) {
840  %v = sitofp <2 x i64> %a to <2 x double>
841  ret <2 x double> %v
842
843; CHECK-LABEL: @test41
844; CHECK: xvcvsxddp 34, 34
845; CHECK: blr
846
847; CHECK-LE-LABEL: @test41
848; CHECK-LE: xvcvsxddp 34, 34
849; CHECK-LE: blr
850}
851
852define <2 x i64> @test42(<2 x double> %a) {
853  %v = fptoui <2 x double> %a to <2 x i64>
854  ret <2 x i64> %v
855
856; CHECK-LABEL: @test42
857; CHECK: xvcvdpuxds 34, 34
858; CHECK: blr
859
860; CHECK-LE-LABEL: @test42
861; CHECK-LE: xvcvdpuxds 34, 34
862; CHECK-LE: blr
863}
864
865define <2 x i64> @test43(<2 x double> %a) {
866  %v = fptosi <2 x double> %a to <2 x i64>
867  ret <2 x i64> %v
868
869; CHECK-LABEL: @test43
870; CHECK: xvcvdpsxds 34, 34
871; CHECK: blr
872
873; CHECK-LE-LABEL: @test43
874; CHECK-LE: xvcvdpsxds 34, 34
875; CHECK-LE: blr
876}
877
878define <2 x float> @test44(<2 x i64> %a) {
879  %v = uitofp <2 x i64> %a to <2 x float>
880  ret <2 x float> %v
881
882; CHECK-LABEL: @test44
883; FIXME: The code quality here looks pretty bad.
884; CHECK: blr
885}
886
887define <2 x float> @test45(<2 x i64> %a) {
888  %v = sitofp <2 x i64> %a to <2 x float>
889  ret <2 x float> %v
890
891; CHECK-LABEL: @test45
892; FIXME: The code quality here looks pretty bad.
893; CHECK: blr
894}
895
896define <2 x i64> @test46(<2 x float> %a) {
897  %v = fptoui <2 x float> %a to <2 x i64>
898  ret <2 x i64> %v
899
900; CHECK-LABEL: @test46
901; FIXME: The code quality here looks pretty bad.
902; CHECK: blr
903}
904
905define <2 x i64> @test47(<2 x float> %a) {
906  %v = fptosi <2 x float> %a to <2 x i64>
907  ret <2 x i64> %v
908
909; CHECK-LABEL: @test47
910; FIXME: The code quality here looks pretty bad.
911; CHECK: blr
912}
913
914define <2 x double> @test50(double* %a) {
915  %v = load double, double* %a, align 8
916  %w = insertelement <2 x double> undef, double %v, i32 0
917  %x = insertelement <2 x double> %w, double %v, i32 1
918  ret <2 x double> %x
919
920; CHECK-LABEL: @test50
921; CHECK: lxvdsx 34, 0, 3
922; CHECK: blr
923
924; CHECK-LE-LABEL: @test50
925; CHECK-LE: lxvdsx 34, 0, 3
926; CHECK-LE: blr
927}
928
929define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
930  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
931  ret <2 x double> %v
932
933; CHECK-LABEL: @test51
934; CHECK: xxspltd 34, 34, 0
935; CHECK: blr
936
937; CHECK-LE-LABEL: @test51
938; CHECK-LE: xxspltd 34, 34, 1
939; CHECK-LE: blr
940}
941
942define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
943  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
944  ret <2 x double> %v
945
946; CHECK-LABEL: @test52
947; CHECK: xxmrghd 34, 34, 35
948; CHECK: blr
949
950; CHECK-LE-LABEL: @test52
951; CHECK-LE: xxmrgld 34, 35, 34
952; CHECK-LE: blr
953}
954
955define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
956  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
957  ret <2 x double> %v
958
959; CHECK-LABEL: @test53
960; CHECK: xxmrghd 34, 35, 34
961; CHECK: blr
962
963; CHECK-LE-LABEL: @test53
964; CHECK-LE: xxmrgld 34, 34, 35
965; CHECK-LE: blr
966}
967
968define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
969  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
970  ret <2 x double> %v
971
972; CHECK-LABEL: @test54
973; CHECK: xxpermdi 34, 34, 35, 2
974; CHECK: blr
975
976; CHECK-LE-LABEL: @test54
977; CHECK-LE: xxpermdi 34, 35, 34, 2
978; CHECK-LE: blr
979}
980
981define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
982  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
983  ret <2 x double> %v
984
985; CHECK-LABEL: @test55
986; CHECK: xxmrgld 34, 34, 35
987; CHECK: blr
988
989; CHECK-LE-LABEL: @test55
990; CHECK-LE: xxmrghd 34, 35, 34
991; CHECK-LE: blr
992}
993
994define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
995  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
996  ret <2 x i64> %v
997
998; CHECK-LABEL: @test56
999; CHECK: xxmrgld 34, 34, 35
1000; CHECK: blr
1001
1002; CHECK-LE-LABEL: @test56
1003; CHECK-LE: xxmrghd 34, 35, 34
1004; CHECK-LE: blr
1005}
1006
1007define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
1008  %v = shl <2 x i64> %a, %b
1009  ret <2 x i64> %v
1010
1011; CHECK-LABEL: @test60
1012; This should scalarize, and the current code quality is not good.
1013; CHECK: stxvd2x
1014; CHECK: stxvd2x
1015; CHECK: sld
1016; CHECK: sld
1017; CHECK: lxvd2x
1018; CHECK: blr
1019}
1020
1021define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
1022  %v = lshr <2 x i64> %a, %b
1023  ret <2 x i64> %v
1024
1025; CHECK-LABEL: @test61
1026; This should scalarize, and the current code quality is not good.
1027; CHECK: stxvd2x
1028; CHECK: stxvd2x
1029; CHECK: srd
1030; CHECK: srd
1031; CHECK: lxvd2x
1032; CHECK: blr
1033}
1034
1035define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
1036  %v = ashr <2 x i64> %a, %b
1037  ret <2 x i64> %v
1038
1039; CHECK-LABEL: @test62
1040; This should scalarize, and the current code quality is not good.
1041; CHECK: stxvd2x
1042; CHECK: stxvd2x
1043; CHECK: srad
1044; CHECK: srad
1045; CHECK: lxvd2x
1046; CHECK: blr
1047}
1048
1049define double @test63(<2 x double> %a) {
1050  %v = extractelement <2 x double> %a, i32 0
1051  ret double %v
1052
1053; CHECK-REG-LABEL: @test63
1054; CHECK-REG: xxlor 1, 34, 34
1055; CHECK-REG: blr
1056
1057; CHECK-FISL-LABEL: @test63
1058; CHECK-FISL: xxlor 0, 34, 34
1059; CHECK-FISL: fmr 1, 0
1060; CHECK-FISL: blr
1061
1062; CHECK-LE-LABEL: @test63
1063; CHECK-LE: xxswapd 1, 34
1064; CHECK-LE: blr
1065}
1066
1067define double @test64(<2 x double> %a) {
1068  %v = extractelement <2 x double> %a, i32 1
1069  ret double %v
1070
1071; CHECK-REG-LABEL: @test64
1072; CHECK-REG: xxswapd 1, 34
1073; CHECK-REG: blr
1074
1075; CHECK-FISL-LABEL: @test64
1076; CHECK-FISL: xxswapd  34, 34
1077; CHECK-FISL: xxlor 0, 34, 34
1078; CHECK-FISL: fmr 1, 0
1079; CHECK-FISL: blr
1080
1081; CHECK-LE-LABEL: @test64
1082; CHECK-LE: xxlor 1, 34, 34
1083}
1084
1085define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
1086  %w = icmp eq <2 x i64> %a, %b
1087  ret <2 x i1> %w
1088
1089; CHECK-REG-LABEL: @test65
1090; CHECK-REG: vcmpequw 2, 2, 3
1091; CHECK-REG: blr
1092
1093; CHECK-FISL-LABEL: @test65
1094; CHECK-FISL: vor 4, 3, 3
1095; CHECK-FISL: vor 5, 2, 2
1096; CHECK-FISL: vcmpequw 4, 5, 4
1097; CHECK-FISL: vor 2, 4, 4
1098; CHECK-FISL: blr
1099
1100; CHECK-LE-LABEL: @test65
1101; CHECK-LE: vcmpequd 2, 2, 3
1102; CHECK-LE: blr
1103}
1104
1105define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
1106  %w = icmp ne <2 x i64> %a, %b
1107  ret <2 x i1> %w
1108
1109; CHECK-REG-LABEL: @test66
1110; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
1111; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1112; CHECK-REG: blr
1113
1114; CHECK-FISL-LABEL: @test66
1115; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4
1116; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1117; CHECK-FISL: blr
1118
1119; CHECK-LE-LABEL: @test66
1120; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
1121; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1122; CHECK-LE: blr
1123}
1124
1125define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
1126  %w = icmp ult <2 x i64> %a, %b
1127  ret <2 x i1> %w
1128
1129; CHECK-LABEL: @test67
1130; This should scalarize, and the current code quality is not good.
1131; CHECK: stxvd2x
1132; CHECK: stxvd2x
1133; CHECK: cmpld
1134; CHECK: cmpld
1135; CHECK: lxvd2x
1136; CHECK: blr
1137
1138; CHECK-LE-LABEL: @test67
1139; CHECK-LE: vcmpgtud 2, 3, 2
1140; CHECK-LE: blr
1141}
1142
1143define <2 x double> @test68(<2 x i32> %a) {
1144  %w = sitofp <2 x i32> %a to <2 x double>
1145  ret <2 x double> %w
1146
1147; CHECK-LABEL: @test68
1148; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1
1149; CHECK: xvcvsxwdp 34, [[V1]]
1150; CHECK: blr
1151
1152; CHECK-LE-LABEL: @test68
1153; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1
1154; CHECK-LE: xvcvsxwdp 34, [[V1]]
1155; CHECK-LE: blr
1156}
1157
1158define <2 x double> @test69(<2 x i16> %a) {
1159  %w = sitofp <2 x i16> %a to <2 x double>
1160  ret <2 x double> %w
1161
1162; CHECK-LABEL: @test69
1163; CHECK: vspltisw [[V1:[0-9]+]], 8
1164; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
1165; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
1166; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
1167; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
1168; CHECK: xvcvsxwdp 34, [[V4]]
1169; CHECK: blr
1170
1171; CHECK-LE-LABEL: @test69
1172; CHECK-LE: vspltisw [[V1:[0-9]+]], 8
1173; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
1174; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
1175; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
1176; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
1177; CHECK-LE: xvcvsxwdp 34, [[V4]]
1178; CHECK-LE: blr
1179}
1180
1181define <2 x double> @test70(<2 x i8> %a) {
1182  %w = sitofp <2 x i8> %a to <2 x double>
1183  ret <2 x double> %w
1184
1185; CHECK-LABEL: @test70
1186; CHECK: vspltisw [[V1:[0-9]+]], 12
1187; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
1188; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
1189; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]]
1190; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
1191; CHECK: xvcvsxwdp 34, [[V4]]
1192; CHECK: blr
1193
1194; CHECK-LE-LABEL: @test70
1195; CHECK-LE: vspltisw [[V1:[0-9]+]], 12
1196; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]]
1197; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]]
1198; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]]
1199; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1
1200; CHECK-LE: xvcvsxwdp 34, [[V4]]
1201; CHECK-LE: blr
1202}
1203
1204define <2 x i32> @test80(i32 %v) {
1205  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
1206  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
1207  %i = add <2 x i32> %b2, <i32 2, i32 3>
1208  ret <2 x i32> %i
1209
1210; CHECK-REG-LABEL: @test80
1211; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3
1212; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16
1213; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2
1214; CHECK-REG: std [[R1]], -8(1)
1215; CHECK-REG: std [[R3]], -16(1)
1216; CHECK-REG: lxvd2x 34, 0, [[R2]]
1217; CHECK-REG-NOT: stxvd2x
1218; CHECK-REG: blr
1219
1220; CHECK-FISL-LABEL: @test80
1221; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3
1222; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16
1223; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2
1224; CHECK-FISL-DAG: std [[R1]], -8(1)
1225; CHECK-FISL-DAG: std [[R3]], -16(1)
1226; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]]
1227; CHECK-FISL: blr
1228
1229; CHECK-LE-LABEL: @test80
1230; CHECK-LE-DAG: addi [[R1:[0-9]+]], 1, -16
1231; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
1232; CHECK-LE-DAG: lxvd2x [[V1:[0-9]+]], 0, [[R1]]
1233; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
1234; CHECK-LE-DAG: xxswapd 34, [[V1]]
1235; CHECK-LE-DAG: xxswapd 35, [[V2]]
1236; CHECK-LE: vaddudm 2, 2, 3
1237; CHECK-LE: blr
1238}
1239
1240define <2 x double> @test81(<4 x float> %b) {
1241  %w = bitcast <4 x float> %b to <2 x double>
1242  ret <2 x double> %w
1243
1244; CHECK-LABEL: @test81
1245; CHECK: blr
1246
1247; CHECK-LE-LABEL: @test81
1248; CHECK-LE: blr
1249}
1250
1251define double @test82(double %a, double %b, double %c, double %d) {
1252entry:
1253  %m = fcmp oeq double %c, %d
1254  %v = select i1 %m, double %a, double %b
1255  ret double %v
1256
1257; CHECK-REG-LABEL: @test82
1258; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
1259; CHECK-REG: beqlr [[REG]]
1260
1261; CHECK-FISL-LABEL: @test82
1262; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
1263; CHECK-FISL: beq [[REG]], {{.*}}
1264
1265; CHECK-LE-LABEL: @test82
1266; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
1267; CHECK-LE: beqlr [[REG]]
1268}
1269