1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
3; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
4; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
5; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
6; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx \
7; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
8; RUN:     -check-prefix=CHECK-REG %s
9; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 \
10; RUN:     -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 \
11; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
12; RUN:     -check-prefix=CHECK-FISL %s
13; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 \
14; RUN:     -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx \
15; RUN:     -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
16; RUN:     -check-prefix=CHECK-LE %s
17
18define double @test1(double %a, double %b) {
19; CHECK-LABEL: test1:
20; CHECK:       # %bb.0: # %entry
21; CHECK-NEXT:    xsmuldp f1, f1, f2
22; CHECK-NEXT:    blr
23;
24; CHECK-REG-LABEL: test1:
25; CHECK-REG:       # %bb.0: # %entry
26; CHECK-REG-NEXT:    xsmuldp f1, f1, f2
27; CHECK-REG-NEXT:    blr
28;
29; CHECK-FISL-LABEL: test1:
30; CHECK-FISL:       # %bb.0: # %entry
31; CHECK-FISL-NEXT:    xsmuldp f1, f1, f2
32; CHECK-FISL-NEXT:    blr
33;
34; CHECK-LE-LABEL: test1:
35; CHECK-LE:       # %bb.0: # %entry
36; CHECK-LE-NEXT:    xsmuldp f1, f1, f2
37; CHECK-LE-NEXT:    blr
38entry:
39  %v = fmul double %a, %b
40  ret double %v
41
42
43}
44
45define double @test2(double %a, double %b) {
46; CHECK-LABEL: test2:
47; CHECK:       # %bb.0: # %entry
48; CHECK-NEXT:    xsdivdp f1, f1, f2
49; CHECK-NEXT:    blr
50;
51; CHECK-REG-LABEL: test2:
52; CHECK-REG:       # %bb.0: # %entry
53; CHECK-REG-NEXT:    xsdivdp f1, f1, f2
54; CHECK-REG-NEXT:    blr
55;
56; CHECK-FISL-LABEL: test2:
57; CHECK-FISL:       # %bb.0: # %entry
58; CHECK-FISL-NEXT:    xsdivdp f1, f1, f2
59; CHECK-FISL-NEXT:    blr
60;
61; CHECK-LE-LABEL: test2:
62; CHECK-LE:       # %bb.0: # %entry
63; CHECK-LE-NEXT:    xsdivdp f1, f1, f2
64; CHECK-LE-NEXT:    blr
65entry:
66  %v = fdiv double %a, %b
67  ret double %v
68
69
70}
71
72define double @test3(double %a, double %b) {
73; CHECK-LABEL: test3:
74; CHECK:       # %bb.0: # %entry
75; CHECK-NEXT:    xsadddp f1, f1, f2
76; CHECK-NEXT:    blr
77;
78; CHECK-REG-LABEL: test3:
79; CHECK-REG:       # %bb.0: # %entry
80; CHECK-REG-NEXT:    xsadddp f1, f1, f2
81; CHECK-REG-NEXT:    blr
82;
83; CHECK-FISL-LABEL: test3:
84; CHECK-FISL:       # %bb.0: # %entry
85; CHECK-FISL-NEXT:    xsadddp f1, f1, f2
86; CHECK-FISL-NEXT:    blr
87;
88; CHECK-LE-LABEL: test3:
89; CHECK-LE:       # %bb.0: # %entry
90; CHECK-LE-NEXT:    xsadddp f1, f1, f2
91; CHECK-LE-NEXT:    blr
92entry:
93  %v = fadd double %a, %b
94  ret double %v
95
96
97}
98
99define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
100; CHECK-LABEL: test4:
101; CHECK:       # %bb.0: # %entry
102; CHECK-NEXT:    xvadddp v2, v2, v3
103; CHECK-NEXT:    blr
104;
105; CHECK-REG-LABEL: test4:
106; CHECK-REG:       # %bb.0: # %entry
107; CHECK-REG-NEXT:    xvadddp v2, v2, v3
108; CHECK-REG-NEXT:    blr
109;
110; CHECK-FISL-LABEL: test4:
111; CHECK-FISL:       # %bb.0: # %entry
112; CHECK-FISL-NEXT:    xvadddp v2, v2, v3
113; CHECK-FISL-NEXT:    blr
114;
115; CHECK-LE-LABEL: test4:
116; CHECK-LE:       # %bb.0: # %entry
117; CHECK-LE-NEXT:    xvadddp v2, v2, v3
118; CHECK-LE-NEXT:    blr
119entry:
120  %v = fadd <2 x double> %a, %b
121  ret <2 x double> %v
122
123
124}
125
126define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
127; CHECK-LABEL: test5:
128; CHECK:       # %bb.0: # %entry
129; CHECK-NEXT:    xxlxor v2, v2, v3
130; CHECK-NEXT:    blr
131;
132; CHECK-REG-LABEL: test5:
133; CHECK-REG:       # %bb.0: # %entry
134; CHECK-REG-NEXT:    xxlxor v2, v2, v3
135; CHECK-REG-NEXT:    blr
136;
137; CHECK-FISL-LABEL: test5:
138; CHECK-FISL:       # %bb.0: # %entry
139; CHECK-FISL-NEXT:    xxlxor v2, v2, v3
140; CHECK-FISL-NEXT:    blr
141;
142; CHECK-LE-LABEL: test5:
143; CHECK-LE:       # %bb.0: # %entry
144; CHECK-LE-NEXT:    xxlxor v2, v2, v3
145; CHECK-LE-NEXT:    blr
146entry:
147  %v = xor <4 x i32> %a, %b
148  ret <4 x i32> %v
149
150
151
152}
153
154define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
155; CHECK-LABEL: test6:
156; CHECK:       # %bb.0: # %entry
157; CHECK-NEXT:    xxlxor v2, v2, v3
158; CHECK-NEXT:    blr
159;
160; CHECK-REG-LABEL: test6:
161; CHECK-REG:       # %bb.0: # %entry
162; CHECK-REG-NEXT:    xxlxor v2, v2, v3
163; CHECK-REG-NEXT:    blr
164;
165; CHECK-FISL-LABEL: test6:
166; CHECK-FISL:       # %bb.0: # %entry
167; CHECK-FISL-NEXT:    xxlxor vs0, v2, v3
168; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
169; CHECK-FISL-NEXT:    blr
170;
171; CHECK-LE-LABEL: test6:
172; CHECK-LE:       # %bb.0: # %entry
173; CHECK-LE-NEXT:    xxlxor v2, v2, v3
174; CHECK-LE-NEXT:    blr
175entry:
176  %v = xor <8 x i16> %a, %b
177  ret <8 x i16> %v
178
179
180
181}
182
183define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
184; CHECK-LABEL: test7:
185; CHECK:       # %bb.0: # %entry
186; CHECK-NEXT:    xxlxor v2, v2, v3
187; CHECK-NEXT:    blr
188;
189; CHECK-REG-LABEL: test7:
190; CHECK-REG:       # %bb.0: # %entry
191; CHECK-REG-NEXT:    xxlxor v2, v2, v3
192; CHECK-REG-NEXT:    blr
193;
194; CHECK-FISL-LABEL: test7:
195; CHECK-FISL:       # %bb.0: # %entry
196; CHECK-FISL-NEXT:    xxlxor vs0, v2, v3
197; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
198; CHECK-FISL-NEXT:    blr
199;
200; CHECK-LE-LABEL: test7:
201; CHECK-LE:       # %bb.0: # %entry
202; CHECK-LE-NEXT:    xxlxor v2, v2, v3
203; CHECK-LE-NEXT:    blr
204entry:
205  %v = xor <16 x i8> %a, %b
206  ret <16 x i8> %v
207
208
209
210}
211
212define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
213; CHECK-LABEL: test8:
214; CHECK:       # %bb.0: # %entry
215; CHECK-NEXT:    xxlor v2, v2, v3
216; CHECK-NEXT:    blr
217;
218; CHECK-REG-LABEL: test8:
219; CHECK-REG:       # %bb.0: # %entry
220; CHECK-REG-NEXT:    xxlor v2, v2, v3
221; CHECK-REG-NEXT:    blr
222;
223; CHECK-FISL-LABEL: test8:
224; CHECK-FISL:       # %bb.0: # %entry
225; CHECK-FISL-NEXT:    xxlor v2, v2, v3
226; CHECK-FISL-NEXT:    blr
227;
228; CHECK-LE-LABEL: test8:
229; CHECK-LE:       # %bb.0: # %entry
230; CHECK-LE-NEXT:    xxlor v2, v2, v3
231; CHECK-LE-NEXT:    blr
232entry:
233  %v = or <4 x i32> %a, %b
234  ret <4 x i32> %v
235
236
237
238}
239
240define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
241; CHECK-LABEL: test9:
242; CHECK:       # %bb.0: # %entry
243; CHECK-NEXT:    xxlor v2, v2, v3
244; CHECK-NEXT:    blr
245;
246; CHECK-REG-LABEL: test9:
247; CHECK-REG:       # %bb.0: # %entry
248; CHECK-REG-NEXT:    xxlor v2, v2, v3
249; CHECK-REG-NEXT:    blr
250;
251; CHECK-FISL-LABEL: test9:
252; CHECK-FISL:       # %bb.0: # %entry
253; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
254; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
255; CHECK-FISL-NEXT:    blr
256;
257; CHECK-LE-LABEL: test9:
258; CHECK-LE:       # %bb.0: # %entry
259; CHECK-LE-NEXT:    xxlor v2, v2, v3
260; CHECK-LE-NEXT:    blr
261entry:
262  %v = or <8 x i16> %a, %b
263  ret <8 x i16> %v
264
265
266
267}
268
269define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
270; CHECK-LABEL: test10:
271; CHECK:       # %bb.0: # %entry
272; CHECK-NEXT:    xxlor v2, v2, v3
273; CHECK-NEXT:    blr
274;
275; CHECK-REG-LABEL: test10:
276; CHECK-REG:       # %bb.0: # %entry
277; CHECK-REG-NEXT:    xxlor v2, v2, v3
278; CHECK-REG-NEXT:    blr
279;
280; CHECK-FISL-LABEL: test10:
281; CHECK-FISL:       # %bb.0: # %entry
282; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
283; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
284; CHECK-FISL-NEXT:    blr
285;
286; CHECK-LE-LABEL: test10:
287; CHECK-LE:       # %bb.0: # %entry
288; CHECK-LE-NEXT:    xxlor v2, v2, v3
289; CHECK-LE-NEXT:    blr
290entry:
291  %v = or <16 x i8> %a, %b
292  ret <16 x i8> %v
293
294
295
296}
297
298define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
299; CHECK-LABEL: test11:
300; CHECK:       # %bb.0: # %entry
301; CHECK-NEXT:    xxland v2, v2, v3
302; CHECK-NEXT:    blr
303;
304; CHECK-REG-LABEL: test11:
305; CHECK-REG:       # %bb.0: # %entry
306; CHECK-REG-NEXT:    xxland v2, v2, v3
307; CHECK-REG-NEXT:    blr
308;
309; CHECK-FISL-LABEL: test11:
310; CHECK-FISL:       # %bb.0: # %entry
311; CHECK-FISL-NEXT:    xxland v2, v2, v3
312; CHECK-FISL-NEXT:    blr
313;
314; CHECK-LE-LABEL: test11:
315; CHECK-LE:       # %bb.0: # %entry
316; CHECK-LE-NEXT:    xxland v2, v2, v3
317; CHECK-LE-NEXT:    blr
318entry:
319  %v = and <4 x i32> %a, %b
320  ret <4 x i32> %v
321
322
323
324}
325
326define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
327; CHECK-LABEL: test12:
328; CHECK:       # %bb.0: # %entry
329; CHECK-NEXT:    xxland v2, v2, v3
330; CHECK-NEXT:    blr
331;
332; CHECK-REG-LABEL: test12:
333; CHECK-REG:       # %bb.0: # %entry
334; CHECK-REG-NEXT:    xxland v2, v2, v3
335; CHECK-REG-NEXT:    blr
336;
337; CHECK-FISL-LABEL: test12:
338; CHECK-FISL:       # %bb.0: # %entry
339; CHECK-FISL-NEXT:    xxland vs0, v2, v3
340; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
341; CHECK-FISL-NEXT:    blr
342;
343; CHECK-LE-LABEL: test12:
344; CHECK-LE:       # %bb.0: # %entry
345; CHECK-LE-NEXT:    xxland v2, v2, v3
346; CHECK-LE-NEXT:    blr
347entry:
348  %v = and <8 x i16> %a, %b
349  ret <8 x i16> %v
350
351
352
353}
354
355define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
356; CHECK-LABEL: test13:
357; CHECK:       # %bb.0: # %entry
358; CHECK-NEXT:    xxland v2, v2, v3
359; CHECK-NEXT:    blr
360;
361; CHECK-REG-LABEL: test13:
362; CHECK-REG:       # %bb.0: # %entry
363; CHECK-REG-NEXT:    xxland v2, v2, v3
364; CHECK-REG-NEXT:    blr
365;
366; CHECK-FISL-LABEL: test13:
367; CHECK-FISL:       # %bb.0: # %entry
368; CHECK-FISL-NEXT:    xxland vs0, v2, v3
369; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
370; CHECK-FISL-NEXT:    blr
371;
372; CHECK-LE-LABEL: test13:
373; CHECK-LE:       # %bb.0: # %entry
374; CHECK-LE-NEXT:    xxland v2, v2, v3
375; CHECK-LE-NEXT:    blr
376entry:
377  %v = and <16 x i8> %a, %b
378  ret <16 x i8> %v
379
380
381
382}
383
384define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
385; CHECK-LABEL: test14:
386; CHECK:       # %bb.0: # %entry
387; CHECK-NEXT:    xxlnor v2, v2, v3
388; CHECK-NEXT:    blr
389;
390; CHECK-REG-LABEL: test14:
391; CHECK-REG:       # %bb.0: # %entry
392; CHECK-REG-NEXT:    xxlnor v2, v2, v3
393; CHECK-REG-NEXT:    blr
394;
395; CHECK-FISL-LABEL: test14:
396; CHECK-FISL:       # %bb.0: # %entry
397; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
398; CHECK-FISL-NEXT:    xxlnor v2, v2, v3
399; CHECK-FISL-NEXT:    blr
400;
401; CHECK-LE-LABEL: test14:
402; CHECK-LE:       # %bb.0: # %entry
403; CHECK-LE-NEXT:    xxlnor v2, v2, v3
404; CHECK-LE-NEXT:    blr
405entry:
406  %v = or <4 x i32> %a, %b
407  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
408  ret <4 x i32> %w
409
410
411
412}
413
414define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
415; CHECK-LABEL: test15:
416; CHECK:       # %bb.0: # %entry
417; CHECK-NEXT:    xxlnor v2, v2, v3
418; CHECK-NEXT:    blr
419;
420; CHECK-REG-LABEL: test15:
421; CHECK-REG:       # %bb.0: # %entry
422; CHECK-REG-NEXT:    xxlnor v2, v2, v3
423; CHECK-REG-NEXT:    blr
424;
425; CHECK-FISL-LABEL: test15:
426; CHECK-FISL:       # %bb.0: # %entry
427; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
428; CHECK-FISL-NEXT:    xxlor v4, vs0, vs0
429; CHECK-FISL-NEXT:    xxlnor vs0, v2, v3
430; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
431; CHECK-FISL-NEXT:    blr
432;
433; CHECK-LE-LABEL: test15:
434; CHECK-LE:       # %bb.0: # %entry
435; CHECK-LE-NEXT:    xxlnor v2, v2, v3
436; CHECK-LE-NEXT:    blr
437entry:
438  %v = or <8 x i16> %a, %b
439  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
440  ret <8 x i16> %w
441
442
443
444}
445
446define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
447; CHECK-LABEL: test16:
448; CHECK:       # %bb.0: # %entry
449; CHECK-NEXT:    xxlnor v2, v2, v3
450; CHECK-NEXT:    blr
451;
452; CHECK-REG-LABEL: test16:
453; CHECK-REG:       # %bb.0: # %entry
454; CHECK-REG-NEXT:    xxlnor v2, v2, v3
455; CHECK-REG-NEXT:    blr
456;
457; CHECK-FISL-LABEL: test16:
458; CHECK-FISL:       # %bb.0: # %entry
459; CHECK-FISL-NEXT:    xxlor vs0, v2, v3
460; CHECK-FISL-NEXT:    xxlor v4, vs0, vs0
461; CHECK-FISL-NEXT:    xxlnor vs0, v2, v3
462; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
463; CHECK-FISL-NEXT:    blr
464;
465; CHECK-LE-LABEL: test16:
466; CHECK-LE:       # %bb.0: # %entry
467; CHECK-LE-NEXT:    xxlnor v2, v2, v3
468; CHECK-LE-NEXT:    blr
469entry:
470  %v = or <16 x i8> %a, %b
471  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
472  ret <16 x i8> %w
473
474
475
476}
477
478define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
479; CHECK-LABEL: test17:
480; CHECK:       # %bb.0: # %entry
481; CHECK-NEXT:    xxlandc v2, v2, v3
482; CHECK-NEXT:    blr
483;
484; CHECK-REG-LABEL: test17:
485; CHECK-REG:       # %bb.0: # %entry
486; CHECK-REG-NEXT:    xxlandc v2, v2, v3
487; CHECK-REG-NEXT:    blr
488;
489; CHECK-FISL-LABEL: test17:
490; CHECK-FISL:       # %bb.0: # %entry
491; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3
492; CHECK-FISL-NEXT:    xxland v2, v2, vs0
493; CHECK-FISL-NEXT:    blr
494;
495; CHECK-LE-LABEL: test17:
496; CHECK-LE:       # %bb.0: # %entry
497; CHECK-LE-NEXT:    xxlandc v2, v2, v3
498; CHECK-LE-NEXT:    blr
499entry:
500  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
501  %v = and <4 x i32> %a, %w
502  ret <4 x i32> %v
503
504
505
506}
507
508define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
509; CHECK-LABEL: test18:
510; CHECK:       # %bb.0: # %entry
511; CHECK-NEXT:    xxlandc v2, v2, v3
512; CHECK-NEXT:    blr
513;
514; CHECK-REG-LABEL: test18:
515; CHECK-REG:       # %bb.0: # %entry
516; CHECK-REG-NEXT:    xxlandc v2, v2, v3
517; CHECK-REG-NEXT:    blr
518;
519; CHECK-FISL-LABEL: test18:
520; CHECK-FISL:       # %bb.0: # %entry
521; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3
522; CHECK-FISL-NEXT:    xxlor v4, vs0, vs0
523; CHECK-FISL-NEXT:    xxlandc vs0, v2, v3
524; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
525; CHECK-FISL-NEXT:    blr
526;
527; CHECK-LE-LABEL: test18:
528; CHECK-LE:       # %bb.0: # %entry
529; CHECK-LE-NEXT:    xxlandc v2, v2, v3
530; CHECK-LE-NEXT:    blr
531entry:
532  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
533  %v = and <8 x i16> %a, %w
534  ret <8 x i16> %v
535
536
537
538}
539
540define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
541; CHECK-LABEL: test19:
542; CHECK:       # %bb.0: # %entry
543; CHECK-NEXT:    xxlandc v2, v2, v3
544; CHECK-NEXT:    blr
545;
546; CHECK-REG-LABEL: test19:
547; CHECK-REG:       # %bb.0: # %entry
548; CHECK-REG-NEXT:    xxlandc v2, v2, v3
549; CHECK-REG-NEXT:    blr
550;
551; CHECK-FISL-LABEL: test19:
552; CHECK-FISL:       # %bb.0: # %entry
553; CHECK-FISL-NEXT:    xxlnor vs0, v3, v3
554; CHECK-FISL-NEXT:    xxlor v4, vs0, vs0
555; CHECK-FISL-NEXT:    xxlandc vs0, v2, v3
556; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
557; CHECK-FISL-NEXT:    blr
558;
559; CHECK-LE-LABEL: test19:
560; CHECK-LE:       # %bb.0: # %entry
561; CHECK-LE-NEXT:    xxlandc v2, v2, v3
562; CHECK-LE-NEXT:    blr
563entry:
564  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
565  %v = and <16 x i8> %a, %w
566  ret <16 x i8> %v
567
568
569
570}
571
572define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
573; CHECK-LABEL: test20:
574; CHECK:       # %bb.0: # %entry
575; CHECK-NEXT:    vcmpequw v4, v4, v5
576; CHECK-NEXT:    xxsel v2, v3, v2, v4
577; CHECK-NEXT:    blr
578;
579; CHECK-REG-LABEL: test20:
580; CHECK-REG:       # %bb.0: # %entry
581; CHECK-REG-NEXT:    vcmpequw v4, v4, v5
582; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
583; CHECK-REG-NEXT:    blr
584;
585; CHECK-FISL-LABEL: test20:
586; CHECK-FISL:       # %bb.0: # %entry
587; CHECK-FISL-NEXT:    vcmpequw v4, v4, v5
588; CHECK-FISL-NEXT:    xxsel v2, v3, v2, v4
589; CHECK-FISL-NEXT:    blr
590;
591; CHECK-LE-LABEL: test20:
592; CHECK-LE:       # %bb.0: # %entry
593; CHECK-LE-NEXT:    vcmpequw v4, v4, v5
594; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
595; CHECK-LE-NEXT:    blr
596entry:
597  %m = icmp eq <4 x i32> %c, %d
598  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
599  ret <4 x i32> %v
600
601
602
603}
604
605define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
606; CHECK-LABEL: test21:
607; CHECK:       # %bb.0: # %entry
608; CHECK-NEXT:    xvcmpeqsp vs0, v4, v5
609; CHECK-NEXT:    xxsel v2, v3, v2, vs0
610; CHECK-NEXT:    blr
611;
612; CHECK-REG-LABEL: test21:
613; CHECK-REG:       # %bb.0: # %entry
614; CHECK-REG-NEXT:    xvcmpeqsp vs0, v4, v5
615; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
616; CHECK-REG-NEXT:    blr
617;
618; CHECK-FISL-LABEL: test21:
619; CHECK-FISL:       # %bb.0: # %entry
620; CHECK-FISL-NEXT:    xvcmpeqsp vs0, v4, v5
621; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
622; CHECK-FISL-NEXT:    blr
623;
624; CHECK-LE-LABEL: test21:
625; CHECK-LE:       # %bb.0: # %entry
626; CHECK-LE-NEXT:    xvcmpeqsp vs0, v4, v5
627; CHECK-LE-NEXT:    xxsel v2, v3, v2, vs0
628; CHECK-LE-NEXT:    blr
629entry:
630  %m = fcmp oeq <4 x float> %c, %d
631  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
632  ret <4 x float> %v
633
634
635
636}
637
638define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
639; CHECK-LABEL: test22:
640; CHECK:       # %bb.0: # %entry
641; CHECK-NEXT:    xvcmpeqsp vs0, v5, v5
642; CHECK-NEXT:    xvcmpeqsp vs1, v4, v4
643; CHECK-NEXT:    xvcmpeqsp vs2, v4, v5
644; CHECK-NEXT:    xxlnor vs0, vs0, vs0
645; CHECK-NEXT:    xxlnor vs1, vs1, vs1
646; CHECK-NEXT:    xxlor vs0, vs1, vs0
647; CHECK-NEXT:    xxlor vs0, vs2, vs0
648; CHECK-NEXT:    xxsel v2, v3, v2, vs0
649; CHECK-NEXT:    blr
650;
651; CHECK-REG-LABEL: test22:
652; CHECK-REG:       # %bb.0: # %entry
653; CHECK-REG-NEXT:    xvcmpeqsp vs0, v5, v5
654; CHECK-REG-NEXT:    xvcmpeqsp vs1, v4, v4
655; CHECK-REG-NEXT:    xvcmpeqsp vs2, v4, v5
656; CHECK-REG-NEXT:    xxlnor vs0, vs0, vs0
657; CHECK-REG-NEXT:    xxlnor vs1, vs1, vs1
658; CHECK-REG-NEXT:    xxlor vs0, vs1, vs0
659; CHECK-REG-NEXT:    xxlor vs0, vs2, vs0
660; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
661; CHECK-REG-NEXT:    blr
662;
663; CHECK-FISL-LABEL: test22:
664; CHECK-FISL:       # %bb.0: # %entry
665; CHECK-FISL-NEXT:    xvcmpeqsp vs0, v4, v5
666; CHECK-FISL-NEXT:    xvcmpeqsp vs1, v5, v5
667; CHECK-FISL-NEXT:    xxlnor vs1, vs1, vs1
668; CHECK-FISL-NEXT:    xvcmpeqsp vs2, v4, v4
669; CHECK-FISL-NEXT:    xxlnor vs2, vs2, vs2
670; CHECK-FISL-NEXT:    xxlor vs1, vs2, vs1
671; CHECK-FISL-NEXT:    xxlor vs0, vs0, vs1
672; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
673; CHECK-FISL-NEXT:    blr
674;
675; CHECK-LE-LABEL: test22:
676; CHECK-LE:       # %bb.0: # %entry
677; CHECK-LE-NEXT:    xvcmpeqsp vs0, v5, v5
678; CHECK-LE-NEXT:    xvcmpeqsp vs1, v4, v4
679; CHECK-LE-NEXT:    xvcmpeqsp vs2, v4, v5
680; CHECK-LE-NEXT:    xxlnor vs0, vs0, vs0
681; CHECK-LE-NEXT:    xxlnor vs1, vs1, vs1
682; CHECK-LE-NEXT:    xxlor vs0, vs1, vs0
683; CHECK-LE-NEXT:    xxlor vs0, vs2, vs0
684; CHECK-LE-NEXT:    xxsel v2, v3, v2, vs0
685; CHECK-LE-NEXT:    blr
686entry:
687  %m = fcmp ueq <4 x float> %c, %d
688  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
689  ret <4 x float> %v
690
691
692
693}
694
695define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
696; CHECK-LABEL: test23:
697; CHECK:       # %bb.0: # %entry
698; CHECK-NEXT:    vcmpequh v4, v4, v5
699; CHECK-NEXT:    xxsel v2, v3, v2, v4
700; CHECK-NEXT:    blr
701;
702; CHECK-REG-LABEL: test23:
703; CHECK-REG:       # %bb.0: # %entry
704; CHECK-REG-NEXT:    vcmpequh v4, v4, v5
705; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
706; CHECK-REG-NEXT:    blr
707;
708; CHECK-FISL-LABEL: test23:
709; CHECK-FISL:       # %bb.0: # %entry
710; CHECK-FISL-NEXT:    vcmpequh v4, v4, v5
711; CHECK-FISL-NEXT:    xxsel vs0, v3, v2, v4
712; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
713; CHECK-FISL-NEXT:    blr
714;
715; CHECK-LE-LABEL: test23:
716; CHECK-LE:       # %bb.0: # %entry
717; CHECK-LE-NEXT:    vcmpequh v4, v4, v5
718; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
719; CHECK-LE-NEXT:    blr
720entry:
721  %m = icmp eq <8 x i16> %c, %d
722  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
723  ret <8 x i16> %v
724
725
726
727}
728
729define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
730; CHECK-LABEL: test24:
731; CHECK:       # %bb.0: # %entry
732; CHECK-NEXT:    vcmpequb v4, v4, v5
733; CHECK-NEXT:    xxsel v2, v3, v2, v4
734; CHECK-NEXT:    blr
735;
736; CHECK-REG-LABEL: test24:
737; CHECK-REG:       # %bb.0: # %entry
738; CHECK-REG-NEXT:    vcmpequb v4, v4, v5
739; CHECK-REG-NEXT:    xxsel v2, v3, v2, v4
740; CHECK-REG-NEXT:    blr
741;
742; CHECK-FISL-LABEL: test24:
743; CHECK-FISL:       # %bb.0: # %entry
744; CHECK-FISL-NEXT:    vcmpequb v4, v4, v5
745; CHECK-FISL-NEXT:    xxsel vs0, v3, v2, v4
746; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
747; CHECK-FISL-NEXT:    blr
748;
749; CHECK-LE-LABEL: test24:
750; CHECK-LE:       # %bb.0: # %entry
751; CHECK-LE-NEXT:    vcmpequb v4, v4, v5
752; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
753; CHECK-LE-NEXT:    blr
754entry:
755  %m = icmp eq <16 x i8> %c, %d
756  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
757  ret <16 x i8> %v
758
759
760
761}
762
763define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
764; CHECK-LABEL: test25:
765; CHECK:       # %bb.0: # %entry
766; CHECK-NEXT:    xvcmpeqdp vs0, v4, v5
767; CHECK-NEXT:    xxsel v2, v3, v2, vs0
768; CHECK-NEXT:    blr
769;
770; CHECK-REG-LABEL: test25:
771; CHECK-REG:       # %bb.0: # %entry
772; CHECK-REG-NEXT:    xvcmpeqdp vs0, v4, v5
773; CHECK-REG-NEXT:    xxsel v2, v3, v2, vs0
774; CHECK-REG-NEXT:    blr
775;
776; CHECK-FISL-LABEL: test25:
777; CHECK-FISL:       # %bb.0: # %entry
778; CHECK-FISL-NEXT:    xvcmpeqdp vs0, v4, v5
779; CHECK-FISL-NEXT:    xxsel v2, v3, v2, vs0
780; CHECK-FISL-NEXT:    blr
781;
782; CHECK-LE-LABEL: test25:
783; CHECK-LE:       # %bb.0: # %entry
784; CHECK-LE-NEXT:    xvcmpeqdp v4, v4, v5
785; CHECK-LE-NEXT:    xxsel v2, v3, v2, v4
786; CHECK-LE-NEXT:    blr
787entry:
788  %m = fcmp oeq <2 x double> %c, %d
789  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
790  ret <2 x double> %v
791
792
793}
794
795define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
796; CHECK-LABEL: test26:
797; CHECK:       # %bb.0:
798; CHECK-NEXT:    addi r3, r1, -32
799; CHECK-NEXT:    addi r4, r1, -48
800; CHECK-NEXT:    stxvd2x v3, 0, r3
801; CHECK-NEXT:    stxvd2x v2, 0, r4
802; CHECK-NEXT:    ld r3, -24(r1)
803; CHECK-NEXT:    ld r4, -40(r1)
804; CHECK-NEXT:    add r3, r4, r3
805; CHECK-NEXT:    ld r4, -48(r1)
806; CHECK-NEXT:    std r3, -8(r1)
807; CHECK-NEXT:    ld r3, -32(r1)
808; CHECK-NEXT:    add r3, r4, r3
809; CHECK-NEXT:    std r3, -16(r1)
810; CHECK-NEXT:    addi r3, r1, -16
811; CHECK-NEXT:    lxvd2x v2, 0, r3
812; CHECK-NEXT:    blr
813;
814; CHECK-REG-LABEL: test26:
815; CHECK-REG:       # %bb.0:
816; CHECK-REG-NEXT:    addi r3, r1, -32
817; CHECK-REG-NEXT:    addi r4, r1, -48
818; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
819; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
820; CHECK-REG-NEXT:    ld r3, -24(r1)
821; CHECK-REG-NEXT:    ld r4, -40(r1)
822; CHECK-REG-NEXT:    add r3, r4, r3
823; CHECK-REG-NEXT:    ld r4, -48(r1)
824; CHECK-REG-NEXT:    std r3, -8(r1)
825; CHECK-REG-NEXT:    ld r3, -32(r1)
826; CHECK-REG-NEXT:    add r3, r4, r3
827; CHECK-REG-NEXT:    std r3, -16(r1)
828; CHECK-REG-NEXT:    addi r3, r1, -16
829; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
830; CHECK-REG-NEXT:    blr
831;
832; CHECK-FISL-LABEL: test26:
833; CHECK-FISL:       # %bb.0:
834; CHECK-FISL-NEXT:    addi r3, r1, -32
835; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
836; CHECK-FISL-NEXT:    addi r3, r1, -48
837; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
838; CHECK-FISL-NEXT:    ld r3, -24(r1)
839; CHECK-FISL-NEXT:    ld r4, -40(r1)
840; CHECK-FISL-NEXT:    add r3, r4, r3
841; CHECK-FISL-NEXT:    std r3, -8(r1)
842; CHECK-FISL-NEXT:    ld r3, -32(r1)
843; CHECK-FISL-NEXT:    ld r4, -48(r1)
844; CHECK-FISL-NEXT:    add r3, r4, r3
845; CHECK-FISL-NEXT:    std r3, -16(r1)
846; CHECK-FISL-NEXT:    addi r3, r1, -16
847; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
848; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
849; CHECK-FISL-NEXT:    blr
850;
851; CHECK-LE-LABEL: test26:
852; CHECK-LE:       # %bb.0:
853; CHECK-LE-NEXT:    vaddudm v2, v2, v3
854; CHECK-LE-NEXT:    blr
855  %v = add <2 x i64> %a, %b
856  ret <2 x i64> %v
857
858
859; Make sure we use only two stores (one for each operand).
860
861; FIXME: The code quality here is not good; just make sure we do something for now.
862
863}
864
865define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
866; CHECK-LABEL: test27:
867; CHECK:       # %bb.0:
868; CHECK-NEXT:    xxland v2, v2, v3
869; CHECK-NEXT:    blr
870;
871; CHECK-REG-LABEL: test27:
872; CHECK-REG:       # %bb.0:
873; CHECK-REG-NEXT:    xxland v2, v2, v3
874; CHECK-REG-NEXT:    blr
875;
876; CHECK-FISL-LABEL: test27:
877; CHECK-FISL:       # %bb.0:
878; CHECK-FISL-NEXT:    xxland vs0, v2, v3
879; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
880; CHECK-FISL-NEXT:    blr
881;
882; CHECK-LE-LABEL: test27:
883; CHECK-LE:       # %bb.0:
884; CHECK-LE-NEXT:    xxland v2, v2, v3
885; CHECK-LE-NEXT:    blr
886  %v = and <2 x i64> %a, %b
887  ret <2 x i64> %v
888
889
890}
891
892define <2 x double> @test28(<2 x double>* %a) {
893; CHECK-LABEL: test28:
894; CHECK:       # %bb.0:
895; CHECK-NEXT:    lxvd2x v2, 0, r3
896; CHECK-NEXT:    blr
897;
898; CHECK-REG-LABEL: test28:
899; CHECK-REG:       # %bb.0:
900; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
901; CHECK-REG-NEXT:    blr
902;
903; CHECK-FISL-LABEL: test28:
904; CHECK-FISL:       # %bb.0:
905; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
906; CHECK-FISL-NEXT:    blr
907;
908; CHECK-LE-LABEL: test28:
909; CHECK-LE:       # %bb.0:
910; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
911; CHECK-LE-NEXT:    xxswapd v2, vs0
912; CHECK-LE-NEXT:    blr
913  %v = load <2 x double>, <2 x double>* %a, align 16
914  ret <2 x double> %v
915
916
917}
918
919define void @test29(<2 x double>* %a, <2 x double> %b) {
920; CHECK-LABEL: test29:
921; CHECK:       # %bb.0:
922; CHECK-NEXT:    stxvd2x v2, 0, r3
923; CHECK-NEXT:    blr
924;
925; CHECK-REG-LABEL: test29:
926; CHECK-REG:       # %bb.0:
927; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
928; CHECK-REG-NEXT:    blr
929;
930; CHECK-FISL-LABEL: test29:
931; CHECK-FISL:       # %bb.0:
932; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
933; CHECK-FISL-NEXT:    blr
934;
935; CHECK-LE-LABEL: test29:
936; CHECK-LE:       # %bb.0:
937; CHECK-LE-NEXT:    xxswapd vs0, v2
938; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
939; CHECK-LE-NEXT:    blr
940  store <2 x double> %b, <2 x double>* %a, align 16
941  ret void
942
943
944}
945
946define <2 x double> @test28u(<2 x double>* %a) {
947; CHECK-LABEL: test28u:
948; CHECK:       # %bb.0:
949; CHECK-NEXT:    lxvd2x v2, 0, r3
950; CHECK-NEXT:    blr
951;
952; CHECK-REG-LABEL: test28u:
953; CHECK-REG:       # %bb.0:
954; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
955; CHECK-REG-NEXT:    blr
956;
957; CHECK-FISL-LABEL: test28u:
958; CHECK-FISL:       # %bb.0:
959; CHECK-FISL-NEXT:    lxvd2x v2, 0, r3
960; CHECK-FISL-NEXT:    blr
961;
962; CHECK-LE-LABEL: test28u:
963; CHECK-LE:       # %bb.0:
964; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
965; CHECK-LE-NEXT:    xxswapd v2, vs0
966; CHECK-LE-NEXT:    blr
967  %v = load <2 x double>, <2 x double>* %a, align 8
968  ret <2 x double> %v
969
970
971}
972
973define void @test29u(<2 x double>* %a, <2 x double> %b) {
974; CHECK-LABEL: test29u:
975; CHECK:       # %bb.0:
976; CHECK-NEXT:    stxvd2x v2, 0, r3
977; CHECK-NEXT:    blr
978;
979; CHECK-REG-LABEL: test29u:
980; CHECK-REG:       # %bb.0:
981; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
982; CHECK-REG-NEXT:    blr
983;
984; CHECK-FISL-LABEL: test29u:
985; CHECK-FISL:       # %bb.0:
986; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
987; CHECK-FISL-NEXT:    blr
988;
989; CHECK-LE-LABEL: test29u:
990; CHECK-LE:       # %bb.0:
991; CHECK-LE-NEXT:    xxswapd vs0, v2
992; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
993; CHECK-LE-NEXT:    blr
994  store <2 x double> %b, <2 x double>* %a, align 8
995  ret void
996
997
998}
999
1000define <2 x i64> @test30(<2 x i64>* %a) {
1001; CHECK-LABEL: test30:
1002; CHECK:       # %bb.0:
1003; CHECK-NEXT:    lxvd2x v2, 0, r3
1004; CHECK-NEXT:    blr
1005;
1006; CHECK-REG-LABEL: test30:
1007; CHECK-REG:       # %bb.0:
1008; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1009; CHECK-REG-NEXT:    blr
1010;
1011; CHECK-FISL-LABEL: test30:
1012; CHECK-FISL:       # %bb.0:
1013; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
1014; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
1015; CHECK-FISL-NEXT:    blr
1016;
1017; CHECK-LE-LABEL: test30:
1018; CHECK-LE:       # %bb.0:
1019; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
1020; CHECK-LE-NEXT:    xxswapd v2, vs0
1021; CHECK-LE-NEXT:    blr
1022  %v = load <2 x i64>, <2 x i64>* %a, align 16
1023  ret <2 x i64> %v
1024
1025
1026
1027}
1028
1029define void @test31(<2 x i64>* %a, <2 x i64> %b) {
1030; CHECK-LABEL: test31:
1031; CHECK:       # %bb.0:
1032; CHECK-NEXT:    stxvd2x v2, 0, r3
1033; CHECK-NEXT:    blr
1034;
1035; CHECK-REG-LABEL: test31:
1036; CHECK-REG:       # %bb.0:
1037; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1038; CHECK-REG-NEXT:    blr
1039;
1040; CHECK-FISL-LABEL: test31:
1041; CHECK-FISL:       # %bb.0:
1042; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1043; CHECK-FISL-NEXT:    blr
1044;
1045; CHECK-LE-LABEL: test31:
1046; CHECK-LE:       # %bb.0:
1047; CHECK-LE-NEXT:    xxswapd vs0, v2
1048; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1049; CHECK-LE-NEXT:    blr
1050  store <2 x i64> %b, <2 x i64>* %a, align 16
1051  ret void
1052
1053
1054}
1055
1056define <4 x float> @test32(<4 x float>* %a) {
1057; CHECK-LABEL: test32:
1058; CHECK:       # %bb.0:
1059; CHECK-NEXT:    lxvw4x v2, 0, r3
1060; CHECK-NEXT:    blr
1061;
1062; CHECK-REG-LABEL: test32:
1063; CHECK-REG:       # %bb.0:
1064; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1065; CHECK-REG-NEXT:    blr
1066;
1067; CHECK-FISL-LABEL: test32:
1068; CHECK-FISL:       # %bb.0:
1069; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1070; CHECK-FISL-NEXT:    blr
1071;
1072; CHECK-LE-LABEL: test32:
1073; CHECK-LE:       # %bb.0:
1074; CHECK-LE-NEXT:    lvx v2, 0, r3
1075; CHECK-LE-NEXT:    blr
1076  %v = load <4 x float>, <4 x float>* %a, align 16
1077  ret <4 x float> %v
1078
1079
1080
1081}
1082
1083define void @test33(<4 x float>* %a, <4 x float> %b) {
1084; CHECK-LABEL: test33:
1085; CHECK:       # %bb.0:
1086; CHECK-NEXT:    stxvw4x v2, 0, r3
1087; CHECK-NEXT:    blr
1088;
1089; CHECK-REG-LABEL: test33:
1090; CHECK-REG:       # %bb.0:
1091; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1092; CHECK-REG-NEXT:    blr
1093;
1094; CHECK-FISL-LABEL: test33:
1095; CHECK-FISL:       # %bb.0:
1096; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1097; CHECK-FISL-NEXT:    blr
1098;
1099; CHECK-LE-LABEL: test33:
1100; CHECK-LE:       # %bb.0:
1101; CHECK-LE-NEXT:    stvx v2, 0, r3
1102; CHECK-LE-NEXT:    blr
1103  store <4 x float> %b, <4 x float>* %a, align 16
1104  ret void
1105
1106
1107
1108}
1109
1110define <4 x float> @test32u(<4 x float>* %a) {
1111; CHECK-LABEL: test32u:
1112; CHECK:       # %bb.0:
1113; CHECK-NEXT:    li r4, 15
1114; CHECK-NEXT:    lvsl v3, 0, r3
1115; CHECK-NEXT:    lvx v2, r3, r4
1116; CHECK-NEXT:    lvx v4, 0, r3
1117; CHECK-NEXT:    vperm v2, v4, v2, v3
1118; CHECK-NEXT:    blr
1119;
1120; CHECK-REG-LABEL: test32u:
1121; CHECK-REG:       # %bb.0:
1122; CHECK-REG-NEXT:    li r4, 15
1123; CHECK-REG-NEXT:    lvsl v3, 0, r3
1124; CHECK-REG-NEXT:    lvx v2, r3, r4
1125; CHECK-REG-NEXT:    lvx v4, 0, r3
1126; CHECK-REG-NEXT:    vperm v2, v4, v2, v3
1127; CHECK-REG-NEXT:    blr
1128;
1129; CHECK-FISL-LABEL: test32u:
1130; CHECK-FISL:       # %bb.0:
1131; CHECK-FISL-NEXT:    li r4, 15
1132; CHECK-FISL-NEXT:    lvx v2, r3, r4
1133; CHECK-FISL-NEXT:    lvsl v3, 0, r3
1134; CHECK-FISL-NEXT:    lvx v4, 0, r3
1135; CHECK-FISL-NEXT:    vperm v2, v4, v2, v3
1136; CHECK-FISL-NEXT:    blr
1137;
1138; CHECK-LE-LABEL: test32u:
1139; CHECK-LE:       # %bb.0:
1140; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
1141; CHECK-LE-NEXT:    xxswapd v2, vs0
1142; CHECK-LE-NEXT:    blr
1143  %v = load <4 x float>, <4 x float>* %a, align 8
1144  ret <4 x float> %v
1145
1146
1147}
1148
1149define void @test33u(<4 x float>* %a, <4 x float> %b) {
1150; CHECK-LABEL: test33u:
1151; CHECK:       # %bb.0:
1152; CHECK-NEXT:    stxvw4x v2, 0, r3
1153; CHECK-NEXT:    blr
1154;
1155; CHECK-REG-LABEL: test33u:
1156; CHECK-REG:       # %bb.0:
1157; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1158; CHECK-REG-NEXT:    blr
1159;
1160; CHECK-FISL-LABEL: test33u:
1161; CHECK-FISL:       # %bb.0:
1162; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1163; CHECK-FISL-NEXT:    blr
1164;
1165; CHECK-LE-LABEL: test33u:
1166; CHECK-LE:       # %bb.0:
1167; CHECK-LE-NEXT:    xxswapd vs0, v2
1168; CHECK-LE-NEXT:    stxvd2x vs0, 0, r3
1169; CHECK-LE-NEXT:    blr
1170  store <4 x float> %b, <4 x float>* %a, align 8
1171  ret void
1172
1173
1174
1175}
1176
1177define <4 x i32> @test34(<4 x i32>* %a) {
1178; CHECK-LABEL: test34:
1179; CHECK:       # %bb.0:
1180; CHECK-NEXT:    lxvw4x v2, 0, r3
1181; CHECK-NEXT:    blr
1182;
1183; CHECK-REG-LABEL: test34:
1184; CHECK-REG:       # %bb.0:
1185; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1186; CHECK-REG-NEXT:    blr
1187;
1188; CHECK-FISL-LABEL: test34:
1189; CHECK-FISL:       # %bb.0:
1190; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1191; CHECK-FISL-NEXT:    blr
1192;
1193; CHECK-LE-LABEL: test34:
1194; CHECK-LE:       # %bb.0:
1195; CHECK-LE-NEXT:    lvx v2, 0, r3
1196; CHECK-LE-NEXT:    blr
1197  %v = load <4 x i32>, <4 x i32>* %a, align 16
1198  ret <4 x i32> %v
1199
1200
1201
1202}
1203
1204define void @test35(<4 x i32>* %a, <4 x i32> %b) {
1205; CHECK-LABEL: test35:
1206; CHECK:       # %bb.0:
1207; CHECK-NEXT:    stxvw4x v2, 0, r3
1208; CHECK-NEXT:    blr
1209;
1210; CHECK-REG-LABEL: test35:
1211; CHECK-REG:       # %bb.0:
1212; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1213; CHECK-REG-NEXT:    blr
1214;
1215; CHECK-FISL-LABEL: test35:
1216; CHECK-FISL:       # %bb.0:
1217; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1218; CHECK-FISL-NEXT:    blr
1219;
1220; CHECK-LE-LABEL: test35:
1221; CHECK-LE:       # %bb.0:
1222; CHECK-LE-NEXT:    stvx v2, 0, r3
1223; CHECK-LE-NEXT:    blr
1224  store <4 x i32> %b, <4 x i32>* %a, align 16
1225  ret void
1226
1227
1228
1229}
1230
1231define <2 x double> @test40(<2 x i64> %a) {
1232; CHECK-LABEL: test40:
1233; CHECK:       # %bb.0:
1234; CHECK-NEXT:    xvcvuxddp v2, v2
1235; CHECK-NEXT:    blr
1236;
1237; CHECK-REG-LABEL: test40:
1238; CHECK-REG:       # %bb.0:
1239; CHECK-REG-NEXT:    xvcvuxddp v2, v2
1240; CHECK-REG-NEXT:    blr
1241;
1242; CHECK-FISL-LABEL: test40:
1243; CHECK-FISL:       # %bb.0:
1244; CHECK-FISL-NEXT:    xvcvuxddp v2, v2
1245; CHECK-FISL-NEXT:    blr
1246;
1247; CHECK-LE-LABEL: test40:
1248; CHECK-LE:       # %bb.0:
1249; CHECK-LE-NEXT:    xvcvuxddp v2, v2
1250; CHECK-LE-NEXT:    blr
1251  %v = uitofp <2 x i64> %a to <2 x double>
1252  ret <2 x double> %v
1253
1254
1255}
1256
1257define <2 x double> @test41(<2 x i64> %a) {
1258; CHECK-LABEL: test41:
1259; CHECK:       # %bb.0:
1260; CHECK-NEXT:    xvcvsxddp v2, v2
1261; CHECK-NEXT:    blr
1262;
1263; CHECK-REG-LABEL: test41:
1264; CHECK-REG:       # %bb.0:
1265; CHECK-REG-NEXT:    xvcvsxddp v2, v2
1266; CHECK-REG-NEXT:    blr
1267;
1268; CHECK-FISL-LABEL: test41:
1269; CHECK-FISL:       # %bb.0:
1270; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
1271; CHECK-FISL-NEXT:    blr
1272;
1273; CHECK-LE-LABEL: test41:
1274; CHECK-LE:       # %bb.0:
1275; CHECK-LE-NEXT:    xvcvsxddp v2, v2
1276; CHECK-LE-NEXT:    blr
1277  %v = sitofp <2 x i64> %a to <2 x double>
1278  ret <2 x double> %v
1279
1280
1281}
1282
1283define <2 x i64> @test42(<2 x double> %a) {
1284; CHECK-LABEL: test42:
1285; CHECK:       # %bb.0:
1286; CHECK-NEXT:    xvcvdpuxds v2, v2
1287; CHECK-NEXT:    blr
1288;
1289; CHECK-REG-LABEL: test42:
1290; CHECK-REG:       # %bb.0:
1291; CHECK-REG-NEXT:    xvcvdpuxds v2, v2
1292; CHECK-REG-NEXT:    blr
1293;
1294; CHECK-FISL-LABEL: test42:
1295; CHECK-FISL:       # %bb.0:
1296; CHECK-FISL-NEXT:    xvcvdpuxds v2, v2
1297; CHECK-FISL-NEXT:    blr
1298;
1299; CHECK-LE-LABEL: test42:
1300; CHECK-LE:       # %bb.0:
1301; CHECK-LE-NEXT:    xvcvdpuxds v2, v2
1302; CHECK-LE-NEXT:    blr
1303  %v = fptoui <2 x double> %a to <2 x i64>
1304  ret <2 x i64> %v
1305
1306
1307}
1308
1309define <2 x i64> @test43(<2 x double> %a) {
1310; CHECK-LABEL: test43:
1311; CHECK:       # %bb.0:
1312; CHECK-NEXT:    xvcvdpsxds v2, v2
1313; CHECK-NEXT:    blr
1314;
1315; CHECK-REG-LABEL: test43:
1316; CHECK-REG:       # %bb.0:
1317; CHECK-REG-NEXT:    xvcvdpsxds v2, v2
1318; CHECK-REG-NEXT:    blr
1319;
1320; CHECK-FISL-LABEL: test43:
1321; CHECK-FISL:       # %bb.0:
1322; CHECK-FISL-NEXT:    xvcvdpsxds v2, v2
1323; CHECK-FISL-NEXT:    blr
1324;
1325; CHECK-LE-LABEL: test43:
1326; CHECK-LE:       # %bb.0:
1327; CHECK-LE-NEXT:    xvcvdpsxds v2, v2
1328; CHECK-LE-NEXT:    blr
1329  %v = fptosi <2 x double> %a to <2 x i64>
1330  ret <2 x i64> %v
1331
1332
1333}
1334
1335define <2 x float> @test44(<2 x i64> %a) {
1336; CHECK-LABEL: test44:
1337; CHECK:       # %bb.0:
1338; CHECK-NEXT:    addi r3, r1, -16
1339; CHECK-NEXT:    addi r4, r1, -64
1340; CHECK-NEXT:    stxvd2x v2, 0, r3
1341; CHECK-NEXT:    ld r3, -8(r1)
1342; CHECK-NEXT:    std r3, -24(r1)
1343; CHECK-NEXT:    ld r3, -16(r1)
1344; CHECK-NEXT:    std r3, -32(r1)
1345; CHECK-NEXT:    lfd f0, -24(r1)
1346; CHECK-NEXT:    fcfidus f0, f0
1347; CHECK-NEXT:    stfs f0, -48(r1)
1348; CHECK-NEXT:    lfd f0, -32(r1)
1349; CHECK-NEXT:    addi r3, r1, -48
1350; CHECK-NEXT:    fcfidus f0, f0
1351; CHECK-NEXT:    stfs f0, -64(r1)
1352; CHECK-NEXT:    lxvw4x v2, 0, r3
1353; CHECK-NEXT:    lxvw4x v3, 0, r4
1354; CHECK-NEXT:    vmrghw v2, v3, v2
1355; CHECK-NEXT:    blr
1356;
1357; CHECK-REG-LABEL: test44:
1358; CHECK-REG:       # %bb.0:
1359; CHECK-REG-NEXT:    addi r3, r1, -16
1360; CHECK-REG-NEXT:    addi r4, r1, -64
1361; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1362; CHECK-REG-NEXT:    ld r3, -8(r1)
1363; CHECK-REG-NEXT:    std r3, -24(r1)
1364; CHECK-REG-NEXT:    ld r3, -16(r1)
1365; CHECK-REG-NEXT:    std r3, -32(r1)
1366; CHECK-REG-NEXT:    lfd f0, -24(r1)
1367; CHECK-REG-NEXT:    fcfidus f0, f0
1368; CHECK-REG-NEXT:    stfs f0, -48(r1)
1369; CHECK-REG-NEXT:    lfd f0, -32(r1)
1370; CHECK-REG-NEXT:    addi r3, r1, -48
1371; CHECK-REG-NEXT:    fcfidus f0, f0
1372; CHECK-REG-NEXT:    stfs f0, -64(r1)
1373; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1374; CHECK-REG-NEXT:    lxvw4x v3, 0, r4
1375; CHECK-REG-NEXT:    vmrghw v2, v3, v2
1376; CHECK-REG-NEXT:    blr
1377;
1378; CHECK-FISL-LABEL: test44:
1379; CHECK-FISL:       # %bb.0:
1380; CHECK-FISL-NEXT:    addi r3, r1, -16
1381; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1382; CHECK-FISL-NEXT:    ld r3, -8(r1)
1383; CHECK-FISL-NEXT:    std r3, -24(r1)
1384; CHECK-FISL-NEXT:    ld r3, -16(r1)
1385; CHECK-FISL-NEXT:    std r3, -32(r1)
1386; CHECK-FISL-NEXT:    lfd f0, -24(r1)
1387; CHECK-FISL-NEXT:    fcfidus f0, f0
1388; CHECK-FISL-NEXT:    stfs f0, -48(r1)
1389; CHECK-FISL-NEXT:    lfd f0, -32(r1)
1390; CHECK-FISL-NEXT:    fcfidus f0, f0
1391; CHECK-FISL-NEXT:    stfs f0, -64(r1)
1392; CHECK-FISL-NEXT:    addi r3, r1, -48
1393; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1394; CHECK-FISL-NEXT:    addi r3, r1, -64
1395; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
1396; CHECK-FISL-NEXT:    vmrghw v2, v3, v2
1397; CHECK-FISL-NEXT:    blr
1398;
1399; CHECK-LE-LABEL: test44:
1400; CHECK-LE:       # %bb.0:
1401; CHECK-LE-NEXT:    xxswapd vs0, v2
1402; CHECK-LE-NEXT:    xxlor vs1, v2, v2
1403; CHECK-LE-NEXT:    xscvuxdsp f1, f1
1404; CHECK-LE-NEXT:    xscvuxdsp f0, f0
1405; CHECK-LE-NEXT:    xscvdpspn vs1, f1
1406; CHECK-LE-NEXT:    xscvdpspn vs0, f0
1407; CHECK-LE-NEXT:    xxsldwi v3, vs1, vs1, 3
1408; CHECK-LE-NEXT:    xxsldwi v2, vs0, vs0, 3
1409; CHECK-LE-NEXT:    vmrghw v2, v3, v2
1410; CHECK-LE-NEXT:    blr
1411  %v = uitofp <2 x i64> %a to <2 x float>
1412  ret <2 x float> %v
1413
1414; FIXME: The code quality here looks pretty bad.
1415}
1416
1417define <2 x float> @test45(<2 x i64> %a) {
1418; CHECK-LABEL: test45:
1419; CHECK:       # %bb.0:
1420; CHECK-NEXT:    addi r3, r1, -16
1421; CHECK-NEXT:    addi r4, r1, -64
1422; CHECK-NEXT:    stxvd2x v2, 0, r3
1423; CHECK-NEXT:    ld r3, -8(r1)
1424; CHECK-NEXT:    std r3, -24(r1)
1425; CHECK-NEXT:    ld r3, -16(r1)
1426; CHECK-NEXT:    std r3, -32(r1)
1427; CHECK-NEXT:    lfd f0, -24(r1)
1428; CHECK-NEXT:    fcfids f0, f0
1429; CHECK-NEXT:    stfs f0, -48(r1)
1430; CHECK-NEXT:    lfd f0, -32(r1)
1431; CHECK-NEXT:    addi r3, r1, -48
1432; CHECK-NEXT:    fcfids f0, f0
1433; CHECK-NEXT:    stfs f0, -64(r1)
1434; CHECK-NEXT:    lxvw4x v2, 0, r3
1435; CHECK-NEXT:    lxvw4x v3, 0, r4
1436; CHECK-NEXT:    vmrghw v2, v3, v2
1437; CHECK-NEXT:    blr
1438;
1439; CHECK-REG-LABEL: test45:
1440; CHECK-REG:       # %bb.0:
1441; CHECK-REG-NEXT:    addi r3, r1, -16
1442; CHECK-REG-NEXT:    addi r4, r1, -64
1443; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
1444; CHECK-REG-NEXT:    ld r3, -8(r1)
1445; CHECK-REG-NEXT:    std r3, -24(r1)
1446; CHECK-REG-NEXT:    ld r3, -16(r1)
1447; CHECK-REG-NEXT:    std r3, -32(r1)
1448; CHECK-REG-NEXT:    lfd f0, -24(r1)
1449; CHECK-REG-NEXT:    fcfids f0, f0
1450; CHECK-REG-NEXT:    stfs f0, -48(r1)
1451; CHECK-REG-NEXT:    lfd f0, -32(r1)
1452; CHECK-REG-NEXT:    addi r3, r1, -48
1453; CHECK-REG-NEXT:    fcfids f0, f0
1454; CHECK-REG-NEXT:    stfs f0, -64(r1)
1455; CHECK-REG-NEXT:    lxvw4x v2, 0, r3
1456; CHECK-REG-NEXT:    lxvw4x v3, 0, r4
1457; CHECK-REG-NEXT:    vmrghw v2, v3, v2
1458; CHECK-REG-NEXT:    blr
1459;
1460; CHECK-FISL-LABEL: test45:
1461; CHECK-FISL:       # %bb.0:
1462; CHECK-FISL-NEXT:    addi r3, r1, -16
1463; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1464; CHECK-FISL-NEXT:    ld r3, -8(r1)
1465; CHECK-FISL-NEXT:    std r3, -24(r1)
1466; CHECK-FISL-NEXT:    ld r3, -16(r1)
1467; CHECK-FISL-NEXT:    std r3, -32(r1)
1468; CHECK-FISL-NEXT:    lfd f0, -24(r1)
1469; CHECK-FISL-NEXT:    fcfids f0, f0
1470; CHECK-FISL-NEXT:    stfs f0, -48(r1)
1471; CHECK-FISL-NEXT:    lfd f0, -32(r1)
1472; CHECK-FISL-NEXT:    fcfids f0, f0
1473; CHECK-FISL-NEXT:    stfs f0, -64(r1)
1474; CHECK-FISL-NEXT:    addi r3, r1, -48
1475; CHECK-FISL-NEXT:    lxvw4x v2, 0, r3
1476; CHECK-FISL-NEXT:    addi r3, r1, -64
1477; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
1478; CHECK-FISL-NEXT:    vmrghw v2, v3, v2
1479; CHECK-FISL-NEXT:    blr
1480;
1481; CHECK-LE-LABEL: test45:
1482; CHECK-LE:       # %bb.0:
1483; CHECK-LE-NEXT:    xxswapd vs0, v2
1484; CHECK-LE-NEXT:    xxlor vs1, v2, v2
1485; CHECK-LE-NEXT:    xscvsxdsp f1, f1
1486; CHECK-LE-NEXT:    xscvsxdsp f0, f0
1487; CHECK-LE-NEXT:    xscvdpspn vs1, f1
1488; CHECK-LE-NEXT:    xscvdpspn vs0, f0
1489; CHECK-LE-NEXT:    xxsldwi v3, vs1, vs1, 3
1490; CHECK-LE-NEXT:    xxsldwi v2, vs0, vs0, 3
1491; CHECK-LE-NEXT:    vmrghw v2, v3, v2
1492; CHECK-LE-NEXT:    blr
1493  %v = sitofp <2 x i64> %a to <2 x float>
1494  ret <2 x float> %v
1495
1496; FIXME: The code quality here looks pretty bad.
1497}
1498
1499define <2 x i64> @test46(<2 x float> %a) {
1500; CHECK-LABEL: test46:
1501; CHECK:       # %bb.0:
1502; CHECK-NEXT:    addi r3, r1, -48
1503; CHECK-NEXT:    stxvw4x v2, 0, r3
1504; CHECK-NEXT:    lfs f0, -44(r1)
1505; CHECK-NEXT:    xscvdpuxds f0, f0
1506; CHECK-NEXT:    stfd f0, -32(r1)
1507; CHECK-NEXT:    lfs f0, -48(r1)
1508; CHECK-NEXT:    xscvdpuxds f0, f0
1509; CHECK-NEXT:    stfd f0, -24(r1)
1510; CHECK-NEXT:    ld r3, -32(r1)
1511; CHECK-NEXT:    std r3, -8(r1)
1512; CHECK-NEXT:    ld r3, -24(r1)
1513; CHECK-NEXT:    std r3, -16(r1)
1514; CHECK-NEXT:    addi r3, r1, -16
1515; CHECK-NEXT:    lxvd2x v2, 0, r3
1516; CHECK-NEXT:    blr
1517;
1518; CHECK-REG-LABEL: test46:
1519; CHECK-REG:       # %bb.0:
1520; CHECK-REG-NEXT:    addi r3, r1, -48
1521; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1522; CHECK-REG-NEXT:    lfs f0, -44(r1)
1523; CHECK-REG-NEXT:    xscvdpuxds f0, f0
1524; CHECK-REG-NEXT:    stfd f0, -32(r1)
1525; CHECK-REG-NEXT:    lfs f0, -48(r1)
1526; CHECK-REG-NEXT:    xscvdpuxds f0, f0
1527; CHECK-REG-NEXT:    stfd f0, -24(r1)
1528; CHECK-REG-NEXT:    ld r3, -32(r1)
1529; CHECK-REG-NEXT:    std r3, -8(r1)
1530; CHECK-REG-NEXT:    ld r3, -24(r1)
1531; CHECK-REG-NEXT:    std r3, -16(r1)
1532; CHECK-REG-NEXT:    addi r3, r1, -16
1533; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1534; CHECK-REG-NEXT:    blr
1535;
1536; CHECK-FISL-LABEL: test46:
1537; CHECK-FISL:       # %bb.0:
1538; CHECK-FISL-NEXT:    addi r3, r1, -48
1539; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1540; CHECK-FISL-NEXT:    lfs f0, -44(r1)
1541; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
1542; CHECK-FISL-NEXT:    stfd f0, -32(r1)
1543; CHECK-FISL-NEXT:    lfs f0, -48(r1)
1544; CHECK-FISL-NEXT:    xscvdpuxds f0, f0
1545; CHECK-FISL-NEXT:    stfd f0, -24(r1)
1546; CHECK-FISL-NEXT:    ld r3, -32(r1)
1547; CHECK-FISL-NEXT:    std r3, -8(r1)
1548; CHECK-FISL-NEXT:    ld r3, -24(r1)
1549; CHECK-FISL-NEXT:    std r3, -16(r1)
1550; CHECK-FISL-NEXT:    addi r3, r1, -16
1551; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
1552; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
1553; CHECK-FISL-NEXT:    blr
1554;
1555; CHECK-LE-LABEL: test46:
1556; CHECK-LE:       # %bb.0:
1557; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
1558; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
1559; CHECK-LE-NEXT:    xvcvdpuxds v2, vs0
1560; CHECK-LE-NEXT:    blr
1561  %v = fptoui <2 x float> %a to <2 x i64>
1562  ret <2 x i64> %v
1563
1564; FIXME: The code quality here looks pretty bad.
1565}
1566
1567define <2 x i64> @test47(<2 x float> %a) {
1568; CHECK-LABEL: test47:
1569; CHECK:       # %bb.0:
1570; CHECK-NEXT:    addi r3, r1, -48
1571; CHECK-NEXT:    stxvw4x v2, 0, r3
1572; CHECK-NEXT:    lfs f0, -44(r1)
1573; CHECK-NEXT:    xscvdpsxds f0, f0
1574; CHECK-NEXT:    stfd f0, -32(r1)
1575; CHECK-NEXT:    lfs f0, -48(r1)
1576; CHECK-NEXT:    xscvdpsxds f0, f0
1577; CHECK-NEXT:    stfd f0, -24(r1)
1578; CHECK-NEXT:    ld r3, -32(r1)
1579; CHECK-NEXT:    std r3, -8(r1)
1580; CHECK-NEXT:    ld r3, -24(r1)
1581; CHECK-NEXT:    std r3, -16(r1)
1582; CHECK-NEXT:    addi r3, r1, -16
1583; CHECK-NEXT:    lxvd2x v2, 0, r3
1584; CHECK-NEXT:    blr
1585;
1586; CHECK-REG-LABEL: test47:
1587; CHECK-REG:       # %bb.0:
1588; CHECK-REG-NEXT:    addi r3, r1, -48
1589; CHECK-REG-NEXT:    stxvw4x v2, 0, r3
1590; CHECK-REG-NEXT:    lfs f0, -44(r1)
1591; CHECK-REG-NEXT:    xscvdpsxds f0, f0
1592; CHECK-REG-NEXT:    stfd f0, -32(r1)
1593; CHECK-REG-NEXT:    lfs f0, -48(r1)
1594; CHECK-REG-NEXT:    xscvdpsxds f0, f0
1595; CHECK-REG-NEXT:    stfd f0, -24(r1)
1596; CHECK-REG-NEXT:    ld r3, -32(r1)
1597; CHECK-REG-NEXT:    std r3, -8(r1)
1598; CHECK-REG-NEXT:    ld r3, -24(r1)
1599; CHECK-REG-NEXT:    std r3, -16(r1)
1600; CHECK-REG-NEXT:    addi r3, r1, -16
1601; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1602; CHECK-REG-NEXT:    blr
1603;
1604; CHECK-FISL-LABEL: test47:
1605; CHECK-FISL:       # %bb.0:
1606; CHECK-FISL-NEXT:    addi r3, r1, -48
1607; CHECK-FISL-NEXT:    stxvw4x v2, 0, r3
1608; CHECK-FISL-NEXT:    lfs f0, -44(r1)
1609; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
1610; CHECK-FISL-NEXT:    stfd f0, -32(r1)
1611; CHECK-FISL-NEXT:    lfs f0, -48(r1)
1612; CHECK-FISL-NEXT:    xscvdpsxds f0, f0
1613; CHECK-FISL-NEXT:    stfd f0, -24(r1)
1614; CHECK-FISL-NEXT:    ld r3, -32(r1)
1615; CHECK-FISL-NEXT:    std r3, -8(r1)
1616; CHECK-FISL-NEXT:    ld r3, -24(r1)
1617; CHECK-FISL-NEXT:    std r3, -16(r1)
1618; CHECK-FISL-NEXT:    addi r3, r1, -16
1619; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
1620; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
1621; CHECK-FISL-NEXT:    blr
1622;
1623; CHECK-LE-LABEL: test47:
1624; CHECK-LE:       # %bb.0:
1625; CHECK-LE-NEXT:    xxmrglw vs0, v2, v2
1626; CHECK-LE-NEXT:    xvcvspdp vs0, vs0
1627; CHECK-LE-NEXT:    xvcvdpsxds v2, vs0
1628; CHECK-LE-NEXT:    blr
1629  %v = fptosi <2 x float> %a to <2 x i64>
1630  ret <2 x i64> %v
1631
1632; FIXME: The code quality here looks pretty bad.
1633}
1634
1635define <2 x double> @test50(double* %a) {
1636; CHECK-LABEL: test50:
1637; CHECK:       # %bb.0:
1638; CHECK-NEXT:    lxvdsx v2, 0, r3
1639; CHECK-NEXT:    blr
1640;
1641; CHECK-REG-LABEL: test50:
1642; CHECK-REG:       # %bb.0:
1643; CHECK-REG-NEXT:    lxvdsx v2, 0, r3
1644; CHECK-REG-NEXT:    blr
1645;
1646; CHECK-FISL-LABEL: test50:
1647; CHECK-FISL:       # %bb.0:
1648; CHECK-FISL-NEXT:    lxvdsx v2, 0, r3
1649; CHECK-FISL-NEXT:    blr
1650;
1651; CHECK-LE-LABEL: test50:
1652; CHECK-LE:       # %bb.0:
1653; CHECK-LE-NEXT:    lxvdsx v2, 0, r3
1654; CHECK-LE-NEXT:    blr
1655  %v = load double, double* %a, align 8
1656  %w = insertelement <2 x double> undef, double %v, i32 0
1657  %x = insertelement <2 x double> %w, double %v, i32 1
1658  ret <2 x double> %x
1659
1660
1661}
1662
1663define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
1664; CHECK-LABEL: test51:
1665; CHECK:       # %bb.0:
1666; CHECK-NEXT:    xxspltd v2, v2, 0
1667; CHECK-NEXT:    blr
1668;
1669; CHECK-REG-LABEL: test51:
1670; CHECK-REG:       # %bb.0:
1671; CHECK-REG-NEXT:    xxspltd v2, v2, 0
1672; CHECK-REG-NEXT:    blr
1673;
1674; CHECK-FISL-LABEL: test51:
1675; CHECK-FISL:       # %bb.0:
1676; CHECK-FISL-NEXT:    xxspltd v2, v2, 0
1677; CHECK-FISL-NEXT:    blr
1678;
1679; CHECK-LE-LABEL: test51:
1680; CHECK-LE:       # %bb.0:
1681; CHECK-LE-NEXT:    xxspltd v2, v2, 1
1682; CHECK-LE-NEXT:    blr
1683  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
1684  ret <2 x double> %v
1685
1686
1687}
1688
1689define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
1690; CHECK-LABEL: test52:
1691; CHECK:       # %bb.0:
1692; CHECK-NEXT:    xxmrghd v2, v2, v3
1693; CHECK-NEXT:    blr
1694;
1695; CHECK-REG-LABEL: test52:
1696; CHECK-REG:       # %bb.0:
1697; CHECK-REG-NEXT:    xxmrghd v2, v2, v3
1698; CHECK-REG-NEXT:    blr
1699;
1700; CHECK-FISL-LABEL: test52:
1701; CHECK-FISL:       # %bb.0:
1702; CHECK-FISL-NEXT:    xxmrghd v2, v2, v3
1703; CHECK-FISL-NEXT:    blr
1704;
1705; CHECK-LE-LABEL: test52:
1706; CHECK-LE:       # %bb.0:
1707; CHECK-LE-NEXT:    xxmrgld v2, v3, v2
1708; CHECK-LE-NEXT:    blr
1709  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
1710  ret <2 x double> %v
1711
1712
1713}
1714
1715define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
1716; CHECK-LABEL: test53:
1717; CHECK:       # %bb.0:
1718; CHECK-NEXT:    xxmrghd v2, v3, v2
1719; CHECK-NEXT:    blr
1720;
1721; CHECK-REG-LABEL: test53:
1722; CHECK-REG:       # %bb.0:
1723; CHECK-REG-NEXT:    xxmrghd v2, v3, v2
1724; CHECK-REG-NEXT:    blr
1725;
1726; CHECK-FISL-LABEL: test53:
1727; CHECK-FISL:       # %bb.0:
1728; CHECK-FISL-NEXT:    xxmrghd v2, v3, v2
1729; CHECK-FISL-NEXT:    blr
1730;
1731; CHECK-LE-LABEL: test53:
1732; CHECK-LE:       # %bb.0:
1733; CHECK-LE-NEXT:    xxmrgld v2, v2, v3
1734; CHECK-LE-NEXT:    blr
1735  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
1736  ret <2 x double> %v
1737
1738
1739}
1740
1741define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
1742; CHECK-LABEL: test54:
1743; CHECK:       # %bb.0:
1744; CHECK-NEXT:    xxpermdi v2, v2, v3, 2
1745; CHECK-NEXT:    blr
1746;
1747; CHECK-REG-LABEL: test54:
1748; CHECK-REG:       # %bb.0:
1749; CHECK-REG-NEXT:    xxpermdi v2, v2, v3, 2
1750; CHECK-REG-NEXT:    blr
1751;
1752; CHECK-FISL-LABEL: test54:
1753; CHECK-FISL:       # %bb.0:
1754; CHECK-FISL-NEXT:    xxpermdi v2, v2, v3, 2
1755; CHECK-FISL-NEXT:    blr
1756;
1757; CHECK-LE-LABEL: test54:
1758; CHECK-LE:       # %bb.0:
1759; CHECK-LE-NEXT:    xxpermdi v2, v3, v2, 2
1760; CHECK-LE-NEXT:    blr
1761  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
1762  ret <2 x double> %v
1763
1764
1765}
1766
1767define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
1768; CHECK-LABEL: test55:
1769; CHECK:       # %bb.0:
1770; CHECK-NEXT:    xxmrgld v2, v2, v3
1771; CHECK-NEXT:    blr
1772;
1773; CHECK-REG-LABEL: test55:
1774; CHECK-REG:       # %bb.0:
1775; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
1776; CHECK-REG-NEXT:    blr
1777;
1778; CHECK-FISL-LABEL: test55:
1779; CHECK-FISL:       # %bb.0:
1780; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
1781; CHECK-FISL-NEXT:    blr
1782;
1783; CHECK-LE-LABEL: test55:
1784; CHECK-LE:       # %bb.0:
1785; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
1786; CHECK-LE-NEXT:    blr
1787  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
1788  ret <2 x double> %v
1789
1790
1791}
1792
1793define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
1794; CHECK-LABEL: test56:
1795; CHECK:       # %bb.0:
1796; CHECK-NEXT:    xxmrgld v2, v2, v3
1797; CHECK-NEXT:    blr
1798;
1799; CHECK-REG-LABEL: test56:
1800; CHECK-REG:       # %bb.0:
1801; CHECK-REG-NEXT:    xxmrgld v2, v2, v3
1802; CHECK-REG-NEXT:    blr
1803;
1804; CHECK-FISL-LABEL: test56:
1805; CHECK-FISL:       # %bb.0:
1806; CHECK-FISL-NEXT:    xxmrgld v2, v2, v3
1807; CHECK-FISL-NEXT:    blr
1808;
1809; CHECK-LE-LABEL: test56:
1810; CHECK-LE:       # %bb.0:
1811; CHECK-LE-NEXT:    xxmrghd v2, v3, v2
1812; CHECK-LE-NEXT:    blr
1813  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
1814  ret <2 x i64> %v
1815
1816
1817}
1818
1819define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
1820; CHECK-LABEL: test60:
1821; CHECK:       # %bb.0:
1822; CHECK-NEXT:    addi r3, r1, -32
1823; CHECK-NEXT:    addi r4, r1, -48
1824; CHECK-NEXT:    stxvd2x v3, 0, r3
1825; CHECK-NEXT:    stxvd2x v2, 0, r4
1826; CHECK-NEXT:    lwz r3, -20(r1)
1827; CHECK-NEXT:    ld r4, -40(r1)
1828; CHECK-NEXT:    sld r3, r4, r3
1829; CHECK-NEXT:    ld r4, -48(r1)
1830; CHECK-NEXT:    std r3, -8(r1)
1831; CHECK-NEXT:    lwz r3, -28(r1)
1832; CHECK-NEXT:    sld r3, r4, r3
1833; CHECK-NEXT:    std r3, -16(r1)
1834; CHECK-NEXT:    addi r3, r1, -16
1835; CHECK-NEXT:    lxvd2x v2, 0, r3
1836; CHECK-NEXT:    blr
1837;
1838; CHECK-REG-LABEL: test60:
1839; CHECK-REG:       # %bb.0:
1840; CHECK-REG-NEXT:    addi r3, r1, -32
1841; CHECK-REG-NEXT:    addi r4, r1, -48
1842; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1843; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
1844; CHECK-REG-NEXT:    lwz r3, -20(r1)
1845; CHECK-REG-NEXT:    ld r4, -40(r1)
1846; CHECK-REG-NEXT:    sld r3, r4, r3
1847; CHECK-REG-NEXT:    ld r4, -48(r1)
1848; CHECK-REG-NEXT:    std r3, -8(r1)
1849; CHECK-REG-NEXT:    lwz r3, -28(r1)
1850; CHECK-REG-NEXT:    sld r3, r4, r3
1851; CHECK-REG-NEXT:    std r3, -16(r1)
1852; CHECK-REG-NEXT:    addi r3, r1, -16
1853; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1854; CHECK-REG-NEXT:    blr
1855;
1856; CHECK-FISL-LABEL: test60:
1857; CHECK-FISL:       # %bb.0:
1858; CHECK-FISL-NEXT:    addi r3, r1, -32
1859; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1860; CHECK-FISL-NEXT:    addi r3, r1, -48
1861; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1862; CHECK-FISL-NEXT:    lwz r3, -20(r1)
1863; CHECK-FISL-NEXT:    ld r4, -40(r1)
1864; CHECK-FISL-NEXT:    sld r3, r4, r3
1865; CHECK-FISL-NEXT:    std r3, -8(r1)
1866; CHECK-FISL-NEXT:    lwz r3, -28(r1)
1867; CHECK-FISL-NEXT:    ld r4, -48(r1)
1868; CHECK-FISL-NEXT:    sld r3, r4, r3
1869; CHECK-FISL-NEXT:    std r3, -16(r1)
1870; CHECK-FISL-NEXT:    addi r3, r1, -16
1871; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
1872; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
1873; CHECK-FISL-NEXT:    blr
1874;
1875; CHECK-LE-LABEL: test60:
1876; CHECK-LE:       # %bb.0:
1877; CHECK-LE-NEXT:    vsld v2, v2, v3
1878; CHECK-LE-NEXT:    blr
1879  %v = shl <2 x i64> %a, %b
1880  ret <2 x i64> %v
1881
1882; This should scalarize, and the current code quality is not good.
1883}
1884
1885define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
1886; CHECK-LABEL: test61:
1887; CHECK:       # %bb.0:
1888; CHECK-NEXT:    addi r3, r1, -32
1889; CHECK-NEXT:    addi r4, r1, -48
1890; CHECK-NEXT:    stxvd2x v3, 0, r3
1891; CHECK-NEXT:    stxvd2x v2, 0, r4
1892; CHECK-NEXT:    lwz r3, -20(r1)
1893; CHECK-NEXT:    ld r4, -40(r1)
1894; CHECK-NEXT:    srd r3, r4, r3
1895; CHECK-NEXT:    ld r4, -48(r1)
1896; CHECK-NEXT:    std r3, -8(r1)
1897; CHECK-NEXT:    lwz r3, -28(r1)
1898; CHECK-NEXT:    srd r3, r4, r3
1899; CHECK-NEXT:    std r3, -16(r1)
1900; CHECK-NEXT:    addi r3, r1, -16
1901; CHECK-NEXT:    lxvd2x v2, 0, r3
1902; CHECK-NEXT:    blr
1903;
1904; CHECK-REG-LABEL: test61:
1905; CHECK-REG:       # %bb.0:
1906; CHECK-REG-NEXT:    addi r3, r1, -32
1907; CHECK-REG-NEXT:    addi r4, r1, -48
1908; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1909; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
1910; CHECK-REG-NEXT:    lwz r3, -20(r1)
1911; CHECK-REG-NEXT:    ld r4, -40(r1)
1912; CHECK-REG-NEXT:    srd r3, r4, r3
1913; CHECK-REG-NEXT:    ld r4, -48(r1)
1914; CHECK-REG-NEXT:    std r3, -8(r1)
1915; CHECK-REG-NEXT:    lwz r3, -28(r1)
1916; CHECK-REG-NEXT:    srd r3, r4, r3
1917; CHECK-REG-NEXT:    std r3, -16(r1)
1918; CHECK-REG-NEXT:    addi r3, r1, -16
1919; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1920; CHECK-REG-NEXT:    blr
1921;
1922; CHECK-FISL-LABEL: test61:
1923; CHECK-FISL:       # %bb.0:
1924; CHECK-FISL-NEXT:    addi r3, r1, -32
1925; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1926; CHECK-FISL-NEXT:    addi r3, r1, -48
1927; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1928; CHECK-FISL-NEXT:    lwz r3, -20(r1)
1929; CHECK-FISL-NEXT:    ld r4, -40(r1)
1930; CHECK-FISL-NEXT:    srd r3, r4, r3
1931; CHECK-FISL-NEXT:    std r3, -8(r1)
1932; CHECK-FISL-NEXT:    lwz r3, -28(r1)
1933; CHECK-FISL-NEXT:    ld r4, -48(r1)
1934; CHECK-FISL-NEXT:    srd r3, r4, r3
1935; CHECK-FISL-NEXT:    std r3, -16(r1)
1936; CHECK-FISL-NEXT:    addi r3, r1, -16
1937; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
1938; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
1939; CHECK-FISL-NEXT:    blr
1940;
1941; CHECK-LE-LABEL: test61:
1942; CHECK-LE:       # %bb.0:
1943; CHECK-LE-NEXT:    vsrd v2, v2, v3
1944; CHECK-LE-NEXT:    blr
1945  %v = lshr <2 x i64> %a, %b
1946  ret <2 x i64> %v
1947
1948; This should scalarize, and the current code quality is not good.
1949}
1950
1951define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
1952; CHECK-LABEL: test62:
1953; CHECK:       # %bb.0:
1954; CHECK-NEXT:    addi r3, r1, -32
1955; CHECK-NEXT:    addi r4, r1, -48
1956; CHECK-NEXT:    stxvd2x v3, 0, r3
1957; CHECK-NEXT:    stxvd2x v2, 0, r4
1958; CHECK-NEXT:    lwz r3, -20(r1)
1959; CHECK-NEXT:    ld r4, -40(r1)
1960; CHECK-NEXT:    srad r3, r4, r3
1961; CHECK-NEXT:    ld r4, -48(r1)
1962; CHECK-NEXT:    std r3, -8(r1)
1963; CHECK-NEXT:    lwz r3, -28(r1)
1964; CHECK-NEXT:    srad r3, r4, r3
1965; CHECK-NEXT:    std r3, -16(r1)
1966; CHECK-NEXT:    addi r3, r1, -16
1967; CHECK-NEXT:    lxvd2x v2, 0, r3
1968; CHECK-NEXT:    blr
1969;
1970; CHECK-REG-LABEL: test62:
1971; CHECK-REG:       # %bb.0:
1972; CHECK-REG-NEXT:    addi r3, r1, -32
1973; CHECK-REG-NEXT:    addi r4, r1, -48
1974; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
1975; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
1976; CHECK-REG-NEXT:    lwz r3, -20(r1)
1977; CHECK-REG-NEXT:    ld r4, -40(r1)
1978; CHECK-REG-NEXT:    srad r3, r4, r3
1979; CHECK-REG-NEXT:    ld r4, -48(r1)
1980; CHECK-REG-NEXT:    std r3, -8(r1)
1981; CHECK-REG-NEXT:    lwz r3, -28(r1)
1982; CHECK-REG-NEXT:    srad r3, r4, r3
1983; CHECK-REG-NEXT:    std r3, -16(r1)
1984; CHECK-REG-NEXT:    addi r3, r1, -16
1985; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
1986; CHECK-REG-NEXT:    blr
1987;
1988; CHECK-FISL-LABEL: test62:
1989; CHECK-FISL:       # %bb.0:
1990; CHECK-FISL-NEXT:    addi r3, r1, -32
1991; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
1992; CHECK-FISL-NEXT:    addi r3, r1, -48
1993; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
1994; CHECK-FISL-NEXT:    lwz r3, -20(r1)
1995; CHECK-FISL-NEXT:    ld r4, -40(r1)
1996; CHECK-FISL-NEXT:    srad r3, r4, r3
1997; CHECK-FISL-NEXT:    std r3, -8(r1)
1998; CHECK-FISL-NEXT:    lwz r3, -28(r1)
1999; CHECK-FISL-NEXT:    ld r4, -48(r1)
2000; CHECK-FISL-NEXT:    srad r3, r4, r3
2001; CHECK-FISL-NEXT:    std r3, -16(r1)
2002; CHECK-FISL-NEXT:    addi r3, r1, -16
2003; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
2004; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
2005; CHECK-FISL-NEXT:    blr
2006;
2007; CHECK-LE-LABEL: test62:
2008; CHECK-LE:       # %bb.0:
2009; CHECK-LE-NEXT:    vsrad v2, v2, v3
2010; CHECK-LE-NEXT:    blr
2011  %v = ashr <2 x i64> %a, %b
2012  ret <2 x i64> %v
2013
2014; This should scalarize, and the current code quality is not good.
2015}
2016
2017define double @test63(<2 x double> %a) {
2018; CHECK-LABEL: test63:
2019; CHECK:       # %bb.0:
2020; CHECK-NEXT:    xxlor f1, v2, v2
2021; CHECK-NEXT:    blr
2022;
2023; CHECK-REG-LABEL: test63:
2024; CHECK-REG:       # %bb.0:
2025; CHECK-REG-NEXT:    xxlor f1, v2, v2
2026; CHECK-REG-NEXT:    blr
2027;
2028; CHECK-FISL-LABEL: test63:
2029; CHECK-FISL:       # %bb.0:
2030; CHECK-FISL-NEXT:    # kill: def $vf2 killed $vf2 killed $v2
2031; CHECK-FISL-NEXT:    xxlor f1, v2, v2
2032; CHECK-FISL-NEXT:    blr
2033;
2034; CHECK-LE-LABEL: test63:
2035; CHECK-LE:       # %bb.0:
2036; CHECK-LE-NEXT:    xxswapd vs1, v2
2037; CHECK-LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
2038; CHECK-LE-NEXT:    blr
2039  %v = extractelement <2 x double> %a, i32 0
2040  ret double %v
2041
2042
2043
2044}
2045
2046define double @test64(<2 x double> %a) {
2047; CHECK-LABEL: test64:
2048; CHECK:       # %bb.0:
2049; CHECK-NEXT:    xxswapd vs1, v2
2050; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
2051; CHECK-NEXT:    blr
2052;
2053; CHECK-REG-LABEL: test64:
2054; CHECK-REG:       # %bb.0:
2055; CHECK-REG-NEXT:    xxswapd vs1, v2
2056; CHECK-REG-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
2057; CHECK-REG-NEXT:    blr
2058;
2059; CHECK-FISL-LABEL: test64:
2060; CHECK-FISL:       # %bb.0:
2061; CHECK-FISL-NEXT:    xxswapd vs0, v2
2062; CHECK-FISL-NEXT:    # kill: def $f0 killed $f0 killed $vsl0
2063; CHECK-FISL-NEXT:    fmr f1, f0
2064; CHECK-FISL-NEXT:    blr
2065;
2066; CHECK-LE-LABEL: test64:
2067; CHECK-LE:       # %bb.0:
2068; CHECK-LE-NEXT:    xxlor f1, v2, v2
2069; CHECK-LE-NEXT:    blr
2070  %v = extractelement <2 x double> %a, i32 1
2071  ret double %v
2072
2073
2074
2075}
2076
2077define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
2078; CHECK-LABEL: test65:
2079; CHECK:       # %bb.0:
2080; CHECK-NEXT:    vcmpequw v2, v2, v3
2081; CHECK-NEXT:    blr
2082;
2083; CHECK-REG-LABEL: test65:
2084; CHECK-REG:       # %bb.0:
2085; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
2086; CHECK-REG-NEXT:    blr
2087;
2088; CHECK-FISL-LABEL: test65:
2089; CHECK-FISL:       # %bb.0:
2090; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3
2091; CHECK-FISL-NEXT:    blr
2092;
2093; CHECK-LE-LABEL: test65:
2094; CHECK-LE:       # %bb.0:
2095; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
2096; CHECK-LE-NEXT:    blr
2097  %w = icmp eq <2 x i64> %a, %b
2098  ret <2 x i1> %w
2099
2100
2101
2102}
2103
2104define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
2105; CHECK-LABEL: test66:
2106; CHECK:       # %bb.0:
2107; CHECK-NEXT:    vcmpequw v2, v2, v3
2108; CHECK-NEXT:    xxlnor v2, v2, v2
2109; CHECK-NEXT:    blr
2110;
2111; CHECK-REG-LABEL: test66:
2112; CHECK-REG:       # %bb.0:
2113; CHECK-REG-NEXT:    vcmpequw v2, v2, v3
2114; CHECK-REG-NEXT:    xxlnor v2, v2, v2
2115; CHECK-REG-NEXT:    blr
2116;
2117; CHECK-FISL-LABEL: test66:
2118; CHECK-FISL:       # %bb.0:
2119; CHECK-FISL-NEXT:    vcmpequw v2, v2, v3
2120; CHECK-FISL-NEXT:    xxlnor vs0, v2, v2
2121; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
2122; CHECK-FISL-NEXT:    blr
2123;
2124; CHECK-LE-LABEL: test66:
2125; CHECK-LE:       # %bb.0:
2126; CHECK-LE-NEXT:    vcmpequd v2, v2, v3
2127; CHECK-LE-NEXT:    xxlnor v2, v2, v2
2128; CHECK-LE-NEXT:    blr
2129  %w = icmp ne <2 x i64> %a, %b
2130  ret <2 x i1> %w
2131
2132
2133
2134}
2135
2136define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
2137; CHECK-LABEL: test67:
2138; CHECK:       # %bb.0:
2139; CHECK-NEXT:    addi r3, r1, -32
2140; CHECK-NEXT:    addi r4, r1, -48
2141; CHECK-NEXT:    stxvd2x v3, 0, r3
2142; CHECK-NEXT:    stxvd2x v2, 0, r4
2143; CHECK-NEXT:    ld r3, -24(r1)
2144; CHECK-NEXT:    ld r4, -40(r1)
2145; CHECK-NEXT:    ld r6, -48(r1)
2146; CHECK-NEXT:    cmpld r4, r3
2147; CHECK-NEXT:    li r3, 0
2148; CHECK-NEXT:    li r4, -1
2149; CHECK-NEXT:    isellt r5, r4, r3
2150; CHECK-NEXT:    std r5, -8(r1)
2151; CHECK-NEXT:    ld r5, -32(r1)
2152; CHECK-NEXT:    cmpld r6, r5
2153; CHECK-NEXT:    isellt r3, r4, r3
2154; CHECK-NEXT:    std r3, -16(r1)
2155; CHECK-NEXT:    addi r3, r1, -16
2156; CHECK-NEXT:    lxvd2x v2, 0, r3
2157; CHECK-NEXT:    blr
2158;
2159; CHECK-REG-LABEL: test67:
2160; CHECK-REG:       # %bb.0:
2161; CHECK-REG-NEXT:    addi r3, r1, -32
2162; CHECK-REG-NEXT:    addi r4, r1, -48
2163; CHECK-REG-NEXT:    stxvd2x v3, 0, r3
2164; CHECK-REG-NEXT:    stxvd2x v2, 0, r4
2165; CHECK-REG-NEXT:    ld r3, -24(r1)
2166; CHECK-REG-NEXT:    ld r4, -40(r1)
2167; CHECK-REG-NEXT:    ld r6, -48(r1)
2168; CHECK-REG-NEXT:    cmpld r4, r3
2169; CHECK-REG-NEXT:    li r3, 0
2170; CHECK-REG-NEXT:    li r4, -1
2171; CHECK-REG-NEXT:    isellt r5, r4, r3
2172; CHECK-REG-NEXT:    std r5, -8(r1)
2173; CHECK-REG-NEXT:    ld r5, -32(r1)
2174; CHECK-REG-NEXT:    cmpld r6, r5
2175; CHECK-REG-NEXT:    isellt r3, r4, r3
2176; CHECK-REG-NEXT:    std r3, -16(r1)
2177; CHECK-REG-NEXT:    addi r3, r1, -16
2178; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2179; CHECK-REG-NEXT:    blr
2180;
2181; CHECK-FISL-LABEL: test67:
2182; CHECK-FISL:       # %bb.0:
2183; CHECK-FISL-NEXT:    addi r3, r1, -32
2184; CHECK-FISL-NEXT:    stxvd2x v3, 0, r3
2185; CHECK-FISL-NEXT:    addi r3, r1, -48
2186; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
2187; CHECK-FISL-NEXT:    ld r3, -24(r1)
2188; CHECK-FISL-NEXT:    ld r4, -40(r1)
2189; CHECK-FISL-NEXT:    cmpld r4, r3
2190; CHECK-FISL-NEXT:    li r3, 0
2191; CHECK-FISL-NEXT:    li r4, -1
2192; CHECK-FISL-NEXT:    isellt r5, r4, r3
2193; CHECK-FISL-NEXT:    std r5, -8(r1)
2194; CHECK-FISL-NEXT:    ld r5, -32(r1)
2195; CHECK-FISL-NEXT:    ld r6, -48(r1)
2196; CHECK-FISL-NEXT:    cmpld r6, r5
2197; CHECK-FISL-NEXT:    isellt r3, r4, r3
2198; CHECK-FISL-NEXT:    std r3, -16(r1)
2199; CHECK-FISL-NEXT:    addi r3, r1, -16
2200; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
2201; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
2202; CHECK-FISL-NEXT:    blr
2203;
2204; CHECK-LE-LABEL: test67:
2205; CHECK-LE:       # %bb.0:
2206; CHECK-LE-NEXT:    vcmpgtud v2, v3, v2
2207; CHECK-LE-NEXT:    blr
2208  %w = icmp ult <2 x i64> %a, %b
2209  ret <2 x i1> %w
2210
2211; This should scalarize, and the current code quality is not good.
2212
2213}
2214
2215define <2 x double> @test68(<2 x i32> %a) {
2216; CHECK-LABEL: test68:
2217; CHECK:       # %bb.0:
2218; CHECK-NEXT:    xxmrghw vs0, v2, v2
2219; CHECK-NEXT:    xvcvsxwdp v2, vs0
2220; CHECK-NEXT:    blr
2221;
2222; CHECK-REG-LABEL: test68:
2223; CHECK-REG:       # %bb.0:
2224; CHECK-REG-NEXT:    xxmrghw vs0, v2, v2
2225; CHECK-REG-NEXT:    xvcvsxwdp v2, vs0
2226; CHECK-REG-NEXT:    blr
2227;
2228; CHECK-FISL-LABEL: test68:
2229; CHECK-FISL:       # %bb.0:
2230; CHECK-FISL-NEXT:    xxmrghw vs0, v2, v2
2231; CHECK-FISL-NEXT:    xvcvsxwdp v2, vs0
2232; CHECK-FISL-NEXT:    blr
2233;
2234; CHECK-LE-LABEL: test68:
2235; CHECK-LE:       # %bb.0:
2236; CHECK-LE-NEXT:    xxmrglw v2, v2, v2
2237; CHECK-LE-NEXT:    xvcvsxwdp v2, v2
2238; CHECK-LE-NEXT:    blr
2239  %w = sitofp <2 x i32> %a to <2 x double>
2240  ret <2 x double> %w
2241
2242
2243}
2244
2245; This gets scalarized so the code isn't great
2246define <2 x double> @test69(<2 x i16> %a) {
2247; CHECK-LABEL: test69:
2248; CHECK:       # %bb.0:
2249; CHECK-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2250; CHECK-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2251; CHECK-NEXT:    lxvw4x v3, 0, r3
2252; CHECK-NEXT:    addi r3, r1, -32
2253; CHECK-NEXT:    vperm v2, v2, v2, v3
2254; CHECK-NEXT:    stxvd2x v2, 0, r3
2255; CHECK-NEXT:    lha r3, -18(r1)
2256; CHECK-NEXT:    std r3, -8(r1)
2257; CHECK-NEXT:    lha r3, -26(r1)
2258; CHECK-NEXT:    std r3, -16(r1)
2259; CHECK-NEXT:    addi r3, r1, -16
2260; CHECK-NEXT:    lxvd2x v2, 0, r3
2261; CHECK-NEXT:    xvcvsxddp v2, v2
2262; CHECK-NEXT:    blr
2263;
2264; CHECK-REG-LABEL: test69:
2265; CHECK-REG:       # %bb.0:
2266; CHECK-REG-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2267; CHECK-REG-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2268; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2269; CHECK-REG-NEXT:    addi r3, r1, -32
2270; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
2271; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
2272; CHECK-REG-NEXT:    lha r3, -18(r1)
2273; CHECK-REG-NEXT:    std r3, -8(r1)
2274; CHECK-REG-NEXT:    lha r3, -26(r1)
2275; CHECK-REG-NEXT:    std r3, -16(r1)
2276; CHECK-REG-NEXT:    addi r3, r1, -16
2277; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2278; CHECK-REG-NEXT:    xvcvsxddp v2, v2
2279; CHECK-REG-NEXT:    blr
2280;
2281; CHECK-FISL-LABEL: test69:
2282; CHECK-FISL:       # %bb.0:
2283; CHECK-FISL-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2284; CHECK-FISL-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2285; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2286; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
2287; CHECK-FISL-NEXT:    addi r3, r1, -32
2288; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
2289; CHECK-FISL-NEXT:    lha r3, -18(r1)
2290; CHECK-FISL-NEXT:    std r3, -8(r1)
2291; CHECK-FISL-NEXT:    lha r3, -26(r1)
2292; CHECK-FISL-NEXT:    std r3, -16(r1)
2293; CHECK-FISL-NEXT:    addi r3, r1, -16
2294; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
2295; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
2296; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
2297; CHECK-FISL-NEXT:    blr
2298;
2299; CHECK-LE-LABEL: test69:
2300; CHECK-LE:       # %bb.0:
2301; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_0@toc@ha
2302; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_0@toc@l
2303; CHECK-LE-NEXT:    lvx v3, 0, r3
2304; CHECK-LE-NEXT:    addis r3, r2, .LCPI63_1@toc@ha
2305; CHECK-LE-NEXT:    addi r3, r3, .LCPI63_1@toc@l
2306; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
2307; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
2308; CHECK-LE-NEXT:    xxswapd v3, vs0
2309; CHECK-LE-NEXT:    vsld v2, v2, v3
2310; CHECK-LE-NEXT:    vsrad v2, v2, v3
2311; CHECK-LE-NEXT:    xvcvsxddp v2, v2
2312; CHECK-LE-NEXT:    blr
2313  %w = sitofp <2 x i16> %a to <2 x double>
2314  ret <2 x double> %w
2315
2316
2317}
2318
2319; This gets scalarized so the code isn't great
2320define <2 x double> @test70(<2 x i8> %a) {
2321; CHECK-LABEL: test70:
2322; CHECK:       # %bb.0:
2323; CHECK-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2324; CHECK-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2325; CHECK-NEXT:    lxvw4x v3, 0, r3
2326; CHECK-NEXT:    addi r3, r1, -32
2327; CHECK-NEXT:    vperm v2, v2, v2, v3
2328; CHECK-NEXT:    stxvd2x v2, 0, r3
2329; CHECK-NEXT:    ld r3, -24(r1)
2330; CHECK-NEXT:    extsb r3, r3
2331; CHECK-NEXT:    std r3, -8(r1)
2332; CHECK-NEXT:    ld r3, -32(r1)
2333; CHECK-NEXT:    extsb r3, r3
2334; CHECK-NEXT:    std r3, -16(r1)
2335; CHECK-NEXT:    addi r3, r1, -16
2336; CHECK-NEXT:    lxvd2x v2, 0, r3
2337; CHECK-NEXT:    xvcvsxddp v2, v2
2338; CHECK-NEXT:    blr
2339;
2340; CHECK-REG-LABEL: test70:
2341; CHECK-REG:       # %bb.0:
2342; CHECK-REG-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2343; CHECK-REG-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2344; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2345; CHECK-REG-NEXT:    addi r3, r1, -32
2346; CHECK-REG-NEXT:    vperm v2, v2, v2, v3
2347; CHECK-REG-NEXT:    stxvd2x v2, 0, r3
2348; CHECK-REG-NEXT:    ld r3, -24(r1)
2349; CHECK-REG-NEXT:    extsb r3, r3
2350; CHECK-REG-NEXT:    std r3, -8(r1)
2351; CHECK-REG-NEXT:    ld r3, -32(r1)
2352; CHECK-REG-NEXT:    extsb r3, r3
2353; CHECK-REG-NEXT:    std r3, -16(r1)
2354; CHECK-REG-NEXT:    addi r3, r1, -16
2355; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
2356; CHECK-REG-NEXT:    xvcvsxddp v2, v2
2357; CHECK-REG-NEXT:    blr
2358;
2359; CHECK-FISL-LABEL: test70:
2360; CHECK-FISL:       # %bb.0:
2361; CHECK-FISL-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2362; CHECK-FISL-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2363; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2364; CHECK-FISL-NEXT:    vperm v2, v2, v2, v3
2365; CHECK-FISL-NEXT:    addi r3, r1, -32
2366; CHECK-FISL-NEXT:    stxvd2x v2, 0, r3
2367; CHECK-FISL-NEXT:    ld r3, -24(r1)
2368; CHECK-FISL-NEXT:    extsb r3, r3
2369; CHECK-FISL-NEXT:    std r3, -8(r1)
2370; CHECK-FISL-NEXT:    ld r3, -32(r1)
2371; CHECK-FISL-NEXT:    extsb r3, r3
2372; CHECK-FISL-NEXT:    std r3, -16(r1)
2373; CHECK-FISL-NEXT:    addi r3, r1, -16
2374; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3
2375; CHECK-FISL-NEXT:    xxlor v2, vs0, vs0
2376; CHECK-FISL-NEXT:    xvcvsxddp v2, v2
2377; CHECK-FISL-NEXT:    blr
2378;
2379; CHECK-LE-LABEL: test70:
2380; CHECK-LE:       # %bb.0:
2381; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_0@toc@ha
2382; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_0@toc@l
2383; CHECK-LE-NEXT:    lvx v3, 0, r3
2384; CHECK-LE-NEXT:    addis r3, r2, .LCPI64_1@toc@ha
2385; CHECK-LE-NEXT:    addi r3, r3, .LCPI64_1@toc@l
2386; CHECK-LE-NEXT:    lxvd2x vs0, 0, r3
2387; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
2388; CHECK-LE-NEXT:    xxswapd v3, vs0
2389; CHECK-LE-NEXT:    vsld v2, v2, v3
2390; CHECK-LE-NEXT:    vsrad v2, v2, v3
2391; CHECK-LE-NEXT:    xvcvsxddp v2, v2
2392; CHECK-LE-NEXT:    blr
2393  %w = sitofp <2 x i8> %a to <2 x double>
2394  ret <2 x double> %w
2395
2396
2397}
2398
2399; This gets scalarized so the code isn't great
2400define <2 x i32> @test80(i32 %v) {
2401; CHECK-LABEL: test80:
2402; CHECK:       # %bb.0:
2403; CHECK-NEXT:    addi r4, r1, -16
2404; CHECK-NEXT:    stw r3, -16(r1)
2405; CHECK-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2406; CHECK-NEXT:    lxvw4x vs0, 0, r4
2407; CHECK-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2408; CHECK-NEXT:    lxvw4x v3, 0, r3
2409; CHECK-NEXT:    xxspltw v2, vs0, 0
2410; CHECK-NEXT:    vadduwm v2, v2, v3
2411; CHECK-NEXT:    blr
2412;
2413; CHECK-REG-LABEL: test80:
2414; CHECK-REG:       # %bb.0:
2415; CHECK-REG-NEXT:    addi r4, r1, -16
2416; CHECK-REG-NEXT:    stw r3, -16(r1)
2417; CHECK-REG-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2418; CHECK-REG-NEXT:    lxvw4x vs0, 0, r4
2419; CHECK-REG-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2420; CHECK-REG-NEXT:    lxvw4x v3, 0, r3
2421; CHECK-REG-NEXT:    xxspltw v2, vs0, 0
2422; CHECK-REG-NEXT:    vadduwm v2, v2, v3
2423; CHECK-REG-NEXT:    blr
2424;
2425; CHECK-FISL-LABEL: test80:
2426; CHECK-FISL:       # %bb.0:
2427; CHECK-FISL-NEXT:    # kill: def $r3 killed $r3 killed $x3
2428; CHECK-FISL-NEXT:    stw r3, -16(r1)
2429; CHECK-FISL-NEXT:    addi r3, r1, -16
2430; CHECK-FISL-NEXT:    lxvw4x vs0, 0, r3
2431; CHECK-FISL-NEXT:    xxspltw v2, vs0, 0
2432; CHECK-FISL-NEXT:    addis r3, r2, .LCPI65_0@toc@ha
2433; CHECK-FISL-NEXT:    addi r3, r3, .LCPI65_0@toc@l
2434; CHECK-FISL-NEXT:    lxvw4x v3, 0, r3
2435; CHECK-FISL-NEXT:    vadduwm v2, v2, v3
2436; CHECK-FISL-NEXT:    blr
2437;
2438; CHECK-LE-LABEL: test80:
2439; CHECK-LE:       # %bb.0:
2440; CHECK-LE-NEXT:    mtfprwz f0, r3
2441; CHECK-LE-NEXT:    addis r4, r2, .LCPI65_0@toc@ha
2442; CHECK-LE-NEXT:    addi r3, r4, .LCPI65_0@toc@l
2443; CHECK-LE-NEXT:    xxspltw v2, vs0, 1
2444; CHECK-LE-NEXT:    lvx v3, 0, r3
2445; CHECK-LE-NEXT:    vadduwm v2, v2, v3
2446; CHECK-LE-NEXT:    blr
2447  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
2448  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
2449  %i = add <2 x i32> %b2, <i32 2, i32 3>
2450  ret <2 x i32> %i
2451
2452
2453
2454}
2455
2456define <2 x double> @test81(<4 x float> %b) {
2457; CHECK-LABEL: test81:
2458; CHECK:       # %bb.0:
2459; CHECK-NEXT:    blr
2460;
2461; CHECK-REG-LABEL: test81:
2462; CHECK-REG:       # %bb.0:
2463; CHECK-REG-NEXT:    blr
2464;
2465; CHECK-FISL-LABEL: test81:
2466; CHECK-FISL:       # %bb.0:
2467; CHECK-FISL-NEXT:    blr
2468;
2469; CHECK-LE-LABEL: test81:
2470; CHECK-LE:       # %bb.0:
2471; CHECK-LE-NEXT:    blr
2472  %w = bitcast <4 x float> %b to <2 x double>
2473  ret <2 x double> %w
2474
2475
2476}
2477
2478define double @test82(double %a, double %b, double %c, double %d) {
2479; CHECK-LABEL: test82:
2480; CHECK:       # %bb.0: # %entry
2481; CHECK-NEXT:    xscmpudp cr0, f3, f4
2482; CHECK-NEXT:    beqlr cr0
2483; CHECK-NEXT:  # %bb.1: # %entry
2484; CHECK-NEXT:    fmr f1, f2
2485; CHECK-NEXT:    blr
2486;
2487; CHECK-REG-LABEL: test82:
2488; CHECK-REG:       # %bb.0: # %entry
2489; CHECK-REG-NEXT:    xscmpudp cr0, f3, f4
2490; CHECK-REG-NEXT:    beqlr cr0
2491; CHECK-REG-NEXT:  # %bb.1: # %entry
2492; CHECK-REG-NEXT:    fmr f1, f2
2493; CHECK-REG-NEXT:    blr
2494;
2495; CHECK-FISL-LABEL: test82:
2496; CHECK-FISL:       # %bb.0: # %entry
2497; CHECK-FISL-NEXT:    xscmpudp cr0, f3, f4
2498; CHECK-FISL-NEXT:    stfd f2, -8(r1) # 8-byte Folded Spill
2499; CHECK-FISL-NEXT:    stfd f1, -16(r1) # 8-byte Folded Spill
2500; CHECK-FISL-NEXT:    beq cr0, .LBB67_2
2501; CHECK-FISL-NEXT:  # %bb.1: # %entry
2502; CHECK-FISL-NEXT:    lfd f0, -8(r1) # 8-byte Folded Reload
2503; CHECK-FISL-NEXT:    stfd f0, -16(r1) # 8-byte Folded Spill
2504; CHECK-FISL-NEXT:  .LBB67_2: # %entry
2505; CHECK-FISL-NEXT:    lfd f0, -16(r1) # 8-byte Folded Reload
2506; CHECK-FISL-NEXT:    fmr f1, f0
2507; CHECK-FISL-NEXT:    blr
2508;
2509; CHECK-LE-LABEL: test82:
2510; CHECK-LE:       # %bb.0: # %entry
2511; CHECK-LE-NEXT:    xscmpudp cr0, f3, f4
2512; CHECK-LE-NEXT:    beqlr cr0
2513; CHECK-LE-NEXT:  # %bb.1: # %entry
2514; CHECK-LE-NEXT:    fmr f1, f2
2515; CHECK-LE-NEXT:    blr
2516entry:
2517  %m = fcmp oeq double %c, %d
2518  %v = select i1 %m, double %a, double %b
2519  ret double %v
2520
2521
2522
2523}
2524