1; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s
2; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s
3; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s
4; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s
5; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s
6
7define double @test1(double %a, double %b) {
8entry:
9  %v = fmul double %a, %b
10  ret double %v
11
12; CHECK-LABEL: @test1
13; CHECK: xsmuldp 1, 1, 2
14; CHECK: blr
15
16; CHECK-LE-LABEL: @test1
17; CHECK-LE: xsmuldp 1, 1, 2
18; CHECK-LE: blr
19}
20
21define double @test2(double %a, double %b) {
22entry:
23  %v = fdiv double %a, %b
24  ret double %v
25
26; CHECK-LABEL: @test2
27; CHECK: xsdivdp 1, 1, 2
28; CHECK: blr
29
30; CHECK-LE-LABEL: @test2
31; CHECK-LE: xsdivdp 1, 1, 2
32; CHECK-LE: blr
33}
34
35define double @test3(double %a, double %b) {
36entry:
37  %v = fadd double %a, %b
38  ret double %v
39
40; CHECK-LABEL: @test3
41; CHECK: xsadddp 1, 1, 2
42; CHECK: blr
43
44; CHECK-LE-LABEL: @test3
45; CHECK-LE: xsadddp 1, 1, 2
46; CHECK-LE: blr
47}
48
49define <2 x double> @test4(<2 x double> %a, <2 x double> %b) {
50entry:
51  %v = fadd <2 x double> %a, %b
52  ret <2 x double> %v
53
54; CHECK-LABEL: @test4
55; CHECK: xvadddp 34, 34, 35
56; CHECK: blr
57
58; CHECK-LE-LABEL: @test4
59; CHECK-LE: xvadddp 34, 34, 35
60; CHECK-LE: blr
61}
62
63define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) {
64entry:
65  %v = xor <4 x i32> %a, %b
66  ret <4 x i32> %v
67
68; CHECK-REG-LABEL: @test5
69; CHECK-REG: xxlxor 34, 34, 35
70; CHECK-REG: blr
71
72; CHECK-FISL-LABEL: @test5
73; CHECK-FISL: xxlxor 34, 34, 35
74; CHECK-FISL: blr
75
76; CHECK-LE-LABEL: @test5
77; CHECK-LE: xxlxor 34, 34, 35
78; CHECK-LE: blr
79}
80
81define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
82entry:
83  %v = xor <8 x i16> %a, %b
84  ret <8 x i16> %v
85
86; CHECK-REG-LABEL: @test6
87; CHECK-REG: xxlxor 34, 34, 35
88; CHECK-REG: blr
89
90; CHECK-FISL-LABEL: @test6
91; CHECK-FISL: xxlxor 34, 34, 35
92; CHECK-FISL: blr
93
94; CHECK-LE-LABEL: @test6
95; CHECK-LE: xxlxor 34, 34, 35
96; CHECK-LE: blr
97}
98
99define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) {
100entry:
101  %v = xor <16 x i8> %a, %b
102  ret <16 x i8> %v
103
104; CHECK-REG-LABEL: @test7
105; CHECK-REG: xxlxor 34, 34, 35
106; CHECK-REG: blr
107
108; CHECK-FISL-LABEL: @test7
109; CHECK-FISL: xxlxor 34, 34, 35
110; CHECK-FISL: blr
111
112; CHECK-LE-LABEL: @test7
113; CHECK-LE: xxlxor 34, 34, 35
114; CHECK-LE: blr
115}
116
117define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) {
118entry:
119  %v = or <4 x i32> %a, %b
120  ret <4 x i32> %v
121
122; CHECK-REG-LABEL: @test8
123; CHECK-REG: xxlor 34, 34, 35
124; CHECK-REG: blr
125
126; CHECK-FISL-LABEL: @test8
127; CHECK-FISL: xxlor 34, 34, 35
128; CHECK-FISL: blr
129
130; CHECK-LE-LABEL: @test8
131; CHECK-LE: xxlor 34, 34, 35
132; CHECK-LE: blr
133}
134
135define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
136entry:
137  %v = or <8 x i16> %a, %b
138  ret <8 x i16> %v
139
140; CHECK-REG-LABEL: @test9
141; CHECK-REG: xxlor 34, 34, 35
142; CHECK-REG: blr
143
144; CHECK-FISL-LABEL: @test9
145; CHECK-FISL: xxlor 34, 34, 35
146; CHECK-FISL: blr
147
148; CHECK-LE-LABEL: @test9
149; CHECK-LE: xxlor 34, 34, 35
150; CHECK-LE: blr
151}
152
153define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) {
154entry:
155  %v = or <16 x i8> %a, %b
156  ret <16 x i8> %v
157
158; CHECK-REG-LABEL: @test10
159; CHECK-REG: xxlor 34, 34, 35
160; CHECK-REG: blr
161
162; CHECK-FISL-LABEL: @test10
163; CHECK-FISL: xxlor 34, 34, 35
164; CHECK-FISL: blr
165
166; CHECK-LE-LABEL: @test10
167; CHECK-LE: xxlor 34, 34, 35
168; CHECK-LE: blr
169}
170
171define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {
172entry:
173  %v = and <4 x i32> %a, %b
174  ret <4 x i32> %v
175
176; CHECK-REG-LABEL: @test11
177; CHECK-REG: xxland 34, 34, 35
178; CHECK-REG: blr
179
180; CHECK-FISL-LABEL: @test11
181; CHECK-FISL: xxland 34, 34, 35
182; CHECK-FISL: blr
183
184; CHECK-LE-LABEL: @test11
185; CHECK-LE: xxland 34, 34, 35
186; CHECK-LE: blr
187}
188
189define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
190entry:
191  %v = and <8 x i16> %a, %b
192  ret <8 x i16> %v
193
194; CHECK-REG-LABEL: @test12
195; CHECK-REG: xxland 34, 34, 35
196; CHECK-REG: blr
197
198; CHECK-FISL-LABEL: @test12
199; CHECK-FISL: xxland 34, 34, 35
200; CHECK-FISL: blr
201
202; CHECK-LE-LABEL: @test12
203; CHECK-LE: xxland 34, 34, 35
204; CHECK-LE: blr
205}
206
207define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) {
208entry:
209  %v = and <16 x i8> %a, %b
210  ret <16 x i8> %v
211
212; CHECK-REG-LABEL: @test13
213; CHECK-REG: xxland 34, 34, 35
214; CHECK-REG: blr
215
216; CHECK-FISL-LABEL: @test13
217; CHECK-FISL: xxland 34, 34, 35
218; CHECK-FISL: blr
219
220; CHECK-LE-LABEL: @test13
221; CHECK-LE: xxland 34, 34, 35
222; CHECK-LE: blr
223}
224
225define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) {
226entry:
227  %v = or <4 x i32> %a, %b
228  %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1>
229  ret <4 x i32> %w
230
231; CHECK-REG-LABEL: @test14
232; CHECK-REG: xxlnor 34, 34, 35
233; CHECK-REG: blr
234
235; CHECK-FISL-LABEL: @test14
236; CHECK-FISL: xxlor 0, 34, 35
237; CHECK-FISL: xxlnor 34, 34, 35
238; CHECK-FISL: lis 0, -1
239; CHECK-FISL: ori 0, 0, 65520
240; CHECK-FISL: stxvd2x 0, 1, 0
241; CHECK-FISL: blr
242
243; CHECK-LE-LABEL: @test14
244; CHECK-LE: xxlnor 34, 34, 35
245; CHECK-LE: blr
246}
247
248define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
249entry:
250  %v = or <8 x i16> %a, %b
251  %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
252  ret <8 x i16> %w
253
254; CHECK-REG-LABEL: @test15
255; CHECK-REG: xxlnor 34, 34, 35
256; CHECK-REG: blr
257
258; CHECK-FISL-LABEL: @test15
259; CHECK-FISL: xxlor 0, 34, 35
260; CHECK-FISL: xxlor 36, 0, 0
261; CHECK-FISL: xxlnor 0, 34, 35
262; CHECK-FISL: xxlor 34, 0, 0
263; CHECK-FISL: lis 0, -1
264; CHECK-FISL: ori 0, 0, 65520
265; CHECK-FISL: stxvd2x 36, 1, 0
266; CHECK-FISL: blr
267
268; CHECK-LE-LABEL: @test15
269; CHECK-LE: xxlnor 34, 34, 35
270; CHECK-LE: blr
271}
272
273define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) {
274entry:
275  %v = or <16 x i8> %a, %b
276  %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
277  ret <16 x i8> %w
278
279; CHECK-REG-LABEL: @test16
280; CHECK-REG: xxlnor 34, 34, 35
281; CHECK-REG: blr
282
283; CHECK-FISL-LABEL: @test16
284; CHECK-FISL: xxlor 0, 34, 35
285; CHECK-FISL: xxlor 36, 0, 0
286; CHECK-FISL: xxlnor 0, 34, 35
287; CHECK-FISL: xxlor 34, 0, 0
288; CHECK-FISL: lis 0, -1
289; CHECK-FISL: ori 0, 0, 65520
290; CHECK-FISL: stxvd2x 36, 1, 0
291; CHECK-FISL: blr
292
293; CHECK-LE-LABEL: @test16
294; CHECK-LE: xxlnor 34, 34, 35
295; CHECK-LE: blr
296}
297
298define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) {
299entry:
300  %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
301  %v = and <4 x i32> %a, %w
302  ret <4 x i32> %v
303
304; CHECK-REG-LABEL: @test17
305; CHECK-REG: xxlandc 34, 34, 35
306; CHECK-REG: blr
307
308; CHECK-FISL-LABEL: @test17
309; CHECK-FISL: xxlnor 35, 35, 35
310; CHECK-FISL: xxland 34, 34, 35
311; CHECK-FISL: blr
312
313; CHECK-LE-LABEL: @test17
314; CHECK-LE: xxlandc 34, 34, 35
315; CHECK-LE: blr
316}
317
318define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) {
319entry:
320  %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
321  %v = and <8 x i16> %a, %w
322  ret <8 x i16> %v
323
324; CHECK-REG-LABEL: @test18
325; CHECK-REG: xxlandc 34, 34, 35
326; CHECK-REG: blr
327
328; CHECK-FISL-LABEL: @test18
329; CHECK-FISL: xxlnor 0, 35, 35
330; CHECK-FISL: xxlor 36, 0, 0
331; CHECK-FISL: xxlandc 0, 34, 35
332; CHECK-FISL: xxlor 34, 0, 0
333; CHECK-FISL: lis 0, -1
334; CHECK-FISL: ori 0, 0, 65520
335; CHECK-FISL: stxvd2x 36, 1, 0
336; CHECK-FISL: blr
337
338; CHECK-LE-LABEL: @test18
339; CHECK-LE: xxlandc 34, 34, 35
340; CHECK-LE: blr
341}
342
343define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) {
344entry:
345  %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
346  %v = and <16 x i8> %a, %w
347  ret <16 x i8> %v
348
349; CHECK-REG-LABEL: @test19
350; CHECK-REG: xxlandc 34, 34, 35
351; CHECK-REG: blr
352
353; CHECK-FISL-LABEL: @test19
354; CHECK-FISL: xxlnor 0, 35, 35
355; CHECK-FISL: xxlor 36, 0, 0
356; CHECK-FISL: xxlandc 0, 34, 35
357; CHECK-FISL: xxlor 34, 0, 0
358; CHECK-FISL: lis 0, -1
359; CHECK-FISL: ori 0, 0, 65520
360; CHECK-FISL: stxvd2x 36, 1, 0
361; CHECK-FISL: blr
362
363; CHECK-LE-LABEL: @test19
364; CHECK-LE: xxlandc 34, 34, 35
365; CHECK-LE: blr
366}
367
368define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
369entry:
370  %m = icmp eq <4 x i32> %c, %d
371  %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
372  ret <4 x i32> %v
373
374; CHECK-REG-LABEL: @test20
375; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5
376; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
377; CHECK-REG: blr
378
379; CHECK-FISL-LABEL: @test20
380; CHECK-FISL: vcmpequw {{[0-9]+}}, 4, 5
381; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}}
382; CHECK-FISL: blr
383
384; CHECK-LE-LABEL: @test20
385; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5
386; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
387; CHECK-LE: blr
388}
389
390define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
391entry:
392  %m = fcmp oeq <4 x float> %c, %d
393  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
394  ret <4 x float> %v
395
396; CHECK-REG-LABEL: @test21
397; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37
398; CHECK-REG: xxsel 34, 35, 34, [[V1]]
399; CHECK-REG: blr
400
401; CHECK-FISL-LABEL: @test21
402; CHECK-FISL: xvcmpeqsp [[V1:[0-9]+]], 36, 37
403; CHECK-FISL: xxsel 34, 35, 34, [[V1]]
404; CHECK-FISL: blr
405
406; CHECK-LE-LABEL: @test21
407; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37
408; CHECK-LE: xxsel 34, 35, 34, [[V1]]
409; CHECK-LE: blr
410}
411
412define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
413entry:
414  %m = fcmp ueq <4 x float> %c, %d
415  %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
416  ret <4 x float> %v
417
418; CHECK-REG-LABEL: @test22
419; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
420; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
421; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
422; CHECK-REG-DAG: xxlnor
423; CHECK-REG-DAG: xxlnor
424; CHECK-REG-DAG: xxlor
425; CHECK-REG-DAG: xxlor
426; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
427; CHECK-REG: blr
428
429; CHECK-FISL-LABEL: @test22
430; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
431; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
432; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
433; CHECK-FISL-DAG: xxlnor
434; CHECK-FISL-DAG: xxlnor
435; CHECK-FISL-DAG: xxlor
436; CHECK-FISL-DAG: xxlor
437; CHECK-FISL: xxsel 34, 35, 34, {{[0-9]+}}
438; CHECK-FISL: blr
439
440; CHECK-LE-LABEL: @test22
441; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37
442; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36
443; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37
444; CHECK-LE-DAG: xxlnor
445; CHECK-LE-DAG: xxlnor
446; CHECK-LE-DAG: xxlor
447; CHECK-LE-DAG: xxlor
448; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
449; CHECK-LE: blr
450}
451
452define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
453entry:
454  %m = icmp eq <8 x i16> %c, %d
455  %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
456  ret <8 x i16> %v
457
458; CHECK-REG-LABEL: @test23
459; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5
460; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
461; CHECK-REG: blr
462
463; CHECK-FISL-LABEL: @test23
464; CHECK-FISL: vcmpequh 4, 4, 5
465; CHECK-FISL: xxsel 34, 35, 34, 36
466; CHECK-FISL: blr
467
468; CHECK-LE-LABEL: @test23
469; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5
470; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
471; CHECK-LE: blr
472}
473
474define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
475entry:
476  %m = icmp eq <16 x i8> %c, %d
477  %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
478  ret <16 x i8> %v
479
480; CHECK-REG-LABEL: @test24
481; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5
482; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}}
483; CHECK-REG: blr
484
485; CHECK-FISL-LABEL: @test24
486; CHECK-FISL: vcmpequb 4, 4, 5
487; CHECK-FISL: xxsel 34, 35, 34, 36
488; CHECK-FISL: blr
489
490; CHECK-LE-LABEL: @test24
491; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5
492; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}}
493; CHECK-LE: blr
494}
495
496define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
497entry:
498  %m = fcmp oeq <2 x double> %c, %d
499  %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
500  ret <2 x double> %v
501
502; CHECK-LABEL: @test25
503; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37
504; CHECK: xxsel 34, 35, 34, [[V1]]
505; CHECK: blr
506
507; CHECK-LE-LABEL: @test25
508; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37
509; CHECK-LE: xxsel 34, 35, 34, [[V1]]
510; CHECK-LE: blr
511}
512
513define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) {
514  %v = add <2 x i64> %a, %b
515  ret <2 x i64> %v
516
517; CHECK-LABEL: @test26
518
519; Make sure we use only two stores (one for each operand).
520; CHECK: stxvd2x 35,
521; CHECK: stxvd2x 34,
522; CHECK-NOT: stxvd2x
523
524; FIXME: The code quality here is not good; just make sure we do something for now.
525; CHECK: add
526; CHECK: add
527; CHECK: blr
528
529; CHECK-LE: vaddudm 2, 2, 3
530; CHECK-LE: blr
531}
532
533define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) {
534  %v = and <2 x i64> %a, %b
535  ret <2 x i64> %v
536
537; CHECK-LABEL: @test27
538; CHECK: xxland 34, 34, 35
539; CHECK: blr
540
541; CHECK-LE-LABEL: @test27
542; CHECK-LE: xxland 34, 34, 35
543; CHECK-LE: blr
544}
545
546define <2 x double> @test28(<2 x double>* %a) {
547  %v = load <2 x double>, <2 x double>* %a, align 16
548  ret <2 x double> %v
549
550; CHECK-LABEL: @test28
551; CHECK: lxvd2x 34, 0, 3
552; CHECK: blr
553
554; CHECK-LE-LABEL: @test28
555; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
556; CHECK-LE: xxswapd 34, [[V1]]
557; CHECK-LE: blr
558}
559
560define void @test29(<2 x double>* %a, <2 x double> %b) {
561  store <2 x double> %b, <2 x double>* %a, align 16
562  ret void
563
564; CHECK-LABEL: @test29
565; CHECK: stxvd2x 34, 0, 3
566; CHECK: blr
567
568; CHECK-LE-LABEL: @test29
569; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
570; CHECK-LE: stxvd2x [[V1]], 0, 3
571; CHECK-LE: blr
572}
573
574define <2 x double> @test28u(<2 x double>* %a) {
575  %v = load <2 x double>, <2 x double>* %a, align 8
576  ret <2 x double> %v
577
578; CHECK-LABEL: @test28u
579; CHECK: lxvd2x 34, 0, 3
580; CHECK: blr
581
582; CHECK-LE-LABEL: @test28u
583; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
584; CHECK-LE: xxswapd 34, [[V1]]
585; CHECK-LE: blr
586}
587
588define void @test29u(<2 x double>* %a, <2 x double> %b) {
589  store <2 x double> %b, <2 x double>* %a, align 8
590  ret void
591
592; CHECK-LABEL: @test29u
593; CHECK: stxvd2x 34, 0, 3
594; CHECK: blr
595
596; CHECK-LE-LABEL: @test29u
597; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
598; CHECK-LE: stxvd2x [[V1]], 0, 3
599; CHECK-LE: blr
600}
601
602define <2 x i64> @test30(<2 x i64>* %a) {
603  %v = load <2 x i64>, <2 x i64>* %a, align 16
604  ret <2 x i64> %v
605
606; CHECK-REG-LABEL: @test30
607; CHECK-REG: lxvd2x 34, 0, 3
608; CHECK-REG: blr
609
610; CHECK-FISL-LABEL: @test30
611; CHECK-FISL: lxvd2x 0, 0, 3
612; CHECK-FISL: xxlor 34, 0, 0
613; CHECK-FISL: blr
614
615; CHECK-LE-LABEL: @test30
616; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
617; CHECK-LE: xxswapd 34, [[V1]]
618; CHECK-LE: blr
619}
620
621define void @test31(<2 x i64>* %a, <2 x i64> %b) {
622  store <2 x i64> %b, <2 x i64>* %a, align 16
623  ret void
624
625; CHECK-LABEL: @test31
626; CHECK: stxvd2x 34, 0, 3
627; CHECK: blr
628
629; CHECK-LE-LABEL: @test31
630; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
631; CHECK-LE: stxvd2x [[V1]], 0, 3
632; CHECK-LE: blr
633}
634
635define <4 x float> @test32(<4 x float>* %a) {
636  %v = load <4 x float>, <4 x float>* %a, align 16
637  ret <4 x float> %v
638
639; CHECK-REG-LABEL: @test32
640; CHECK-REG: lxvw4x 34, 0, 3
641; CHECK-REG: blr
642
643; CHECK-FISL-LABEL: @test32
644; CHECK-FISL: lxvw4x 34, 0, 3
645; CHECK-FISL: blr
646
647; CHECK-LE-LABEL: @test32
648; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
649; CHECK-LE: xxswapd 34, [[V1]]
650; CHECK-LE: blr
651}
652
653define void @test33(<4 x float>* %a, <4 x float> %b) {
654  store <4 x float> %b, <4 x float>* %a, align 16
655  ret void
656
657; CHECK-REG-LABEL: @test33
658; CHECK-REG: stxvw4x 34, 0, 3
659; CHECK-REG: blr
660
661; CHECK-FISL-LABEL: @test33
662; CHECK-FISL: stxvw4x 34, 0, 3
663; CHECK-FISL: blr
664
665; CHECK-LE-LABEL: @test33
666; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
667; CHECK-LE: stxvd2x [[V1]], 0, 3
668; CHECK-LE: blr
669}
670
671define <4 x float> @test32u(<4 x float>* %a) {
672  %v = load <4 x float>, <4 x float>* %a, align 8
673  ret <4 x float> %v
674
675; CHECK-LABEL: @test32u
676; CHECK-DAG: lvsl
677; CHECK-DAG: lvx
678; CHECK-DAG: lvx
679; CHECK: vperm 2,
680; CHECK: blr
681
682; CHECK-LE-LABEL: @test32u
683; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
684; CHECK-LE: xxswapd 34, [[V1]]
685; CHECK-LE: blr
686}
687
688define void @test33u(<4 x float>* %a, <4 x float> %b) {
689  store <4 x float> %b, <4 x float>* %a, align 8
690  ret void
691
692; CHECK-REG-LABEL: @test33u
693; CHECK-REG: stxvw4x 34, 0, 3
694; CHECK-REG: blr
695
696; CHECK-FISL-LABEL: @test33u
697; CHECK-FISL: stxvw4x 34, 0, 3
698; CHECK-FISL: blr
699
700; CHECK-LE-LABEL: @test33u
701; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
702; CHECK-LE: stxvd2x [[V1]], 0, 3
703; CHECK-LE: blr
704}
705
706define <4 x i32> @test34(<4 x i32>* %a) {
707  %v = load <4 x i32>, <4 x i32>* %a, align 16
708  ret <4 x i32> %v
709
710; CHECK-REG-LABEL: @test34
711; CHECK-REG: lxvw4x 34, 0, 3
712; CHECK-REG: blr
713
714; CHECK-FISL-LABEL: @test34
715; CHECK-FISL: lxvw4x 34, 0, 3
716; CHECK-FISL: blr
717
718; CHECK-LE-LABEL: @test34
719; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3
720; CHECK-LE: xxswapd 34, [[V1]]
721; CHECK-LE: blr
722}
723
724define void @test35(<4 x i32>* %a, <4 x i32> %b) {
725  store <4 x i32> %b, <4 x i32>* %a, align 16
726  ret void
727
728; CHECK-REG-LABEL: @test35
729; CHECK-REG: stxvw4x 34, 0, 3
730; CHECK-REG: blr
731
732; CHECK-FISL-LABEL: @test35
733; CHECK-FISL: stxvw4x 34, 0, 3
734; CHECK-FISL: blr
735
736; CHECK-LE-LABEL: @test35
737; CHECK-LE: xxswapd [[V1:[0-9]+]], 34
738; CHECK-LE: stxvd2x [[V1]], 0, 3
739; CHECK-LE: blr
740}
741
742define <2 x double> @test40(<2 x i64> %a) {
743  %v = uitofp <2 x i64> %a to <2 x double>
744  ret <2 x double> %v
745
746; CHECK-LABEL: @test40
747; CHECK: xvcvuxddp 34, 34
748; CHECK: blr
749
750; CHECK-LE-LABEL: @test40
751; CHECK-LE: xvcvuxddp 34, 34
752; CHECK-LE: blr
753}
754
755define <2 x double> @test41(<2 x i64> %a) {
756  %v = sitofp <2 x i64> %a to <2 x double>
757  ret <2 x double> %v
758
759; CHECK-LABEL: @test41
760; CHECK: xvcvsxddp 34, 34
761; CHECK: blr
762
763; CHECK-LE-LABEL: @test41
764; CHECK-LE: xvcvsxddp 34, 34
765; CHECK-LE: blr
766}
767
768define <2 x i64> @test42(<2 x double> %a) {
769  %v = fptoui <2 x double> %a to <2 x i64>
770  ret <2 x i64> %v
771
772; CHECK-LABEL: @test42
773; CHECK: xvcvdpuxds 34, 34
774; CHECK: blr
775
776; CHECK-LE-LABEL: @test42
777; CHECK-LE: xvcvdpuxds 34, 34
778; CHECK-LE: blr
779}
780
781define <2 x i64> @test43(<2 x double> %a) {
782  %v = fptosi <2 x double> %a to <2 x i64>
783  ret <2 x i64> %v
784
785; CHECK-LABEL: @test43
786; CHECK: xvcvdpsxds 34, 34
787; CHECK: blr
788
789; CHECK-LE-LABEL: @test43
790; CHECK-LE: xvcvdpsxds 34, 34
791; CHECK-LE: blr
792}
793
794define <2 x float> @test44(<2 x i64> %a) {
795  %v = uitofp <2 x i64> %a to <2 x float>
796  ret <2 x float> %v
797
798; CHECK-LABEL: @test44
799; FIXME: The code quality here looks pretty bad.
800; CHECK: blr
801}
802
803define <2 x float> @test45(<2 x i64> %a) {
804  %v = sitofp <2 x i64> %a to <2 x float>
805  ret <2 x float> %v
806
807; CHECK-LABEL: @test45
808; FIXME: The code quality here looks pretty bad.
809; CHECK: blr
810}
811
812define <2 x i64> @test46(<2 x float> %a) {
813  %v = fptoui <2 x float> %a to <2 x i64>
814  ret <2 x i64> %v
815
816; CHECK-LABEL: @test46
817; FIXME: The code quality here looks pretty bad.
818; CHECK: blr
819}
820
821define <2 x i64> @test47(<2 x float> %a) {
822  %v = fptosi <2 x float> %a to <2 x i64>
823  ret <2 x i64> %v
824
825; CHECK-LABEL: @test47
826; FIXME: The code quality here looks pretty bad.
827; CHECK: blr
828}
829
830define <2 x double> @test50(double* %a) {
831  %v = load double, double* %a, align 8
832  %w = insertelement <2 x double> undef, double %v, i32 0
833  %x = insertelement <2 x double> %w, double %v, i32 1
834  ret <2 x double> %x
835
836; CHECK-LABEL: @test50
837; CHECK: lxvdsx 34, 0, 3
838; CHECK: blr
839
840; CHECK-LE-LABEL: @test50
841; CHECK-LE: lxvdsx 34, 0, 3
842; CHECK-LE: blr
843}
844
845define <2 x double> @test51(<2 x double> %a, <2 x double> %b) {
846  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0>
847  ret <2 x double> %v
848
849; CHECK-LABEL: @test51
850; CHECK: xxspltd 34, 34, 0
851; CHECK: blr
852
853; CHECK-LE-LABEL: @test51
854; CHECK-LE: xxspltd 34, 34, 1
855; CHECK-LE: blr
856}
857
858define <2 x double> @test52(<2 x double> %a, <2 x double> %b) {
859  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2>
860  ret <2 x double> %v
861
862; CHECK-LABEL: @test52
863; CHECK: xxmrghd 34, 34, 35
864; CHECK: blr
865
866; CHECK-LE-LABEL: @test52
867; CHECK-LE: xxmrgld 34, 35, 34
868; CHECK-LE: blr
869}
870
871define <2 x double> @test53(<2 x double> %a, <2 x double> %b) {
872  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0>
873  ret <2 x double> %v
874
875; CHECK-LABEL: @test53
876; CHECK: xxmrghd 34, 35, 34
877; CHECK: blr
878
879; CHECK-LE-LABEL: @test53
880; CHECK-LE: xxmrgld 34, 34, 35
881; CHECK-LE: blr
882}
883
884define <2 x double> @test54(<2 x double> %a, <2 x double> %b) {
885  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
886  ret <2 x double> %v
887
888; CHECK-LABEL: @test54
889; CHECK: xxpermdi 34, 34, 35, 2
890; CHECK: blr
891
892; CHECK-LE-LABEL: @test54
893; CHECK-LE: xxpermdi 34, 35, 34, 2
894; CHECK-LE: blr
895}
896
897define <2 x double> @test55(<2 x double> %a, <2 x double> %b) {
898  %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3>
899  ret <2 x double> %v
900
901; CHECK-LABEL: @test55
902; CHECK: xxmrgld 34, 34, 35
903; CHECK: blr
904
905; CHECK-LE-LABEL: @test55
906; CHECK-LE: xxmrghd 34, 35, 34
907; CHECK-LE: blr
908}
909
910define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) {
911  %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3>
912  ret <2 x i64> %v
913
914; CHECK-LABEL: @test56
915; CHECK: xxmrgld 34, 34, 35
916; CHECK: blr
917
918; CHECK-LE-LABEL: @test56
919; CHECK-LE: xxmrghd 34, 35, 34
920; CHECK-LE: blr
921}
922
923define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) {
924  %v = shl <2 x i64> %a, %b
925  ret <2 x i64> %v
926
927; CHECK-LABEL: @test60
928; This should scalarize, and the current code quality is not good.
929; CHECK: stxvd2x
930; CHECK: stxvd2x
931; CHECK: sld
932; CHECK: sld
933; CHECK: lxvd2x
934; CHECK: blr
935}
936
937define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) {
938  %v = lshr <2 x i64> %a, %b
939  ret <2 x i64> %v
940
941; CHECK-LABEL: @test61
942; This should scalarize, and the current code quality is not good.
943; CHECK: stxvd2x
944; CHECK: stxvd2x
945; CHECK: srd
946; CHECK: srd
947; CHECK: lxvd2x
948; CHECK: blr
949}
950
951define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
952  %v = ashr <2 x i64> %a, %b
953  ret <2 x i64> %v
954
955; CHECK-LABEL: @test62
956; This should scalarize, and the current code quality is not good.
957; CHECK: stxvd2x
958; CHECK: stxvd2x
959; CHECK: srad
960; CHECK: srad
961; CHECK: lxvd2x
962; CHECK: blr
963}
964
965define double @test63(<2 x double> %a) {
966  %v = extractelement <2 x double> %a, i32 0
967  ret double %v
968
969; CHECK-REG-LABEL: @test63
970; CHECK-REG: xxlor 1, 34, 34
971; CHECK-REG: blr
972
973; CHECK-FISL-LABEL: @test63
974; CHECK-FISL: xxlor 0, 34, 34
975; CHECK-FISL: fmr 1, 0
976; CHECK-FISL: blr
977
978; CHECK-LE-LABEL: @test63
979; CHECK-LE: xxswapd 1, 34
980; CHECK-LE: blr
981}
982
983define double @test64(<2 x double> %a) {
984  %v = extractelement <2 x double> %a, i32 1
985  ret double %v
986
987; CHECK-REG-LABEL: @test64
988; CHECK-REG: xxswapd 1, 34
989; CHECK-REG: blr
990
991; CHECK-FISL-LABEL: @test64
992; CHECK-FISL: xxswapd  34, 34
993; CHECK-FISL: xxlor 0, 34, 34
994; CHECK-FISL: fmr 1, 0
995; CHECK-FISL: blr
996
997; CHECK-LE-LABEL: @test64
998; CHECK-LE: xxlor 1, 34, 34
999}
1000
1001define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) {
1002  %w = icmp eq <2 x i64> %a, %b
1003  ret <2 x i1> %w
1004
1005; CHECK-REG-LABEL: @test65
1006; CHECK-REG: vcmpequw 2, 2, 3
1007; CHECK-REG: blr
1008
1009; CHECK-FISL-LABEL: @test65
1010; CHECK-FISL: vcmpequw 2, 2, 3
1011; CHECK-FISL: blr
1012
1013; CHECK-LE-LABEL: @test65
1014; CHECK-LE: vcmpequd 2, 2, 3
1015; CHECK-LE: blr
1016}
1017
1018define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) {
1019  %w = icmp ne <2 x i64> %a, %b
1020  ret <2 x i1> %w
1021
1022; CHECK-REG-LABEL: @test66
1023; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3
1024; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1025; CHECK-REG: blr
1026
1027; CHECK-FISL-LABEL: @test66
1028; CHECK-FISL: vcmpequw 2, 2, 3
1029; CHECK-FISL: xxlnor 34, 34, 34
1030; CHECK-FISL: blr
1031
1032; CHECK-LE-LABEL: @test66
1033; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3
1034; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}}
1035; CHECK-LE: blr
1036}
1037
1038define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
1039  %w = icmp ult <2 x i64> %a, %b
1040  ret <2 x i1> %w
1041
1042; CHECK-LABEL: @test67
1043; This should scalarize, and the current code quality is not good.
1044; CHECK: stxvd2x
1045; CHECK: stxvd2x
1046; CHECK: cmpld
1047; CHECK: cmpld
1048; CHECK: lxvd2x
1049; CHECK: blr
1050
1051; CHECK-LE-LABEL: @test67
1052; CHECK-LE: vcmpgtud 2, 3, 2
1053; CHECK-LE: blr
1054}
1055
1056define <2 x double> @test68(<2 x i32> %a) {
1057  %w = sitofp <2 x i32> %a to <2 x double>
1058  ret <2 x double> %w
1059
1060; CHECK-LABEL: @test68
1061; CHECK: xxmrghw [[V1:[0-9]+]]
1062; CHECK: xvcvsxwdp 34, [[V1]]
1063; CHECK: blr
1064
1065; CHECK-LE-LABEL: @test68
1066; CHECK-LE: xxmrglw [[V1:[0-9]+]], 34, 34
1067; CHECK-LE: xvcvsxwdp 34, [[V1]]
1068; CHECK-LE: blr
1069}
1070
1071; This gets scalarized so the code isn't great
1072define <2 x double> @test69(<2 x i16> %a) {
1073  %w = sitofp <2 x i16> %a to <2 x double>
1074  ret <2 x double> %w
1075
1076; CHECK-LABEL: @test69
1077; CHECK-DAG: lfiwax
1078; CHECK-DAG: lfiwax
1079; CHECK-DAG: xscvsxddp
1080; CHECK-DAG: xscvsxddp
1081; CHECK: xxmrghd
1082; CHECK: blr
1083
1084; CHECK-LE-LABEL: @test69
1085; CHECK-LE: mfvsrd
1086; CHECK-LE: mtvsrwa
1087; CHECK-LE: mtvsrwa
1088; CHECK-LE: xscvsxddp
1089; CHECK-LE: xscvsxddp
1090; CHECK-LE: xxmrghd
1091; CHECK-LE: blr
1092}
1093
1094; This gets scalarized so the code isn't great
1095define <2 x double> @test70(<2 x i8> %a) {
1096  %w = sitofp <2 x i8> %a to <2 x double>
1097  ret <2 x double> %w
1098
1099; CHECK-LABEL: @test70
1100; CHECK-DAG: lfiwax
1101; CHECK-DAG: lfiwax
1102; CHECK-DAG: xscvsxddp
1103; CHECK-DAG: xscvsxddp
1104; CHECK: xxmrghd
1105; CHECK: blr
1106
1107; CHECK-LE-LABEL: @test70
1108; CHECK-LE: mfvsrd
1109; CHECK-LE: mtvsrwa
1110; CHECK-LE: mtvsrwa
1111; CHECK-LE: xscvsxddp
1112; CHECK-LE: xscvsxddp
1113; CHECK-LE: xxmrghd
1114; CHECK-LE: blr
1115}
1116
1117; This gets scalarized so the code isn't great
1118define <2 x i32> @test80(i32 %v) {
1119  %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
1120  %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer
1121  %i = add <2 x i32> %b2, <i32 2, i32 3>
1122  ret <2 x i32> %i
1123
1124; CHECK-REG-LABEL: @test80
1125; CHECK-REG: stw 3, -16(1)
1126; CHECK-REG: addi [[R1:[0-9]+]], 1, -16
1127; CHECK-REG: addis [[R2:[0-9]+]]
1128; CHECK-REG: addi [[R2]], [[R2]]
1129; CHECK-REG-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1130; CHECK-REG-DAG: lxvw4x 35, 0, [[R2]]
1131; CHECK-REG: xxspltw 34, [[VS1]], 0
1132; CHECK-REG: vadduwm 2, 2, 3
1133; CHECK-REG-NOT: stxvw4x
1134; CHECK-REG: blr
1135
1136; CHECK-FISL-LABEL: @test80
1137; CHECK-FISL: mr 4, 3
1138; CHECK-FISL: stw 4, -16(1)
1139; CHECK-FISL: addi [[R1:[0-9]+]], 1, -16
1140; CHECK-FISL-DAG: lxvw4x [[VS1:[0-9]+]], 0, [[R1]]
1141; CHECK-FISL-DAG: xxspltw {{[0-9]+}}, [[VS1]], 0
1142; CHECK-FISL: addis [[R2:[0-9]+]]
1143; CHECK-FISL: addi [[R2]], [[R2]]
1144; CHECK-FISL-DAG: lxvw4x {{[0-9]+}}, 0, [[R2]]
1145; CHECK-FISL: vadduwm
1146; CHECK-FISL-NOT: stxvw4x
1147; CHECK-FISL: blr
1148
1149; CHECK-LE-LABEL: @test80
1150; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3
1151; CHECK-LE-DAG: xxswapd  [[V1:[0-9]+]], [[R1]]
1152; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI
1153; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]]
1154; CHECK-LE-DAG: xxspltw 34, [[V1]]
1155; CHECK-LE-DAG: xxswapd 35, [[V2]]
1156; CHECK-LE: vadduwm 2, 2, 3
1157; CHECK-LE: blr
1158}
1159
1160define <2 x double> @test81(<4 x float> %b) {
1161  %w = bitcast <4 x float> %b to <2 x double>
1162  ret <2 x double> %w
1163
1164; CHECK-LABEL: @test81
1165; CHECK: blr
1166
1167; CHECK-LE-LABEL: @test81
1168; CHECK-LE: blr
1169}
1170
1171define double @test82(double %a, double %b, double %c, double %d) {
1172entry:
1173  %m = fcmp oeq double %c, %d
1174  %v = select i1 %m, double %a, double %b
1175  ret double %v
1176
1177; CHECK-REG-LABEL: @test82
1178; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4
1179; CHECK-REG: beqlr [[REG]]
1180
1181; CHECK-FISL-LABEL: @test82
1182; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4
1183; CHECK-FISL: beq [[REG]], {{.*}}
1184
1185; CHECK-LE-LABEL: @test82
1186; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4
1187; CHECK-LE: beqlr [[REG]]
1188}
1189
1190; Function Attrs: nounwind readnone
1191define <4 x i32> @test83(i8* %a) {
1192  entry:
1193    %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8* %a)
1194      ret <4 x i32> %0
1195      ; CHECK-LABEL: test83
1196      ; CHECK: lxvw4x 34, 0, 3
1197      ; CHECK: blr
1198}
1199; Function Attrs: nounwind readnone
1200declare <4 x i32> @llvm.ppc.vsx.lxvw4x.be(i8*)
1201
1202; Function Attrs: nounwind readnone
1203define <2 x double> @test84(i8* %a) {
1204  entry:
1205    %0 = tail call <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8* %a)
1206      ret <2 x double> %0
1207      ; CHECK-LABEL: test84
1208      ; CHECK: lxvd2x 34, 0, 3
1209      ; CHECK: blr
1210}
1211; Function Attrs: nounwind readnone
1212declare <2 x double> @llvm.ppc.vsx.lxvd2x.be(i8*)
1213
1214; Function Attrs: nounwind readnone
1215define void @test85(<4 x i32> %a, i8* %b) {
1216  entry:
1217    tail call void @llvm.ppc.vsx.stxvw4x.be(<4 x i32> %a, i8* %b)
1218    ret void
1219      ; CHECK-LABEL: test85
1220      ; CHECK: stxvw4x 34, 0, 5
1221      ; CHECK: blr
1222}
1223; Function Attrs: nounwind readnone
1224declare void @llvm.ppc.vsx.stxvw4x.be(<4 x i32>, i8*)
1225
1226; Function Attrs: nounwind readnone
1227define void @test86(<2 x double> %a, i8* %b) {
1228  entry:
1229    tail call void @llvm.ppc.vsx.stxvd2x.be(<2 x double> %a, i8* %b)
1230    ret void
1231      ; CHECK-LABEL: test86
1232      ; CHECK: stxvd2x 34, 0, 5
1233      ; CHECK: blr
1234}
1235; Function Attrs: nounwind readnone
1236declare void @llvm.ppc.vsx.stxvd2x.be(<2 x double>, i8*)
1237