1; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx < %s | FileCheck \
3; RUN:   -check-prefix=CHECK-REG %s
4; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
5; RUN:   FileCheck %s
6; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | \
7; RUN:   FileCheck -check-prefix=CHECK-FISL %s
8; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck \
9; RUN:   -check-prefix=CHECK-P9-REG %s
10; RUN: llc -verify-machineinstrs -mcpu=pwr9 -fast-isel -O0 < %s | FileCheck \
11; RUN:   -check-prefix=CHECK-P9-FISL %s
12target datalayout = "E-m:e-i64:64-n32:64"
13target triple = "powerpc64-unknown-linux-gnu"
14
15define double @foo1(double %a) nounwind {
16entry:
17  call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
18  br label %return
19
20; CHECK-REG: @foo1
21; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1
22; CHECK-REG: xxlor 1, [[R1]], [[R1]]
23; CHECK-REG: blr
24
25; CHECK-FISL: @foo1
26; CHECK-FISL: lis 0, -1
27; CHECK-FISL: ori 0, 0, 65384
28; CHECK-FISL: stxsdx 1, 1, 0
29; CHECK-FISL: blr
30
31; CHECK-P9-REG: @foo1
32; CHECK-P9-REG: xxlor [[R1:[0-9]+]], 1, 1
33; CHECK-P9-REG: xxlor 1, [[R1]], [[R1]]
34; CHECK-P9-REG: blr
35
36; CHECK-P9-FISL: @foo1
37; CHECK-P9-FISL: stfd 31, -8(1)
38; CHECK-P9-FISL: blr
39
40return:                                           ; preds = %entry
41  ret double %a
42}
43
44define double @foo2(double %a) nounwind {
45entry:
46  %b = fadd double %a, %a
47  call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind
48  br label %return
49
50; CHECK-REG: @foo2
51; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
52; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
53; CHECK-REG: blr
54
55; CHECK-FISL: @foo2
56; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1
57; CHECK-FISL: stxsdx [[R1]], [[R1]], 0
58; CHECK-FISL: lxsdx [[R1]], [[R1]], 0
59; CHECK-FISL: blr
60
61; CHECK-P9-REG: @foo2
62; CHECK-P9-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1
63; CHECK-P9-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]]
64; CHECK-P9-REG: blr
65
66; CHECK-P9-FISL: @foo2
67; CHECK-P9-FISL: xsadddp [[R1:[0-9]+]], 1, 1
68; CHECK-P9-FISL: stfd [[R1]], [[OFF:[0-9\-]+]](1)
69; CHECK-P9-FISL: lfd [[R1]], [[OFF]](1)
70; CHECK-P9-FISL: blr
71
72return:                                           ; preds = %entry
73  ret double %b
74}
75
76define double @foo3(double %a) nounwind {
77entry:
78  call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"() nounwind
79  br label %return
80
81; CHECK: @foo3
82; CHECK: stxsdx 1,
83; CHECK: lxsdx [[R1:[0-9]+]],
84; CHECK: xsadddp 1, [[R1]], [[R1]]
85; CHECK: blr
86
87; CHECK-P9-REG-LABEL: foo3
88; CHECK-P9-REG: stfd 1, [[OFF:[0-9\-]+]](1)
89; CHECK-P9-REG: lfd [[FPR:[0-9]+]], [[OFF]](1)
90; CHECK-P9-REG: xsadddp 1, [[FPR]], [[FPR]]
91
92; CHECK-P9-FISL-LABEL: foo3
93; CHECK-P9-FISL: stfd 1, [[OFF:[0-9\-]+]](1)
94; CHECK-P9-FISL: lfd [[FPR:[0-9]+]], [[OFF]](1)
95; CHECK-P9-FISL: xsadddp 1, [[FPR]], [[FPR]]
96return:                                           ; preds = %entry
97  %b = fadd double %a, %a
98  ret double %b
99}
100
101