1; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=-vsx | FileCheck %s
2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s
3; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=-vsx | FileCheck %s -check-prefix=CHECK-LE
4; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
5; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
6; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -march=ppc64 -mattr=+altivec -mattr=+vsx | FileCheck %s -check-prefix=CHECK-LE-VSX
7
8define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
9	%tmp = load <4 x i32>* %X		; <<4 x i32>> [#uses=1]
10	%tmp2 = load <4 x i32>* %Y		; <<4 x i32>> [#uses=1]
11	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
12	ret <4 x i32> %tmp3
13}
14; CHECK-LABEL: test_v4i32:
15; CHECK: vmsumuhm
16; CHECK-NOT: mullw
17; CHECK-LE-LABEL: test_v4i32:
18; CHECK-LE: vmsumuhm
19; CHECK-LE-NOT: mullw
20; CHECK-VSX-LABEL: test_v4i32:
21; CHECK-VSX: vmsumuhm
22; CHECK-VSX-NOT: mullw
23; CHECK-LE-VSX-LABEL: test_v4i32:
24; CHECK-LE-VSX: vmsumuhm
25; CHECK-LE-VSX-NOT: mullw
26
27define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
28	%tmp = load <8 x i16>* %X		; <<8 x i16>> [#uses=1]
29	%tmp2 = load <8 x i16>* %Y		; <<8 x i16>> [#uses=1]
30	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
31	ret <8 x i16> %tmp3
32}
33; CHECK-LABEL: test_v8i16:
34; CHECK: vmladduhm
35; CHECK-NOT: mullw
36; CHECK-LE-LABEL: test_v8i16:
37; CHECK-LE: vmladduhm
38; CHECK-LE-NOT: mullw
39; CHECK-VSX-LABEL: test_v8i16:
40; CHECK-VSX: vmladduhm
41; CHECK-VSX-NOT: mullw
42; CHECK-LE-VSX-LABEL: test_v8i16:
43; CHECK-LE-VSX: vmladduhm
44; CHECK-LE-VSX-NOT: mullw
45
46define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
47	%tmp = load <16 x i8>* %X		; <<16 x i8>> [#uses=1]
48	%tmp2 = load <16 x i8>* %Y		; <<16 x i8>> [#uses=1]
49	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
50	ret <16 x i8> %tmp3
51}
52; CHECK-LABEL: test_v16i8:
53; CHECK: vmuloub
54; CHECK: vmuleub
55; CHECK-NOT: mullw
56; CHECK-LE-LABEL: test_v16i8:
57; CHECK-LE: vmuloub [[REG1:[0-9]+]]
58; CHECK-LE: vmuleub [[REG2:[0-9]+]]
59; CHECK-LE: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
60; CHECK-LE-NOT: mullw
61; CHECK-VSX-LABEL: test_v16i8:
62; CHECK-VSX: vmuloub
63; CHECK-VSX: vmuleub
64; CHECK-VSX-NOT: mullw
65; CHECK-LE-VSX-LABEL: test_v16i8:
66; CHECK-LE-VSX: vmuloub [[REG1:[0-9]+]]
67; CHECK-LE-VSX: vmuleub [[REG2:[0-9]+]]
68; CHECK-LE-VSX: vperm {{[0-9]+}}, [[REG2]], [[REG1]]
69; CHECK-LE-VSX-NOT: mullw
70
71define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
72	%tmp = load <4 x float>* %X
73	%tmp2 = load <4 x float>* %Y
74	%tmp3 = fmul <4 x float> %tmp, %tmp2
75	ret <4 x float> %tmp3
76}
77; Check the creation of a negative zero float vector by creating a vector of
78; all bits set and shifting it 31 bits to left, resulting a an vector of
79; 4 x 0x80000000 (-0.0 as float).
80; CHECK-LABEL: test_float:
81; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
82; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
83; CHECK: vmaddfp
84; CHECK-LE-LABEL: test_float:
85; CHECK-LE: vspltisw [[ZNEG:[0-9]+]], -1
86; CHECK-LE: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
87; CHECK-LE: vmaddfp
88; CHECK-VSX-LABEL: test_float:
89; CHECK-VSX: xvmulsp
90; CHECK-LE-VSX-LABEL: test_float:
91; CHECK-LE-VSX: xvmulsp
92