1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
4
5define <4 x i32> @vextsb2wLE(<16 x i8> %a) {
6; CHECK-LE-LABEL: vextsb2wLE:
7; CHECK-LE:       # %bb.0: # %entry
8; CHECK-LE-NEXT:    vextsb2w 2, 2
9; CHECK-LE-NEXT:    blr
10; CHECK-BE-LABEL: vextsb2wLE:
11; CHECK-BE:       # %bb.0: # %entry
12; CHECK-BE:         vperm 2, 2, 2, 3
13; CHECK-BE-NEXT:    vextsb2w 2, 2
14; CHECK-BE-NEXT:    blr
15
16entry:
17  %vecext = extractelement <16 x i8> %a, i32 0
18  %conv = sext i8 %vecext to i32
19  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
20  %vecext1 = extractelement <16 x i8> %a, i32 4
21  %conv2 = sext i8 %vecext1 to i32
22  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
23  %vecext4 = extractelement <16 x i8> %a, i32 8
24  %conv5 = sext i8 %vecext4 to i32
25  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
26  %vecext7 = extractelement <16 x i8> %a, i32 12
27  %conv8 = sext i8 %vecext7 to i32
28  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
29  ret <4 x i32> %vecinit9
30}
31
32define <2 x i64> @vextsb2dLE(<16 x i8> %a) {
33; CHECK-LE-LABEL: vextsb2dLE:
34; CHECK-LE:       # %bb.0: # %entry
35; CHECK-LE-NEXT:    vextsb2d 2, 2
36; CHECK-LE-NEXT:    blr
37; CHECK-BE-LABEL: vextsb2dLE:
38; CHECK-BE:       # %bb.0: # %entry
39; CHECK-BE:         vperm 2, 2, 2, 3
40; CHECK-BE-NEXT:    vextsb2d 2, 2
41; CHECK-BE-NEXT:    blr
42
43entry:
44  %vecext = extractelement <16 x i8> %a, i32 0
45  %conv = sext i8 %vecext to i64
46  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
47  %vecext1 = extractelement <16 x i8> %a, i32 8
48  %conv2 = sext i8 %vecext1 to i64
49  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
50  ret <2 x i64> %vecinit3
51}
52
53define <4 x i32> @vextsh2wLE(<8 x i16> %a) {
54; CHECK-LE-LABEL: vextsh2wLE:
55; CHECK-LE:       # %bb.0: # %entry
56; CHECK-LE-NEXT:    vextsh2w 2, 2
57; CHECK-LE-NEXT:    blr
58; CHECK-BE-LABEL: vextsh2wLE:
59; CHECK-BE:       # %bb.0: # %entry
60; CHECK-BE:         vperm 2, 2, 2, 3
61; CHECK-BE-NEXT:    vextsh2w 2, 2
62; CHECK-BE-NEXT:    blr
63
64entry:
65  %vecext = extractelement <8 x i16> %a, i32 0
66  %conv = sext i16 %vecext to i32
67  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
68  %vecext1 = extractelement <8 x i16> %a, i32 2
69  %conv2 = sext i16 %vecext1 to i32
70  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
71  %vecext4 = extractelement <8 x i16> %a, i32 4
72  %conv5 = sext i16 %vecext4 to i32
73  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
74  %vecext7 = extractelement <8 x i16> %a, i32 6
75  %conv8 = sext i16 %vecext7 to i32
76  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
77  ret <4 x i32> %vecinit9
78}
79
80define <2 x i64> @vextsh2dLE(<8 x i16> %a) {
81; CHECK-LE-LABEL: vextsh2dLE:
82; CHECK-LE:       # %bb.0: # %entry
83; CHECK-LE-NEXT:    vextsh2d 2, 2
84; CHECK-LE-NEXT:    blr
85; CHECK-BE-LABEL: vextsh2dLE:
86; CHECK-BE:       # %bb.0: # %entry
87; CHECK-BE:         vperm 2, 2, 2, 3
88; CHECK-BE-NEXT:    vextsh2d 2, 2
89; CHECK-BE-NEXT:    blr
90
91entry:
92  %vecext = extractelement <8 x i16> %a, i32 0
93  %conv = sext i16 %vecext to i64
94  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
95  %vecext1 = extractelement <8 x i16> %a, i32 4
96  %conv2 = sext i16 %vecext1 to i64
97  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
98  ret <2 x i64> %vecinit3
99}
100
101define <2 x i64> @vextsw2dLE(<4 x i32> %a) {
102; CHECK-LE-LABEL: vextsw2dLE:
103; CHECK-LE:       # %bb.0: # %entry
104; CHECK-LE-NEXT:    vextsw2d 2, 2
105; CHECK-LE-NEXT:    blr
106; CHECK-BE-LABEL: vextsw2dLE:
107; CHECK-BE:       # %bb.0: # %entry
108; CHECK-BE:         vmrgew
109; CHECK-BE-NEXT:    vextsw2d 2, 2
110; CHECK-BE-NEXT:    blr
111
112entry:
113  %vecext = extractelement <4 x i32> %a, i32 0
114  %conv = sext i32 %vecext to i64
115  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
116  %vecext1 = extractelement <4 x i32> %a, i32 2
117  %conv2 = sext i32 %vecext1 to i64
118  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
119  ret <2 x i64> %vecinit3
120}
121
122define <4 x i32> @vextsb2wBE(<16 x i8> %a) {
123; CHECK-BE-LABEL: vextsb2wBE:
124; CHECK-BE:       # %bb.0: # %entry
125; CHECK-BE-NEXT:    vextsb2w 2, 2
126; CHECK-BE-NEXT:    blr
127; CHECK-LE-LABEL: vextsb2wBE:
128; CHECK-LE:       # %bb.0: # %entry
129; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 13
130; CHECK-LE-NEXT:    vextsb2w 2, 2
131; CHECK-LE-NEXT:    blr
132entry:
133  %vecext = extractelement <16 x i8> %a, i32 3
134  %conv = sext i8 %vecext to i32
135  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
136  %vecext1 = extractelement <16 x i8> %a, i32 7
137  %conv2 = sext i8 %vecext1 to i32
138  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
139  %vecext4 = extractelement <16 x i8> %a, i32 11
140  %conv5 = sext i8 %vecext4 to i32
141  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
142  %vecext7 = extractelement <16 x i8> %a, i32 15
143  %conv8 = sext i8 %vecext7 to i32
144  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
145  ret <4 x i32> %vecinit9
146}
147
148define <2 x i64> @vextsb2dBE(<16 x i8> %a) {
149; CHECK-BE-LABEL: vextsb2dBE:
150; CHECK-BE:       # %bb.0: # %entry
151; CHECK-BE-NEXT:    vextsb2d 2, 2
152; CHECK-BE-NEXT:    blr
153; CHECK-LE-LABEL: vextsb2dBE:
154; CHECK-LE:       # %bb.0: # %entry
155; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 9
156; CHECK-LE-NEXT:    vextsb2d 2, 2
157; CHECK-LE-NEXT:    blr
158entry:
159  %vecext = extractelement <16 x i8> %a, i32 7
160  %conv = sext i8 %vecext to i64
161  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
162  %vecext1 = extractelement <16 x i8> %a, i32 15
163  %conv2 = sext i8 %vecext1 to i64
164  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
165  ret <2 x i64> %vecinit3
166}
167
168define <4 x i32> @vextsh2wBE(<8 x i16> %a) {
169; CHECK-BE-LABEL: vextsh2wBE:
170; CHECK-BE:       # %bb.0: # %entry
171; CHECK-BE-NEXT:    vextsh2w 2, 2
172; CHECK-BE-NEXT:    blr
173; CHECK-LE-LABEL: vextsh2wBE:
174; CHECK-LE:       # %bb.0: # %entry
175; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 14
176; CHECK-LE-NEXT:    vextsh2w 2, 2
177; CHECK-LE-NEXT:    blr
178entry:
179  %vecext = extractelement <8 x i16> %a, i32 1
180  %conv = sext i16 %vecext to i32
181  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
182  %vecext1 = extractelement <8 x i16> %a, i32 3
183  %conv2 = sext i16 %vecext1 to i32
184  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
185  %vecext4 = extractelement <8 x i16> %a, i32 5
186  %conv5 = sext i16 %vecext4 to i32
187  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
188  %vecext7 = extractelement <8 x i16> %a, i32 7
189  %conv8 = sext i16 %vecext7 to i32
190  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
191  ret <4 x i32> %vecinit9
192}
193
194define <2 x i64> @vextsh2dBE(<8 x i16> %a) {
195; CHECK-BE-LABEL: vextsh2dBE:
196; CHECK-BE:       # %bb.0: # %entry
197; CHECK-BE-NEXT:    vextsh2d 2, 2
198; CHECK-BE-NEXT:    blr
199; CHECK-LE-LABEL: vextsh2dBE:
200; CHECK-LE:       # %bb.0: # %entry
201; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 10
202; CHECK-LE-NEXT:    vextsh2d 2, 2
203; CHECK-LE-NEXT:    blr
204entry:
205  %vecext = extractelement <8 x i16> %a, i32 3
206  %conv = sext i16 %vecext to i64
207  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
208  %vecext1 = extractelement <8 x i16> %a, i32 7
209  %conv2 = sext i16 %vecext1 to i64
210  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
211  ret <2 x i64> %vecinit3
212}
213
214define <2 x i64> @vextsw2dBE(<4 x i32> %a) {
215; CHECK-BE-LABEL: vextsw2dBE:
216; CHECK-BE:       # %bb.0: # %entry
217; CHECK-BE-NEXT:    vextsw2d 2, 2
218; CHECK-BE-NEXT:    blr
219; CHECK-LE-LABEL: vextsw2dBE:
220; CHECK-LE:       # %bb.0: # %entry
221; CHECK-LE-NEXT:    vsldoi 2, 2, 2, 12
222; CHECK-LE-NEXT:    vextsw2d 2, 2
223; CHECK-LE-NEXT:    blr
224entry:
225  %vecext = extractelement <4 x i32> %a, i32 1
226  %conv = sext i32 %vecext to i64
227  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
228  %vecext1 = extractelement <4 x i32> %a, i32 3
229  %conv2 = sext i32 %vecext1 to i64
230  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
231  ret <2 x i64> %vecinit3
232}
233
234define <2 x i64> @vextDiffVectors(<4 x i32> %a, <4 x i32> %b) {
235; CHECK-LE-LABEL: vextDiffVectors:
236; CHECK-LE:       # %bb.0: # %entry
237; CHECK-LE-NOT:     vextsw2d
238
239; CHECK-BE-LABEL: vextDiffVectors:
240; CHECK-BE:       # %bb.0: # %entry
241; CHECK-BE-NOT:     vextsw2d
242entry:
243  %vecext = extractelement <4 x i32> %a, i32 0
244  %conv = sext i32 %vecext to i64
245  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
246  %vecext1 = extractelement <4 x i32> %b, i32 2
247  %conv2 = sext i32 %vecext1 to i64
248  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
249  ret <2 x i64> %vecinit3
250}
251
252define <8 x i16> @testInvalidExtend(<16 x i8> %a) {
253entry:
254; CHECK-LE-LABEL: testInvalidExtend:
255; CHECK-LE:       # %bb.0: # %entry
256; CHECK-LE-NOT:     vexts
257
258; CHECK-BE-LABEL: testInvalidExtend:
259; CHECK-BE:       # %bb.0: # %entry
260; CHECK-BE-NOT:     vexts
261
262  %vecext = extractelement <16 x i8> %a, i32 0
263  %conv = sext i8 %vecext to i16
264  %vecinit = insertelement <8 x i16> undef, i16 %conv, i32 0
265  %vecext1 = extractelement <16 x i8> %a, i32 2
266  %conv2 = sext i8 %vecext1 to i16
267  %vecinit3 = insertelement <8 x i16> %vecinit, i16 %conv2, i32 1
268  %vecext4 = extractelement <16 x i8> %a, i32 4
269  %conv5 = sext i8 %vecext4 to i16
270  %vecinit6 = insertelement <8 x i16> %vecinit3, i16 %conv5, i32 2
271  %vecext7 = extractelement <16 x i8> %a, i32 6
272  %conv8 = sext i8 %vecext7 to i16
273  %vecinit9 = insertelement <8 x i16> %vecinit6, i16 %conv8, i32 3
274  %vecext10 = extractelement <16 x i8> %a, i32 8
275  %conv11 = sext i8 %vecext10 to i16
276  %vecinit12 = insertelement <8 x i16> %vecinit9, i16 %conv11, i32 4
277  %vecext13 = extractelement <16 x i8> %a, i32 10
278  %conv14 = sext i8 %vecext13 to i16
279  %vecinit15 = insertelement <8 x i16> %vecinit12, i16 %conv14, i32 5
280  %vecext16 = extractelement <16 x i8> %a, i32 12
281  %conv17 = sext i8 %vecext16 to i16
282  %vecinit18 = insertelement <8 x i16> %vecinit15, i16 %conv17, i32 6
283  %vecext19 = extractelement <16 x i8> %a, i32 14
284  %conv20 = sext i8 %vecext19 to i16
285  %vecinit21 = insertelement <8 x i16> %vecinit18, i16 %conv20, i32 7
286  ret <8 x i16> %vecinit21
287}
288