1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mcpu=pwr9 < %s | FileCheck %s -check-prefix=PWR9
3target triple = "powerpc64le-unknown-linux-gnu"
4
5define <4 x i32> @vextsb2w(<16 x i8> %a) {
6; PWR9-LABEL: vextsb2w:
7; PWR9:       # BB#0: # %entry
8; PWR9-NEXT:    vextsb2w 2, 2
9; PWR9-NEXT:    blr
10entry:
11  %vecext = extractelement <16 x i8> %a, i32 0
12  %conv = sext i8 %vecext to i32
13  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
14  %vecext1 = extractelement <16 x i8> %a, i32 4
15  %conv2 = sext i8 %vecext1 to i32
16  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
17  %vecext4 = extractelement <16 x i8> %a, i32 8
18  %conv5 = sext i8 %vecext4 to i32
19  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
20  %vecext7 = extractelement <16 x i8> %a, i32 12
21  %conv8 = sext i8 %vecext7 to i32
22  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
23  ret <4 x i32> %vecinit9
24}
25
26define <2 x i64> @vextsb2d(<16 x i8> %a) {
27; PWR9-LABEL: vextsb2d:
28; PWR9:       # BB#0: # %entry
29; PWR9-NEXT:    vextsb2d 2, 2
30; PWR9-NEXT:    blr
31entry:
32  %vecext = extractelement <16 x i8> %a, i32 0
33  %conv = sext i8 %vecext to i64
34  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
35  %vecext1 = extractelement <16 x i8> %a, i32 8
36  %conv2 = sext i8 %vecext1 to i64
37  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
38  ret <2 x i64> %vecinit3
39}
40
41define <4 x i32> @vextsh2w(<8 x i16> %a) {
42; PWR9-LABEL: vextsh2w:
43; PWR9:       # BB#0: # %entry
44; PWR9-NEXT:    vextsh2w 2, 2
45; PWR9-NEXT:    blr
46entry:
47  %vecext = extractelement <8 x i16> %a, i32 0
48  %conv = sext i16 %vecext to i32
49  %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
50  %vecext1 = extractelement <8 x i16> %a, i32 2
51  %conv2 = sext i16 %vecext1 to i32
52  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
53  %vecext4 = extractelement <8 x i16> %a, i32 4
54  %conv5 = sext i16 %vecext4 to i32
55  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
56  %vecext7 = extractelement <8 x i16> %a, i32 6
57  %conv8 = sext i16 %vecext7 to i32
58  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
59  ret <4 x i32> %vecinit9
60}
61
62define <2 x i64> @vextsh2d(<8 x i16> %a) {
63; PWR9-LABEL: vextsh2d:
64; PWR9:       # BB#0: # %entry
65; PWR9-NEXT:    vextsh2d 2, 2
66; PWR9-NEXT:    blr
67entry:
68  %vecext = extractelement <8 x i16> %a, i32 0
69  %conv = sext i16 %vecext to i64
70  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
71  %vecext1 = extractelement <8 x i16> %a, i32 4
72  %conv2 = sext i16 %vecext1 to i64
73  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
74  ret <2 x i64> %vecinit3
75}
76
77define <2 x i64> @vextsw2d(<4 x i32> %a) {
78; PWR9-LABEL: vextsw2d:
79; PWR9:       # BB#0: # %entry
80; PWR9-NEXT:    vextsw2d 2, 2
81; PWR9-NEXT:    blr
82entry:
83  %vecext = extractelement <4 x i32> %a, i32 0
84  %conv = sext i32 %vecext to i64
85  %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
86  %vecext1 = extractelement <4 x i32> %a, i32 2
87  %conv2 = sext i32 %vecext1 to i64
88  %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
89  ret <2 x i64> %vecinit3
90}
91