1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; Test the doubleword comparison expansions on Power7
3;
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
5; RUN:   -mcpu=pwr7 < %s | FileCheck %s
6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
7; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
8
9define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
10; CHECK-LABEL: v2si64_cmp:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vcmpequw 2, 2, 3
13; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
14; CHECK-NEXT:    addi 3, 3, .LCPI0_0@toc@l
15; CHECK-NEXT:    lvx 3, 0, 3
16; CHECK-NEXT:    vperm 3, 2, 2, 3
17; CHECK-NEXT:    xxland 34, 35, 34
18; CHECK-NEXT:    blr
19;
20; CHECK-BE-LABEL: v2si64_cmp:
21; CHECK-BE:       # %bb.0:
22; CHECK-BE-NEXT:    vcmpequw 2, 2, 3
23; CHECK-BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
24; CHECK-BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
25; CHECK-BE-NEXT:    lxvw4x 35, 0, 3
26; CHECK-BE-NEXT:    vperm 3, 2, 2, 3
27; CHECK-BE-NEXT:    xxland 34, 35, 34
28; CHECK-BE-NEXT:    blr
29  %cmp = icmp eq <2 x i64> %x, %y
30  %result = sext <2 x i1> %cmp to <2 x i64>
31  ret <2 x i64> %result
32}
33
34; Greater than signed
35define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
36; CHECK-LABEL: v2si64_cmp_gt:
37; CHECK:       # %bb.0:
38; CHECK-NEXT:    xxswapd 0, 35
39; CHECK-NEXT:    addi 3, 1, -32
40; CHECK-NEXT:    addi 4, 1, -48
41; CHECK-NEXT:    xxswapd 1, 34
42; CHECK-NEXT:    stxvd2x 0, 0, 3
43; CHECK-NEXT:    stxvd2x 1, 0, 4
44; CHECK-NEXT:    ld 3, -24(1)
45; CHECK-NEXT:    ld 4, -40(1)
46; CHECK-NEXT:    ld 6, -48(1)
47; CHECK-NEXT:    cmpd 4, 3
48; CHECK-NEXT:    li 3, 0
49; CHECK-NEXT:    li 4, -1
50; CHECK-NEXT:    iselgt 5, 4, 3
51; CHECK-NEXT:    std 5, -8(1)
52; CHECK-NEXT:    ld 5, -32(1)
53; CHECK-NEXT:    cmpd 6, 5
54; CHECK-NEXT:    iselgt 3, 4, 3
55; CHECK-NEXT:    std 3, -16(1)
56; CHECK-NEXT:    addi 3, 1, -16
57; CHECK-NEXT:    lxvd2x 0, 0, 3
58; CHECK-NEXT:    xxswapd 34, 0
59; CHECK-NEXT:    blr
60;
61; CHECK-BE-LABEL: v2si64_cmp_gt:
62; CHECK-BE:       # %bb.0:
63; CHECK-BE-NEXT:    addi 3, 1, -32
64; CHECK-BE-NEXT:    addi 4, 1, -48
65; CHECK-BE-NEXT:    stxvd2x 35, 0, 3
66; CHECK-BE-NEXT:    stxvd2x 34, 0, 4
67; CHECK-BE-NEXT:    ld 3, -24(1)
68; CHECK-BE-NEXT:    ld 4, -40(1)
69; CHECK-BE-NEXT:    ld 6, -48(1)
70; CHECK-BE-NEXT:    cmpd 4, 3
71; CHECK-BE-NEXT:    li 3, 0
72; CHECK-BE-NEXT:    li 4, -1
73; CHECK-BE-NEXT:    iselgt 5, 4, 3
74; CHECK-BE-NEXT:    std 5, -8(1)
75; CHECK-BE-NEXT:    ld 5, -32(1)
76; CHECK-BE-NEXT:    cmpd 6, 5
77; CHECK-BE-NEXT:    iselgt 3, 4, 3
78; CHECK-BE-NEXT:    std 3, -16(1)
79; CHECK-BE-NEXT:    addi 3, 1, -16
80; CHECK-BE-NEXT:    lxvd2x 34, 0, 3
81; CHECK-BE-NEXT:    blr
82  %cmp = icmp sgt <2 x i64> %x, %y
83  %result = sext <2 x i1> %cmp to <2 x i64>
84  ret <2 x i64> %result
85}
86
87; Greater than unsigned
88define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone {
89; CHECK-LABEL: v2ui64_cmp_gt:
90; CHECK:       # %bb.0:
91; CHECK-NEXT:    xxswapd 0, 35
92; CHECK-NEXT:    addi 3, 1, -32
93; CHECK-NEXT:    addi 4, 1, -48
94; CHECK-NEXT:    xxswapd 1, 34
95; CHECK-NEXT:    stxvd2x 0, 0, 3
96; CHECK-NEXT:    stxvd2x 1, 0, 4
97; CHECK-NEXT:    ld 3, -24(1)
98; CHECK-NEXT:    ld 4, -40(1)
99; CHECK-NEXT:    ld 6, -48(1)
100; CHECK-NEXT:    cmpld 4, 3
101; CHECK-NEXT:    li 3, 0
102; CHECK-NEXT:    li 4, -1
103; CHECK-NEXT:    iselgt 5, 4, 3
104; CHECK-NEXT:    std 5, -8(1)
105; CHECK-NEXT:    ld 5, -32(1)
106; CHECK-NEXT:    cmpld 6, 5
107; CHECK-NEXT:    iselgt 3, 4, 3
108; CHECK-NEXT:    std 3, -16(1)
109; CHECK-NEXT:    addi 3, 1, -16
110; CHECK-NEXT:    lxvd2x 0, 0, 3
111; CHECK-NEXT:    xxswapd 34, 0
112; CHECK-NEXT:    blr
113;
114; CHECK-BE-LABEL: v2ui64_cmp_gt:
115; CHECK-BE:       # %bb.0:
116; CHECK-BE-NEXT:    addi 3, 1, -32
117; CHECK-BE-NEXT:    addi 4, 1, -48
118; CHECK-BE-NEXT:    stxvd2x 35, 0, 3
119; CHECK-BE-NEXT:    stxvd2x 34, 0, 4
120; CHECK-BE-NEXT:    ld 3, -24(1)
121; CHECK-BE-NEXT:    ld 4, -40(1)
122; CHECK-BE-NEXT:    ld 6, -48(1)
123; CHECK-BE-NEXT:    cmpld 4, 3
124; CHECK-BE-NEXT:    li 3, 0
125; CHECK-BE-NEXT:    li 4, -1
126; CHECK-BE-NEXT:    iselgt 5, 4, 3
127; CHECK-BE-NEXT:    std 5, -8(1)
128; CHECK-BE-NEXT:    ld 5, -32(1)
129; CHECK-BE-NEXT:    cmpld 6, 5
130; CHECK-BE-NEXT:    iselgt 3, 4, 3
131; CHECK-BE-NEXT:    std 3, -16(1)
132; CHECK-BE-NEXT:    addi 3, 1, -16
133; CHECK-BE-NEXT:    lxvd2x 34, 0, 3
134; CHECK-BE-NEXT:    blr
135  %cmp = icmp ugt <2 x i64> %x, %y
136  %result = sext <2 x i1> %cmp to <2 x i64>
137  ret <2 x i64> %result
138}
139
140; Check the intrinsics also
141declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
142declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
143declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone
144
145define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) {
146; CHECK-LABEL: test_vcmpequd_p:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vcmpequw 2, 2, 3
149; CHECK-NEXT:    xxlxor 35, 35, 35
150; CHECK-NEXT:    xxsldwi 0, 34, 34, 1
151; CHECK-NEXT:    xxland 0, 0, 34
152; CHECK-NEXT:    xxspltw 1, 0, 2
153; CHECK-NEXT:    xxspltw 0, 0, 0
154; CHECK-NEXT:    xxmrghd 34, 0, 1
155; CHECK-NEXT:    vcmpgtub. 2, 2, 3
156; CHECK-NEXT:    mfocrf 3, 2
157; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
158; CHECK-NEXT:    blr
159;
160; CHECK-BE-LABEL: test_vcmpequd_p:
161; CHECK-BE:       # %bb.0:
162; CHECK-BE-NEXT:    vcmpequw 2, 2, 3
163; CHECK-BE-NEXT:    xxlxor 35, 35, 35
164; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
165; CHECK-BE-NEXT:    xxland 0, 0, 34
166; CHECK-BE-NEXT:    xxspltw 1, 0, 2
167; CHECK-BE-NEXT:    xxspltw 0, 0, 0
168; CHECK-BE-NEXT:    xxmrghd 34, 0, 1
169; CHECK-BE-NEXT:    vcmpgtub. 2, 2, 3
170; CHECK-BE-NEXT:    mfocrf 3, 2
171; CHECK-BE-NEXT:    rlwinm 3, 3, 25, 31, 31
172; CHECK-BE-NEXT:    blr
173  %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
174  ret i32 %tmp
175}
176
177define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) {
178; CHECK-LABEL: test_vcmpgtsd_p:
179; CHECK:       # %bb.0:
180; CHECK-NEXT:    vcmpgtuw 4, 2, 3
181; CHECK-NEXT:    vcmpequw 5, 2, 3
182; CHECK-NEXT:    vcmpgtsw 2, 2, 3
183; CHECK-NEXT:    xxlxor 35, 35, 35
184; CHECK-NEXT:    xxsldwi 0, 36, 36, 1
185; CHECK-NEXT:    xxland 0, 0, 37
186; CHECK-NEXT:    xxlor 0, 34, 0
187; CHECK-NEXT:    xxspltw 1, 0, 2
188; CHECK-NEXT:    xxspltw 0, 0, 0
189; CHECK-NEXT:    xxmrghd 34, 0, 1
190; CHECK-NEXT:    vcmpgtub. 2, 2, 3
191; CHECK-NEXT:    mfocrf 3, 2
192; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
193; CHECK-NEXT:    blr
194;
195; CHECK-BE-LABEL: test_vcmpgtsd_p:
196; CHECK-BE:       # %bb.0:
197; CHECK-BE-NEXT:    vcmpgtuw 4, 2, 3
198; CHECK-BE-NEXT:    vcmpequw 5, 2, 3
199; CHECK-BE-NEXT:    vcmpgtsw 2, 2, 3
200; CHECK-BE-NEXT:    xxlxor 35, 35, 35
201; CHECK-BE-NEXT:    xxsldwi 0, 36, 36, 1
202; CHECK-BE-NEXT:    xxland 0, 0, 37
203; CHECK-BE-NEXT:    xxlor 0, 34, 0
204; CHECK-BE-NEXT:    xxspltw 1, 0, 2
205; CHECK-BE-NEXT:    xxspltw 0, 0, 0
206; CHECK-BE-NEXT:    xxmrghd 34, 0, 1
207; CHECK-BE-NEXT:    vcmpgtub. 2, 2, 3
208; CHECK-BE-NEXT:    mfocrf 3, 2
209; CHECK-BE-NEXT:    rlwinm 3, 3, 25, 31, 31
210; CHECK-BE-NEXT:    blr
211  %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y)
212  ret i32 %tmp
213}
214
215define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) {
216; CHECK-LABEL: test_vcmpgtud_p:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vcmpgtuw 4, 2, 3
219; CHECK-NEXT:    vcmpequw 2, 2, 3
220; CHECK-NEXT:    xxlxor 35, 35, 35
221; CHECK-NEXT:    xxsldwi 0, 36, 36, 1
222; CHECK-NEXT:    xxland 0, 0, 34
223; CHECK-NEXT:    xxlor 0, 36, 0
224; CHECK-NEXT:    xxspltw 1, 0, 2
225; CHECK-NEXT:    xxspltw 0, 0, 0
226; CHECK-NEXT:    xxmrghd 34, 0, 1
227; CHECK-NEXT:    vcmpgtub. 2, 2, 3
228; CHECK-NEXT:    mfocrf 3, 2
229; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
230; CHECK-NEXT:    blr
231;
232; CHECK-BE-LABEL: test_vcmpgtud_p:
233; CHECK-BE:       # %bb.0:
234; CHECK-BE-NEXT:    vcmpgtuw 4, 2, 3
235; CHECK-BE-NEXT:    vcmpequw 2, 2, 3
236; CHECK-BE-NEXT:    xxlxor 35, 35, 35
237; CHECK-BE-NEXT:    xxsldwi 0, 36, 36, 1
238; CHECK-BE-NEXT:    xxland 0, 0, 34
239; CHECK-BE-NEXT:    xxlor 0, 36, 0
240; CHECK-BE-NEXT:    xxspltw 1, 0, 2
241; CHECK-BE-NEXT:    xxspltw 0, 0, 0
242; CHECK-BE-NEXT:    xxmrghd 34, 0, 1
243; CHECK-BE-NEXT:    vcmpgtub. 2, 2, 3
244; CHECK-BE-NEXT:    mfocrf 3, 2
245; CHECK-BE-NEXT:    rlwinm 3, 3, 25, 31, 31
246; CHECK-BE-NEXT:    blr
247  %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y)
248  ret i32 %tmp
249}
250