1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Test the doubleword comparison expansions on Power7 3; 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 5; RUN: -mcpu=pwr7 < %s | FileCheck %s 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE 8 9define <2 x i64> @v2si64_cmp(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 10; CHECK-LABEL: v2si64_cmp: 11; CHECK: # %bb.0: 12; CHECK-NEXT: vcmpequw 2, 2, 3 13; CHECK-NEXT: blr 14; 15; CHECK-BE-LABEL: v2si64_cmp: 16; CHECK-BE: # %bb.0: 17; CHECK-BE-NEXT: vcmpequw 2, 2, 3 18; CHECK-BE-NEXT: blr 19 %cmp = icmp eq <2 x i64> %x, %y 20 %result = sext <2 x i1> %cmp to <2 x i64> 21 ret <2 x i64> %result 22} 23 24; Greater than signed 25define <2 x i64> @v2si64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 26; CHECK-LABEL: v2si64_cmp_gt: 27; CHECK: # %bb.0: 28; CHECK-NEXT: xxswapd 0, 35 29; CHECK-NEXT: addi 3, 1, -32 30; CHECK-NEXT: addi 4, 1, -48 31; CHECK-NEXT: xxswapd 1, 34 32; CHECK-NEXT: stxvd2x 0, 0, 3 33; CHECK-NEXT: stxvd2x 1, 0, 4 34; CHECK-NEXT: ld 3, -24(1) 35; CHECK-NEXT: ld 4, -40(1) 36; CHECK-NEXT: ld 6, -48(1) 37; CHECK-NEXT: cmpd 4, 3 38; CHECK-NEXT: li 3, 0 39; CHECK-NEXT: li 4, -1 40; CHECK-NEXT: iselgt 5, 4, 3 41; CHECK-NEXT: std 5, -8(1) 42; CHECK-NEXT: ld 5, -32(1) 43; CHECK-NEXT: cmpd 6, 5 44; CHECK-NEXT: iselgt 3, 4, 3 45; CHECK-NEXT: std 3, -16(1) 46; CHECK-NEXT: addi 3, 1, -16 47; CHECK-NEXT: lxvd2x 0, 0, 3 48; CHECK-NEXT: xxswapd 34, 0 49; CHECK-NEXT: blr 50; 51; CHECK-BE-LABEL: v2si64_cmp_gt: 52; CHECK-BE: # %bb.0: 53; CHECK-BE-NEXT: addi 3, 1, -32 54; CHECK-BE-NEXT: addi 4, 1, -48 55; CHECK-BE-NEXT: stxvd2x 35, 0, 3 56; CHECK-BE-NEXT: stxvd2x 34, 0, 4 57; CHECK-BE-NEXT: ld 3, -24(1) 58; CHECK-BE-NEXT: ld 4, -40(1) 59; CHECK-BE-NEXT: ld 6, -48(1) 60; CHECK-BE-NEXT: cmpd 4, 3 61; CHECK-BE-NEXT: li 3, 0 62; CHECK-BE-NEXT: li 4, -1 63; CHECK-BE-NEXT: iselgt 5, 4, 3 64; CHECK-BE-NEXT: std 5, -8(1) 65; CHECK-BE-NEXT: ld 5, -32(1) 66; CHECK-BE-NEXT: cmpd 6, 5 67; CHECK-BE-NEXT: iselgt 3, 4, 3 68; CHECK-BE-NEXT: std 3, -16(1) 69; CHECK-BE-NEXT: addi 3, 1, -16 70; CHECK-BE-NEXT: lxvd2x 34, 0, 3 71; CHECK-BE-NEXT: blr 72 %cmp = icmp sgt <2 x i64> %x, %y 73 %result = sext <2 x i1> %cmp to <2 x i64> 74 ret <2 x i64> %result 75} 76 77; Greater than unsigned 78define <2 x i64> @v2ui64_cmp_gt(<2 x i64> %x, <2 x i64> %y) nounwind readnone { 79; CHECK-LABEL: v2ui64_cmp_gt: 80; CHECK: # %bb.0: 81; CHECK-NEXT: xxswapd 0, 35 82; CHECK-NEXT: addi 3, 1, -32 83; CHECK-NEXT: addi 4, 1, -48 84; CHECK-NEXT: xxswapd 1, 34 85; CHECK-NEXT: stxvd2x 0, 0, 3 86; CHECK-NEXT: stxvd2x 1, 0, 4 87; CHECK-NEXT: ld 3, -24(1) 88; CHECK-NEXT: ld 4, -40(1) 89; CHECK-NEXT: ld 6, -48(1) 90; CHECK-NEXT: cmpld 4, 3 91; CHECK-NEXT: li 3, 0 92; CHECK-NEXT: li 4, -1 93; CHECK-NEXT: iselgt 5, 4, 3 94; CHECK-NEXT: std 5, -8(1) 95; CHECK-NEXT: ld 5, -32(1) 96; CHECK-NEXT: cmpld 6, 5 97; CHECK-NEXT: iselgt 3, 4, 3 98; CHECK-NEXT: std 3, -16(1) 99; CHECK-NEXT: addi 3, 1, -16 100; CHECK-NEXT: lxvd2x 0, 0, 3 101; CHECK-NEXT: xxswapd 34, 0 102; CHECK-NEXT: blr 103; 104; CHECK-BE-LABEL: v2ui64_cmp_gt: 105; CHECK-BE: # %bb.0: 106; CHECK-BE-NEXT: addi 3, 1, -32 107; CHECK-BE-NEXT: addi 4, 1, -48 108; CHECK-BE-NEXT: stxvd2x 35, 0, 3 109; CHECK-BE-NEXT: stxvd2x 34, 0, 4 110; CHECK-BE-NEXT: ld 3, -24(1) 111; CHECK-BE-NEXT: ld 4, -40(1) 112; CHECK-BE-NEXT: ld 6, -48(1) 113; CHECK-BE-NEXT: cmpld 4, 3 114; CHECK-BE-NEXT: li 3, 0 115; CHECK-BE-NEXT: li 4, -1 116; CHECK-BE-NEXT: iselgt 5, 4, 3 117; CHECK-BE-NEXT: std 5, -8(1) 118; CHECK-BE-NEXT: ld 5, -32(1) 119; CHECK-BE-NEXT: cmpld 6, 5 120; CHECK-BE-NEXT: iselgt 3, 4, 3 121; CHECK-BE-NEXT: std 3, -16(1) 122; CHECK-BE-NEXT: addi 3, 1, -16 123; CHECK-BE-NEXT: lxvd2x 34, 0, 3 124; CHECK-BE-NEXT: blr 125 %cmp = icmp ugt <2 x i64> %x, %y 126 %result = sext <2 x i1> %cmp to <2 x i64> 127 ret <2 x i64> %result 128} 129 130; Check the intrinsics also 131declare i32 @llvm.ppc.altivec.vcmpequd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 132declare i32 @llvm.ppc.altivec.vcmpgtsd.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 133declare i32 @llvm.ppc.altivec.vcmpgtud.p(i32, <2 x i64>, <2 x i64>) nounwind readnone 134 135define i32 @test_vcmpequd_p(<2 x i64> %x, <2 x i64> %y) { 136; CHECK-LABEL: test_vcmpequd_p: 137; CHECK: # %bb.0: 138; CHECK-NEXT: vcmpequw 2, 2, 3 139; CHECK-NEXT: xxlxor 35, 35, 35 140; CHECK-NEXT: xxsldwi 0, 34, 34, 1 141; CHECK-NEXT: xxland 0, 0, 34 142; CHECK-NEXT: xxspltw 1, 0, 2 143; CHECK-NEXT: xxspltw 0, 0, 0 144; CHECK-NEXT: xxmrghd 34, 0, 1 145; CHECK-NEXT: vcmpgtub. 2, 2, 3 146; CHECK-NEXT: mfocrf 3, 2 147; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 148; CHECK-NEXT: blr 149; 150; CHECK-BE-LABEL: test_vcmpequd_p: 151; CHECK-BE: # %bb.0: 152; CHECK-BE-NEXT: vcmpequw 2, 2, 3 153; CHECK-BE-NEXT: xxlxor 35, 35, 35 154; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 1 155; CHECK-BE-NEXT: xxland 0, 0, 34 156; CHECK-BE-NEXT: xxspltw 1, 0, 2 157; CHECK-BE-NEXT: xxspltw 0, 0, 0 158; CHECK-BE-NEXT: xxmrghd 34, 0, 1 159; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 160; CHECK-BE-NEXT: mfocrf 3, 2 161; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 162; CHECK-BE-NEXT: blr 163 %tmp = tail call i32 @llvm.ppc.altivec.vcmpequd.p(i32 2, <2 x i64> %x, <2 x i64> %y) 164 ret i32 %tmp 165} 166 167define i32 @test_vcmpgtsd_p(<2 x i64> %x, <2 x i64> %y) { 168; CHECK-LABEL: test_vcmpgtsd_p: 169; CHECK: # %bb.0: 170; CHECK-NEXT: vcmpgtuw 4, 2, 3 171; CHECK-NEXT: vcmpequw 5, 2, 3 172; CHECK-NEXT: vcmpgtsw 2, 2, 3 173; CHECK-NEXT: xxlxor 35, 35, 35 174; CHECK-NEXT: xxsldwi 0, 36, 36, 1 175; CHECK-NEXT: xxland 0, 0, 37 176; CHECK-NEXT: xxlor 0, 34, 0 177; CHECK-NEXT: xxspltw 1, 0, 2 178; CHECK-NEXT: xxspltw 0, 0, 0 179; CHECK-NEXT: xxmrghd 34, 0, 1 180; CHECK-NEXT: vcmpgtub. 2, 2, 3 181; CHECK-NEXT: mfocrf 3, 2 182; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 183; CHECK-NEXT: blr 184; 185; CHECK-BE-LABEL: test_vcmpgtsd_p: 186; CHECK-BE: # %bb.0: 187; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3 188; CHECK-BE-NEXT: vcmpequw 5, 2, 3 189; CHECK-BE-NEXT: vcmpgtsw 2, 2, 3 190; CHECK-BE-NEXT: xxlxor 35, 35, 35 191; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1 192; CHECK-BE-NEXT: xxland 0, 0, 37 193; CHECK-BE-NEXT: xxlor 0, 34, 0 194; CHECK-BE-NEXT: xxspltw 1, 0, 2 195; CHECK-BE-NEXT: xxspltw 0, 0, 0 196; CHECK-BE-NEXT: xxmrghd 34, 0, 1 197; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 198; CHECK-BE-NEXT: mfocrf 3, 2 199; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 200; CHECK-BE-NEXT: blr 201 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsd.p(i32 2, <2 x i64> %x, <2 x i64> %y) 202 ret i32 %tmp 203} 204 205define i32 @test_vcmpgtud_p(<2 x i64> %x, <2 x i64> %y) { 206; CHECK-LABEL: test_vcmpgtud_p: 207; CHECK: # %bb.0: 208; CHECK-NEXT: vcmpgtuw 4, 2, 3 209; CHECK-NEXT: vcmpequw 2, 2, 3 210; CHECK-NEXT: xxlxor 35, 35, 35 211; CHECK-NEXT: xxsldwi 0, 36, 36, 1 212; CHECK-NEXT: xxland 0, 0, 34 213; CHECK-NEXT: xxlor 0, 36, 0 214; CHECK-NEXT: xxspltw 1, 0, 2 215; CHECK-NEXT: xxspltw 0, 0, 0 216; CHECK-NEXT: xxmrghd 34, 0, 1 217; CHECK-NEXT: vcmpgtub. 2, 2, 3 218; CHECK-NEXT: mfocrf 3, 2 219; CHECK-NEXT: rlwinm 3, 3, 25, 31, 31 220; CHECK-NEXT: blr 221; 222; CHECK-BE-LABEL: test_vcmpgtud_p: 223; CHECK-BE: # %bb.0: 224; CHECK-BE-NEXT: vcmpgtuw 4, 2, 3 225; CHECK-BE-NEXT: vcmpequw 2, 2, 3 226; CHECK-BE-NEXT: xxlxor 35, 35, 35 227; CHECK-BE-NEXT: xxsldwi 0, 36, 36, 1 228; CHECK-BE-NEXT: xxland 0, 0, 34 229; CHECK-BE-NEXT: xxlor 0, 36, 0 230; CHECK-BE-NEXT: xxspltw 1, 0, 2 231; CHECK-BE-NEXT: xxspltw 0, 0, 0 232; CHECK-BE-NEXT: xxmrghd 34, 0, 1 233; CHECK-BE-NEXT: vcmpgtub. 2, 2, 3 234; CHECK-BE-NEXT: mfocrf 3, 2 235; CHECK-BE-NEXT: rlwinm 3, 3, 25, 31, 31 236; CHECK-BE-NEXT: blr 237 %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtud.p(i32 2, <2 x i64> %x, <2 x i64> %y) 238 ret i32 %tmp 239} 240