1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-BE
8
9define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
10; CHECK-LABEL: test8i8:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    lvx v2, 0, r4
13; CHECK-NEXT:    mfvsrd r4, v2
14; CHECK-NEXT:    xxswapd vs0, v2
15; CHECK-NEXT:    clrldi r5, r4, 48
16; CHECK-NEXT:    mtvsrd f1, r5
17; CHECK-NEXT:    rldicl r5, r4, 48, 48
18; CHECK-NEXT:    mtvsrd f2, r5
19; CHECK-NEXT:    rldicl r5, r4, 32, 48
20; CHECK-NEXT:    rldicl r4, r4, 16, 48
21; CHECK-NEXT:    mtvsrd f3, r5
22; CHECK-NEXT:    xxswapd v2, vs1
23; CHECK-NEXT:    mfvsrd r5, f0
24; CHECK-NEXT:    xxswapd v3, vs2
25; CHECK-NEXT:    mtvsrd f0, r4
26; CHECK-NEXT:    clrldi r4, r5, 48
27; CHECK-NEXT:    mtvsrd f1, r4
28; CHECK-NEXT:    rldicl r4, r5, 48, 48
29; CHECK-NEXT:    xxswapd v4, vs0
30; CHECK-NEXT:    mtvsrd f2, r4
31; CHECK-NEXT:    rldicl r4, r5, 32, 48
32; CHECK-NEXT:    rldicl r5, r5, 16, 48
33; CHECK-NEXT:    vmrglb v2, v3, v2
34; CHECK-NEXT:    xxswapd v3, vs3
35; CHECK-NEXT:    mtvsrd f3, r4
36; CHECK-NEXT:    xxswapd v5, vs1
37; CHECK-NEXT:    mtvsrd f0, r5
38; CHECK-NEXT:    xxswapd v0, vs2
39; CHECK-NEXT:    xxswapd v1, vs3
40; CHECK-NEXT:    vmrglb v3, v4, v3
41; CHECK-NEXT:    xxswapd v6, vs0
42; CHECK-NEXT:    vmrglb v4, v0, v5
43; CHECK-NEXT:    vmrglb v5, v6, v1
44; CHECK-NEXT:    vmrglh v2, v3, v2
45; CHECK-NEXT:    vmrglh v3, v5, v4
46; CHECK-NEXT:    vmrglw v2, v2, v3
47; CHECK-NEXT:    xxswapd vs0, v2
48; CHECK-NEXT:    stfdx f0, 0, r3
49; CHECK-NEXT:    blr
50;
51; CHECK-BE-LABEL: test8i8:
52; CHECK-BE:       # %bb.0: # %entry
53; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
54; CHECK-BE-NEXT:    addi r4, r1, -32
55; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
56; CHECK-BE-NEXT:    lhz r4, -18(r1)
57; CHECK-BE-NEXT:    stb r4, -48(r1)
58; CHECK-BE-NEXT:    lhz r4, -20(r1)
59; CHECK-BE-NEXT:    stb r4, -64(r1)
60; CHECK-BE-NEXT:    lhz r4, -22(r1)
61; CHECK-BE-NEXT:    stb r4, -80(r1)
62; CHECK-BE-NEXT:    lhz r4, -24(r1)
63; CHECK-BE-NEXT:    stb r4, -96(r1)
64; CHECK-BE-NEXT:    lhz r4, -26(r1)
65; CHECK-BE-NEXT:    stb r4, -112(r1)
66; CHECK-BE-NEXT:    lhz r4, -28(r1)
67; CHECK-BE-NEXT:    stb r4, -128(r1)
68; CHECK-BE-NEXT:    lhz r4, -30(r1)
69; CHECK-BE-NEXT:    stb r4, -144(r1)
70; CHECK-BE-NEXT:    lhz r4, -32(r1)
71; CHECK-BE-NEXT:    stb r4, -160(r1)
72; CHECK-BE-NEXT:    addi r4, r1, -48
73; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
74; CHECK-BE-NEXT:    addi r4, r1, -64
75; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
76; CHECK-BE-NEXT:    addi r4, r1, -80
77; CHECK-BE-NEXT:    lxvw4x v4, 0, r4
78; CHECK-BE-NEXT:    addi r4, r1, -96
79; CHECK-BE-NEXT:    lxvw4x v5, 0, r4
80; CHECK-BE-NEXT:    addi r4, r1, -112
81; CHECK-BE-NEXT:    lxvw4x v0, 0, r4
82; CHECK-BE-NEXT:    addi r4, r1, -128
83; CHECK-BE-NEXT:    lxvw4x v1, 0, r4
84; CHECK-BE-NEXT:    addi r4, r1, -144
85; CHECK-BE-NEXT:    lxvw4x v6, 0, r4
86; CHECK-BE-NEXT:    addi r4, r1, -160
87; CHECK-BE-NEXT:    lxvw4x v7, 0, r4
88; CHECK-BE-NEXT:    vmrghb v2, v3, v2
89; CHECK-BE-NEXT:    vmrghb v3, v5, v4
90; CHECK-BE-NEXT:    vmrghb v4, v1, v0
91; CHECK-BE-NEXT:    addi r4, r1, -16
92; CHECK-BE-NEXT:    vmrghh v2, v3, v2
93; CHECK-BE-NEXT:    vmrghb v5, v7, v6
94; CHECK-BE-NEXT:    vmrghh v3, v5, v4
95; CHECK-BE-NEXT:    vmrghw v2, v3, v2
96; CHECK-BE-NEXT:    stxvd2x v2, 0, r4
97; CHECK-BE-NEXT:    ld r4, -16(r1)
98; CHECK-BE-NEXT:    std r4, 0(r3)
99; CHECK-BE-NEXT:    blr
100entry:
101  %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
102  %1 = trunc <8 x i16> %0 to <8 x i8>
103  store <8 x i8> %1, <8 x i8>* %Sink, align 16
104  ret void
105}
106
107define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
108; CHECK-LABEL: test4i8:
109; CHECK:       # %bb.0: # %entry
110; CHECK-NEXT:    lvx v2, 0, r4
111; CHECK-NEXT:    xxswapd vs0, v2
112; CHECK-NEXT:    mfvsrd r4, f0
113; CHECK-NEXT:    clrldi r5, r4, 48
114; CHECK-NEXT:    mtvsrd f0, r5
115; CHECK-NEXT:    rldicl r5, r4, 48, 48
116; CHECK-NEXT:    mtvsrd f1, r5
117; CHECK-NEXT:    rldicl r5, r4, 32, 48
118; CHECK-NEXT:    rldicl r4, r4, 16, 48
119; CHECK-NEXT:    mtvsrd f2, r5
120; CHECK-NEXT:    xxswapd v2, vs0
121; CHECK-NEXT:    mtvsrd f3, r4
122; CHECK-NEXT:    xxswapd v3, vs1
123; CHECK-NEXT:    xxswapd v4, vs2
124; CHECK-NEXT:    xxswapd v5, vs3
125; CHECK-NEXT:    vmrglb v2, v3, v2
126; CHECK-NEXT:    vmrglb v3, v5, v4
127; CHECK-NEXT:    vmrglh v2, v3, v2
128; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
129; CHECK-NEXT:    stfiwx f0, 0, r3
130; CHECK-NEXT:    blr
131;
132; CHECK-BE-LABEL: test4i8:
133; CHECK-BE:       # %bb.0: # %entry
134; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
135; CHECK-BE-NEXT:    addi r4, r1, -32
136; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
137; CHECK-BE-NEXT:    lhz r4, -26(r1)
138; CHECK-BE-NEXT:    stb r4, -48(r1)
139; CHECK-BE-NEXT:    lhz r4, -28(r1)
140; CHECK-BE-NEXT:    stb r4, -64(r1)
141; CHECK-BE-NEXT:    lhz r4, -30(r1)
142; CHECK-BE-NEXT:    stb r4, -80(r1)
143; CHECK-BE-NEXT:    lhz r4, -32(r1)
144; CHECK-BE-NEXT:    stb r4, -96(r1)
145; CHECK-BE-NEXT:    addi r4, r1, -48
146; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
147; CHECK-BE-NEXT:    addi r4, r1, -64
148; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
149; CHECK-BE-NEXT:    addi r4, r1, -80
150; CHECK-BE-NEXT:    lxvw4x v4, 0, r4
151; CHECK-BE-NEXT:    addi r4, r1, -96
152; CHECK-BE-NEXT:    lxvw4x v5, 0, r4
153; CHECK-BE-NEXT:    vmrghb v2, v3, v2
154; CHECK-BE-NEXT:    addi r4, r1, -16
155; CHECK-BE-NEXT:    vmrghb v3, v5, v4
156; CHECK-BE-NEXT:    vmrghh v2, v3, v2
157; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
158; CHECK-BE-NEXT:    lwz r4, -16(r1)
159; CHECK-BE-NEXT:    stw r4, 0(r3)
160; CHECK-BE-NEXT:    blr
161entry:
162  %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
163  %1 = trunc <4 x i16> %0 to <4 x i8>
164  store <4 x i8> %1, <4 x i8>* %Sink, align 16
165  ret void
166}
167
168define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
169; CHECK-LABEL: test4i8w:
170; CHECK:       # %bb.0: # %entry
171; CHECK-NEXT:    lvx v2, 0, r4
172; CHECK-NEXT:    xxswapd vs0, v2
173; CHECK-NEXT:    mfvsrwz r4, v2
174; CHECK-NEXT:    xxsldwi vs1, v2, v2, 1
175; CHECK-NEXT:    xxsldwi vs3, v2, v2, 3
176; CHECK-NEXT:    mtvsrd f2, r4
177; CHECK-NEXT:    mfvsrwz r4, f0
178; CHECK-NEXT:    mfvsrwz r5, f1
179; CHECK-NEXT:    xxswapd v4, vs2
180; CHECK-NEXT:    mtvsrd f0, r4
181; CHECK-NEXT:    mfvsrwz r4, f3
182; CHECK-NEXT:    mtvsrd f1, r5
183; CHECK-NEXT:    xxswapd v2, vs0
184; CHECK-NEXT:    mtvsrd f3, r4
185; CHECK-NEXT:    xxswapd v3, vs1
186; CHECK-NEXT:    xxswapd v5, vs3
187; CHECK-NEXT:    vmrglb v2, v3, v2
188; CHECK-NEXT:    vmrglb v3, v5, v4
189; CHECK-NEXT:    vmrglh v2, v3, v2
190; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
191; CHECK-NEXT:    stfiwx f0, 0, r3
192; CHECK-NEXT:    blr
193;
194; CHECK-BE-LABEL: test4i8w:
195; CHECK-BE:       # %bb.0: # %entry
196; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
197; CHECK-BE-NEXT:    addi r4, r1, -32
198; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
199; CHECK-BE-NEXT:    lwz r4, -20(r1)
200; CHECK-BE-NEXT:    stb r4, -48(r1)
201; CHECK-BE-NEXT:    lwz r4, -24(r1)
202; CHECK-BE-NEXT:    stb r4, -64(r1)
203; CHECK-BE-NEXT:    lwz r4, -28(r1)
204; CHECK-BE-NEXT:    stb r4, -80(r1)
205; CHECK-BE-NEXT:    lwz r4, -32(r1)
206; CHECK-BE-NEXT:    stb r4, -96(r1)
207; CHECK-BE-NEXT:    addi r4, r1, -48
208; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
209; CHECK-BE-NEXT:    addi r4, r1, -64
210; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
211; CHECK-BE-NEXT:    addi r4, r1, -80
212; CHECK-BE-NEXT:    lxvw4x v4, 0, r4
213; CHECK-BE-NEXT:    addi r4, r1, -96
214; CHECK-BE-NEXT:    lxvw4x v5, 0, r4
215; CHECK-BE-NEXT:    vmrghb v2, v3, v2
216; CHECK-BE-NEXT:    addi r4, r1, -16
217; CHECK-BE-NEXT:    vmrghb v3, v5, v4
218; CHECK-BE-NEXT:    vmrghh v2, v3, v2
219; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
220; CHECK-BE-NEXT:    lwz r4, -16(r1)
221; CHECK-BE-NEXT:    stw r4, 0(r3)
222; CHECK-BE-NEXT:    blr
223entry:
224  %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
225  %1 = trunc <4 x i32> %0 to <4 x i8>
226  store <4 x i8> %1, <4 x i8>* %Sink, align 16
227  ret void
228}
229
230define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
231; CHECK-LABEL: test2i8:
232; CHECK:       # %bb.0: # %entry
233; CHECK-NEXT:    lvx v2, 0, r4
234; CHECK-NEXT:    xxswapd vs0, v2
235; CHECK-NEXT:    mfvsrd r4, f0
236; CHECK-NEXT:    clrldi r5, r4, 48
237; CHECK-NEXT:    rldicl r4, r4, 48, 48
238; CHECK-NEXT:    mtvsrd f0, r5
239; CHECK-NEXT:    mtvsrd f1, r4
240; CHECK-NEXT:    xxswapd v2, vs0
241; CHECK-NEXT:    xxswapd v3, vs1
242; CHECK-NEXT:    vmrglb v2, v3, v2
243; CHECK-NEXT:    xxswapd vs0, v2
244; CHECK-NEXT:    mfvsrd r4, f0
245; CHECK-NEXT:    clrldi r4, r4, 48
246; CHECK-NEXT:    sth r4, 0(r3)
247; CHECK-NEXT:    blr
248;
249; CHECK-BE-LABEL: test2i8:
250; CHECK-BE:       # %bb.0: # %entry
251; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
252; CHECK-BE-NEXT:    addi r4, r1, -32
253; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
254; CHECK-BE-NEXT:    lhz r4, -30(r1)
255; CHECK-BE-NEXT:    stb r4, -48(r1)
256; CHECK-BE-NEXT:    lhz r4, -32(r1)
257; CHECK-BE-NEXT:    stb r4, -64(r1)
258; CHECK-BE-NEXT:    addi r4, r1, -48
259; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
260; CHECK-BE-NEXT:    addi r4, r1, -64
261; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
262; CHECK-BE-NEXT:    addi r4, r1, -16
263; CHECK-BE-NEXT:    vmrghb v2, v3, v2
264; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
265; CHECK-BE-NEXT:    lhz r4, -16(r1)
266; CHECK-BE-NEXT:    sth r4, 0(r3)
267; CHECK-BE-NEXT:    blr
268entry:
269  %0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
270  %1 = trunc <2 x i16> %0 to <2 x i8>
271  store <2 x i8> %1, <2 x i8>* %Sink, align 16
272  ret void
273}
274
275define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
276; CHECK-LABEL: test4i16:
277; CHECK:       # %bb.0: # %entry
278; CHECK-NEXT:    lvx v2, 0, r4
279; CHECK-NEXT:    xxswapd vs0, v2
280; CHECK-NEXT:    mfvsrwz r4, v2
281; CHECK-NEXT:    xxsldwi vs1, v2, v2, 1
282; CHECK-NEXT:    xxsldwi vs3, v2, v2, 3
283; CHECK-NEXT:    mtvsrd f2, r4
284; CHECK-NEXT:    mfvsrwz r4, f0
285; CHECK-NEXT:    mfvsrwz r5, f1
286; CHECK-NEXT:    xxswapd v4, vs2
287; CHECK-NEXT:    mtvsrd f0, r4
288; CHECK-NEXT:    mfvsrwz r4, f3
289; CHECK-NEXT:    mtvsrd f1, r5
290; CHECK-NEXT:    xxswapd v2, vs0
291; CHECK-NEXT:    mtvsrd f3, r4
292; CHECK-NEXT:    xxswapd v3, vs1
293; CHECK-NEXT:    xxswapd v5, vs3
294; CHECK-NEXT:    vmrglh v2, v3, v2
295; CHECK-NEXT:    vmrglh v3, v5, v4
296; CHECK-NEXT:    vmrglw v2, v3, v2
297; CHECK-NEXT:    xxswapd vs0, v2
298; CHECK-NEXT:    stfdx f0, 0, r3
299; CHECK-NEXT:    blr
300;
301; CHECK-BE-LABEL: test4i16:
302; CHECK-BE:       # %bb.0: # %entry
303; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
304; CHECK-BE-NEXT:    addi r4, r1, -32
305; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
306; CHECK-BE-NEXT:    lwz r4, -20(r1)
307; CHECK-BE-NEXT:    sth r4, -48(r1)
308; CHECK-BE-NEXT:    lwz r4, -24(r1)
309; CHECK-BE-NEXT:    sth r4, -64(r1)
310; CHECK-BE-NEXT:    lwz r4, -28(r1)
311; CHECK-BE-NEXT:    sth r4, -80(r1)
312; CHECK-BE-NEXT:    lwz r4, -32(r1)
313; CHECK-BE-NEXT:    sth r4, -96(r1)
314; CHECK-BE-NEXT:    addi r4, r1, -48
315; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
316; CHECK-BE-NEXT:    addi r4, r1, -64
317; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
318; CHECK-BE-NEXT:    addi r4, r1, -80
319; CHECK-BE-NEXT:    lxvw4x v4, 0, r4
320; CHECK-BE-NEXT:    addi r4, r1, -96
321; CHECK-BE-NEXT:    lxvw4x v5, 0, r4
322; CHECK-BE-NEXT:    vmrghh v2, v3, v2
323; CHECK-BE-NEXT:    addi r4, r1, -16
324; CHECK-BE-NEXT:    vmrghh v3, v5, v4
325; CHECK-BE-NEXT:    vmrghw v2, v3, v2
326; CHECK-BE-NEXT:    stxvd2x v2, 0, r4
327; CHECK-BE-NEXT:    ld r4, -16(r1)
328; CHECK-BE-NEXT:    std r4, 0(r3)
329; CHECK-BE-NEXT:    blr
330entry:
331  %0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
332  %1 = trunc <4 x i32> %0 to <4 x i16>
333  store <4 x i16> %1, <4 x i16>* %Sink, align 16
334  ret void
335}
336
337define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly %SrcPtr) {
338; CHECK-LABEL: test2i16:
339; CHECK:       # %bb.0: # %entry
340; CHECK-NEXT:    lvx v2, 0, r4
341; CHECK-NEXT:    xxswapd vs0, v2
342; CHECK-NEXT:    xxsldwi vs1, v2, v2, 1
343; CHECK-NEXT:    mfvsrwz r4, f0
344; CHECK-NEXT:    mfvsrwz r5, f1
345; CHECK-NEXT:    mtvsrd f0, r4
346; CHECK-NEXT:    mtvsrd f1, r5
347; CHECK-NEXT:    xxswapd v2, vs0
348; CHECK-NEXT:    xxswapd v3, vs1
349; CHECK-NEXT:    vmrglh v2, v3, v2
350; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
351; CHECK-NEXT:    stfiwx f0, 0, r3
352; CHECK-NEXT:    blr
353;
354; CHECK-BE-LABEL: test2i16:
355; CHECK-BE:       # %bb.0: # %entry
356; CHECK-BE-NEXT:    lxvw4x vs0, 0, r4
357; CHECK-BE-NEXT:    addi r4, r1, -32
358; CHECK-BE-NEXT:    stxvw4x vs0, 0, r4
359; CHECK-BE-NEXT:    lwz r4, -28(r1)
360; CHECK-BE-NEXT:    sth r4, -48(r1)
361; CHECK-BE-NEXT:    lwz r4, -32(r1)
362; CHECK-BE-NEXT:    sth r4, -64(r1)
363; CHECK-BE-NEXT:    addi r4, r1, -48
364; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
365; CHECK-BE-NEXT:    addi r4, r1, -64
366; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
367; CHECK-BE-NEXT:    addi r4, r1, -16
368; CHECK-BE-NEXT:    vmrghh v2, v3, v2
369; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
370; CHECK-BE-NEXT:    lwz r4, -16(r1)
371; CHECK-BE-NEXT:    stw r4, 0(r3)
372; CHECK-BE-NEXT:    blr
373entry:
374  %0 = load <2 x i32>, <2 x i32>* %SrcPtr, align 16
375  %1 = trunc <2 x i32> %0 to <2 x i16>
376  store <2 x i16> %1, <2 x i16>* %Sink, align 16
377  ret void
378}
379
380define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) {
381; CHECK-LABEL: test2i16d:
382; CHECK:       # %bb.0: # %entry
383; CHECK-NEXT:    lxvd2x vs0, 0, r4
384; CHECK-NEXT:    xxswapd vs1, vs0
385; CHECK-NEXT:    mfvsrwz r4, f0
386; CHECK-NEXT:    mtvsrd f0, r4
387; CHECK-NEXT:    mfvsrwz r5, f1
388; CHECK-NEXT:    xxswapd v2, vs0
389; CHECK-NEXT:    mtvsrd f1, r5
390; CHECK-NEXT:    xxswapd v3, vs1
391; CHECK-NEXT:    vmrglh v2, v3, v2
392; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
393; CHECK-NEXT:    stfiwx f0, 0, r3
394; CHECK-NEXT:    blr
395;
396; CHECK-BE-LABEL: test2i16d:
397; CHECK-BE:       # %bb.0: # %entry
398; CHECK-BE-NEXT:    lxvd2x vs0, 0, r4
399; CHECK-BE-NEXT:    addi r4, r1, -32
400; CHECK-BE-NEXT:    stxvd2x vs0, 0, r4
401; CHECK-BE-NEXT:    lwz r4, -20(r1)
402; CHECK-BE-NEXT:    sth r4, -48(r1)
403; CHECK-BE-NEXT:    lwz r4, -28(r1)
404; CHECK-BE-NEXT:    sth r4, -64(r1)
405; CHECK-BE-NEXT:    addi r4, r1, -48
406; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
407; CHECK-BE-NEXT:    addi r4, r1, -64
408; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
409; CHECK-BE-NEXT:    addi r4, r1, -16
410; CHECK-BE-NEXT:    vmrghh v2, v3, v2
411; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
412; CHECK-BE-NEXT:    lwz r4, -16(r1)
413; CHECK-BE-NEXT:    stw r4, 0(r3)
414; CHECK-BE-NEXT:    blr
415entry:
416  %0 = load <2 x i64>, <2 x i64>* %SrcPtr, align 16
417  %1 = trunc <2 x i64> %0 to <2 x i16>
418  store <2 x i16> %1, <2 x i16>* %Sink, align 16
419  ret void
420}
421