1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
9
10@glob = common local_unnamed_addr global i64 0, align 8
11
12define i64 @test_llneull(i64 %a, i64 %b) {
13; CHECK-LABEL: test_llneull:
14; CHECK:       # BB#0: # %entry
15; CHECK-NEXT:    xor r3, r3, r4
16; CHECK-NEXT:    addic r4, r3, -1
17; CHECK-NEXT:    subfe r3, r4, r3
18; CHECK-NEXT:    blr
19entry:
20  %cmp = icmp ne i64 %a, %b
21  %conv1 = zext i1 %cmp to i64
22  ret i64 %conv1
23}
24
25define i64 @test_llneull_sext(i64 %a, i64 %b) {
26; CHECK-LABEL: test_llneull_sext:
27; CHECK:       # BB#0: # %entry
28; CHECK-NEXT:    xor r3, r3, r4
29; CHECK-NEXT:    subfic r3, r3, 0
30; CHECK-NEXT:    subfe r3, r3, r3
31; CHECK-NEXT:    blr
32entry:
33  %cmp = icmp ne i64 %a, %b
34  %conv1 = sext i1 %cmp to i64
35  ret i64 %conv1
36}
37
38define i64 @test_llneull_z(i64 %a) {
39; CHECK-LABEL: test_llneull_z:
40; CHECK:       # BB#0: # %entry
41; CHECK-NEXT:    addic r4, r3, -1
42; CHECK-NEXT:    subfe r3, r4, r3
43; CHECK-NEXT:    blr
44entry:
45  %cmp = icmp ne i64 %a, 0
46  %conv1 = zext i1 %cmp to i64
47  ret i64 %conv1
48}
49
50define i64 @test_llneull_sext_z(i64 %a) {
51; CHECK-LABEL: test_llneull_sext_z:
52; CHECK:       # BB#0: # %entry
53; CHECK-NEXT:    subfic r3, r3, 0
54; CHECK-NEXT:    subfe r3, r3, r3
55; CHECK-NEXT:    blr
56entry:
57  %cmp = icmp ne i64 %a, 0
58  %conv1 = sext i1 %cmp to i64
59  ret i64 %conv1
60}
61
62define void @test_llneull_store(i64 %a, i64 %b) {
63; CHECK-LABEL: test_llneull_store:
64; CHECK:       # BB#0: # %entry
65; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
66; CHECK-NEXT:    xor r3, r3, r4
67; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
68; CHECK-NEXT:    addic r5, r3, -1
69; CHECK-NEXT:    subfe r3, r5, r3
70; CHECK-NEXT:    std r3, 0(r12)
71; CHECK-NEXT:    blr
72entry:
73  %cmp = icmp ne i64 %a, %b
74  %conv1 = zext i1 %cmp to i64
75  store i64 %conv1, i64* @glob, align 8
76  ret void
77}
78
79define void @test_llneull_sext_store(i64 %a, i64 %b) {
80; CHECK-LABEL: test_llneull_sext_store:
81; CHECK:       # BB#0: # %entry
82; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
83; CHECK-NEXT:    xor r3, r3, r4
84; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
85; CHECK-NEXT:    subfic r3, r3, 0
86; CHECK-NEXT:    subfe r3, r3, r3
87; CHECK-NEXT:    std r3, 0(r12)
88; CHECK-NEXT:    blr
89entry:
90  %cmp = icmp ne i64 %a, %b
91  %conv1 = sext i1 %cmp to i64
92  store i64 %conv1, i64* @glob, align 8
93  ret void
94}
95
96define void @test_llneull_z_store(i64 %a) {
97; CHECK-LABEL: test_llneull_z_store:
98; CHECK:       # BB#0: # %entry
99; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
100; CHECK-NEXT:    addic r5, r3, -1
101; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
102; CHECK-NEXT:    subfe r3, r5, r3
103; CHECK-NEXT:    std r3, 0(r4)
104; CHECK-NEXT:    blr
105entry:
106  %cmp = icmp ne i64 %a, 0
107  %conv1 = zext i1 %cmp to i64
108  store i64 %conv1, i64* @glob, align 8
109  ret void
110}
111
112define void @test_llneull_sext_z_store(i64 %a) {
113; CHECK-LABEL: test_llneull_sext_z_store:
114; CHECK:       # BB#0: # %entry
115; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
116; CHECK-NEXT:    subfic r3, r3, 0
117; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
118; CHECK-NEXT:    subfe r3, r3, r3
119; CHECK-NEXT:    std r3, 0(r4)
120; CHECK-NEXT:    blr
121entry:
122  %cmp = icmp ne i64 %a, 0
123  %conv1 = sext i1 %cmp to i64
124  store i64 %conv1, i64* @glob, align 8
125  ret void
126}
127