1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = common local_unnamed_addr global i32 0, align 4
10
11; Function Attrs: norecurse nounwind readnone
12define i64 @test_llltui(i32 zeroext %a, i32 zeroext %b) {
13; CHECK-LABEL: test_llltui:
14; CHECK:       # BB#0: # %entry
15; CHECK-NOT:     clrldi
16; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
17; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
18; CHECK-NEXT:    blr
19entry:
20  %cmp = icmp ult i32 %a, %b
21  %conv1 = zext i1 %cmp to i64
22  ret i64 %conv1
23}
24
25; Function Attrs: norecurse nounwind readnone
26define i64 @test_llltui_sext(i32 zeroext %a, i32 zeroext %b) {
27; CHECK-LABEL: test_llltui_sext:
28; CHECK:       # BB#0: # %entry
29; CHECK-NEXT:    sub [[REG:r[0-9]+]], r3, r4
30; CHECK-NEXT:    sradi r3, [[REG]], 63
31; CHECK-NEXT:    blr
32entry:
33  %cmp = icmp ult i32 %a, %b
34  %conv1 = sext i1 %cmp to i64
35  ret i64 %conv1
36}
37
38; Function Attrs: norecurse nounwind readnone
39define i64 @test_llltui_z(i32 zeroext %a) {
40; CHECK-LABEL: test_llltui_z:
41; CHECK:       # BB#0: # %entry
42; CHECK-NEXT:    li r3, 0
43; CHECK-NEXT:    blr
44entry:
45  ret i64 0
46}
47
48; Function Attrs: norecurse nounwind readnone
49define i64 @test_llltui_sext_z(i32 zeroext %a) {
50; CHECK-LABEL: test_llltui_sext_z:
51; CHECK:       # BB#0: # %entry
52; CHECK-NEXT:    li r3, 0
53; CHECK-NEXT:    blr
54entry:
55  ret i64 0
56}
57
58; Function Attrs: norecurse nounwind
59define void @test_llltui_store(i32 zeroext %a, i32 zeroext %b) {
60; CHECK-LABEL: test_llltui_store:
61; CHECK:       # BB#0: # %entry
62; CHECK-NOT:     clrldi
63; CHECK:         sub [[REG:r[2-9]+]], r3, r4
64; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
65entry:
66  %cmp = icmp ult i32 %a, %b
67  %conv = zext i1 %cmp to i32
68  store i32 %conv, i32* @glob, align 4
69  ret void
70}
71
72; Function Attrs: norecurse nounwind
73define void @test_llltui_sext_store(i32 zeroext %a, i32 zeroext %b) {
74; CHECK-LABEL: test_llltui_sext_store:
75; CHECK:       # BB#0: # %entry
76; CHECK-NOT:     clrldi
77; CHECK:         sub [[REG:r[0-9]+]], r3, r4
78; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
79entry:
80  %cmp = icmp ult i32 %a, %b
81  %sub = sext i1 %cmp to i32
82  store i32 %sub, i32* @glob, align 4
83  ret void
84}
85
86; Function Attrs: norecurse nounwind
87define void @test_llltui_z_store(i32 zeroext %a) {
88; CHECK-LABEL: test_llltui_z_store:
89; CHECK:       # BB#0: # %entry
90; CHECK:         li [[REG:r[0-9]+]], 0
91; CHECK:         stw [[REG]], 0(r3)
92; CHECK-NEXT:    blr
93entry:
94  store i32 0, i32* @glob, align 4
95  ret void
96}
97
98; Function Attrs: norecurse nounwind
99define void @test_llltui_sext_z_store(i32 zeroext %a) {
100; CHECK-LABEL: test_llltui_sext_z_store:
101; CHECK:       # BB#0: # %entry
102; CHECK:         li [[REG:r[0-9]+]], 0
103; CHECK:         stw [[REG]], 0(r3)
104; CHECK-NEXT:    blr
105entry:
106  store i32 0, i32* @glob, align 4
107  ret void
108}
109
110