1; XFAIL: * 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = common local_unnamed_addr global i8 0, align 1 10 11; Function Attrs: norecurse nounwind readnone 12define i64 @test_llltuc(i8 zeroext %a, i8 zeroext %b) { 13; CHECK-LABEL: test_llltuc: 14; CHECK: # BB#0: # %entry 15; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 16; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 17; CHECK-NEXT: blr 18entry: 19 %cmp = icmp ult i8 %a, %b 20 %conv3 = zext i1 %cmp to i64 21 ret i64 %conv3 22} 23 24; Function Attrs: norecurse nounwind readnone 25define i64 @test_llltuc_sext(i8 zeroext %a, i8 zeroext %b) { 26; CHECK-LABEL: test_llltuc_sext: 27; CHECK: # BB#0: # %entry 28; CHECK-NEXT: sub [[REG:r[0-9]+]], r3, r4 29; CHECK-NEXT: sradi r3, [[REG]], 63 30; CHECK-NEXT: blr 31entry: 32 %cmp = icmp ult i8 %a, %b 33 %conv3 = sext i1 %cmp to i64 34 ret i64 %conv3 35} 36 37; Function Attrs: norecurse nounwind 38define void @test_llltuc_store(i8 zeroext %a, i8 zeroext %b) { 39; CHECK-LABEL: test_llltuc_store: 40; CHECK: # BB#0: # %entry 41; CHECK: sub [[REG:r[2-9]+]], r3, r4 42; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 43entry: 44 %cmp = icmp ult i8 %a, %b 45 %conv3 = zext i1 %cmp to i8 46 store i8 %conv3, i8* @glob, align 1 47 ret void 48} 49 50; Function Attrs: norecurse nounwind 51define void @test_llltuc_sext_store(i8 zeroext %a, i8 zeroext %b) { 52; CHECK-LABEL: test_llltuc_sext_store: 53; CHECK: # BB#0: # %entry 54; CHECK: sub [[REG:r[0-9]+]], r3, r4 55; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 56entry: 57 %cmp = icmp ult i8 %a, %b 58 %conv3 = sext i1 %cmp to i8 59 store i8 %conv3, i8* @glob, align 1 60 ret void 61} 62