1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6; RUN:   --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8
9@glob = common local_unnamed_addr global i16 0, align 2
10
11define i64 @test_llless(i16 signext %a, i16 signext %b)  {
12; CHECK-LABEL: test_llless:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    sub r3, r4, r3
15; CHECK-NEXT:    rldicl r3, r3, 1, 63
16; CHECK-NEXT:    xori r3, r3, 1
17; CHECK-NEXT:    blr
18entry:
19  %cmp = icmp sle i16 %a, %b
20  %conv3 = zext i1 %cmp to i64
21  ret i64 %conv3
22}
23
24define i64 @test_llless_sext(i16 signext %a, i16 signext %b)  {
25; CHECK-LABEL: test_llless_sext:
26; CHECK:       # %bb.0: # %entry
27; CHECK-NEXT:    sub r3, r4, r3
28; CHECK-NEXT:    rldicl r3, r3, 1, 63
29; CHECK-NEXT:    addi r3, r3, -1
30; CHECK-NEXT:    blr
31entry:
32  %cmp = icmp sle i16 %a, %b
33  %conv3 = sext i1 %cmp to i64
34  ret i64 %conv3
35}
36
37define void @test_llless_store(i16 signext %a, i16 signext %b) {
38; CHECK-LABEL: test_llless_store:
39; CHECK:       # %bb.0: # %entry
40; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
41; CHECK-NEXT:    sub r3, r4, r3
42; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
43; CHECK-NEXT:    rldicl r3, r3, 1, 63
44; CHECK-NEXT:    xori r3, r3, 1
45; CHECK-NEXT:    sth r3, 0(r12)
46; CHECK-NEXT:    blr
47entry:
48  %cmp = icmp sle i16 %a, %b
49  %conv3 = zext i1 %cmp to i16
50  store i16 %conv3, i16* @glob, align 2
51  ret void
52}
53
54define void @test_llless_sext_store(i16 signext %a, i16 signext %b) {
55; CHECK-LABEL: test_llless_sext_store:
56; CHECK:       # %bb.0: # %entry
57; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
58; CHECK-NEXT:    sub r3, r4, r3
59; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
60; CHECK-NEXT:    rldicl r3, r3, 1, 63
61; CHECK-NEXT:    addi r3, r3, -1
62; CHECK-NEXT:    sth r3, 0(r12)
63; CHECK-NEXT:    blr
64entry:
65  %cmp = icmp sle i16 %a, %b
66  %conv3 = sext i1 %cmp to i16
67  store i16 %conv3, i16* @glob, align 2
68  ret void
69}
70