1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8@glob = common local_unnamed_addr global i64 0, align 8
9
10; Function Attrs: norecurse nounwind readnone
11define i64 @test_lllesll(i64 %a, i64 %b)  {
12; CHECK-LABEL: test_lllesll:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    sradi r5, r4, 63
15; CHECK-NEXT:    rldicl r6, r3, 1, 63
16; CHECK-NEXT:    subfc r12, r3, r4
17; CHECK-NEXT:    adde r3, r5, r6
18; CHECK-NEXT:    blr
19entry:
20  %cmp = icmp sle i64 %a, %b
21  %conv1 = zext i1 %cmp to i64
22  ret i64 %conv1
23}
24
25; Function Attrs: norecurse nounwind readnone
26define i64 @test_lllesll_sext(i64 %a, i64 %b)  {
27; CHECK-LABEL: test_lllesll_sext:
28; CHECK:       # %bb.0: # %entry
29; CHECK-NEXT:    sradi r5, r4, 63
30; CHECK-NEXT:    rldicl r6, r3, 1, 63
31; CHECK-NEXT:    subfc r12, r3, r4
32; CHECK-NEXT:    adde r3, r5, r6
33; CHECK-NEXT:    neg r3, r3
34; CHECK-NEXT:    blr
35entry:
36  %cmp = icmp sle i64 %a, %b
37  %conv1 = sext i1 %cmp to i64
38  ret i64 %conv1
39}
40
41; Function Attrs: norecurse nounwind readnone
42define i64 @test_lllesll_z(i64 %a)  {
43; CHECK-LABEL: test_lllesll_z:
44; CHECK:       # %bb.0: # %entry
45; CHECK-NEXT:    addi r4, r3, -1
46; CHECK-NEXT:    or r3, r4, r3
47; CHECK-NEXT:    rldicl r3, r3, 1, 63
48; CHECK-NEXT:    blr
49entry:
50  %cmp = icmp slt i64 %a, 1
51  %conv1 = zext i1 %cmp to i64
52  ret i64 %conv1
53}
54
55; Function Attrs: norecurse nounwind readnone
56define i64 @test_lllesll_sext_z(i64 %a)  {
57; CHECK-LABEL: test_lllesll_sext_z:
58; CHECK:       # %bb.0: # %entry
59; CHECK-NEXT:    addi r4, r3, -1
60; CHECK-NEXT:    or r3, r4, r3
61; CHECK-NEXT:    sradi r3, r3, 63
62; CHECK-NEXT:    blr
63entry:
64  %cmp = icmp slt i64 %a, 1
65  %conv1 = sext i1 %cmp to i64
66  ret i64 %conv1
67}
68
69; Function Attrs: norecurse nounwind
70define void @test_lllesll_store(i64 %a, i64 %b) {
71; CHECK-LABEL: test_lllesll_store:
72; CHECK:       # %bb.0: # %entry
73; CHECK:    sradi r6, r4, 63
74; CHECK:    subfc r4, r3, r4
75; CHECK:    rldicl r3, r3, 1, 63
76; CHECK:    adde r3, r6, r3
77; CHECK:    std r3,
78; CHECK-NEXT:    blr
79entry:
80  %cmp = icmp sle i64 %a, %b
81  %conv1 = zext i1 %cmp to i64
82  store i64 %conv1, i64* @glob, align 8
83  ret void
84}
85
86; Function Attrs: norecurse nounwind
87define void @test_lllesll_sext_store(i64 %a, i64 %b) {
88; CHECK-LABEL: test_lllesll_sext_store:
89; CHECK:       # %bb.0: # %entry
90; CHECK:    sradi r6, r4, 63
91; CHECK-DAG:    rldicl r3, r3, 1, 63
92; CHECK-DAG:    subfc r4, r3, r4
93; CHECK:    adde r3, r6, r3
94; CHECK:    neg r3, r3
95; CHECK:    std r3, 0(r4)
96; CHECK-NEXT:    blr
97entry:
98  %cmp = icmp sle i64 %a, %b
99  %conv1 = sext i1 %cmp to i64
100  store i64 %conv1, i64* @glob, align 8
101  ret void
102}
103
104; Function Attrs: norecurse nounwind
105define void @test_lllesll_z_store(i64 %a) {
106; CHECK-LABEL: test_lllesll_z_store:
107; CHECK:       # %bb.0: # %entry
108; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
109; CHECK-NEXT:    addi r5, r3, -1
110; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
111; CHECK-NEXT:    or r3, r5, r3
112; CHECK-NEXT:    rldicl r3, r3, 1, 63
113; CHECK-NEXT:    std r3, 0(r4)
114; CHECK-NEXT:    blr
115entry:
116  %cmp = icmp slt i64 %a, 1
117  %conv1 = zext i1 %cmp to i64
118  store i64 %conv1, i64* @glob, align 8
119  ret void
120}
121
122; Function Attrs: norecurse nounwind
123define void @test_lllesll_sext_z_store(i64 %a) {
124; CHECK-LABEL: test_lllesll_sext_z_store:
125; CHECK:       # %bb.0: # %entry
126; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
127; CHECK-NEXT:    addi r5, r3, -1
128; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
129; CHECK-NEXT:    or r3, r5, r3
130; CHECK-NEXT:    sradi r3, r3, 63
131; CHECK-NEXT:    std r3, 0(r4)
132; CHECK-NEXT:    blr
133entry:
134  %cmp = icmp slt i64 %a, 1
135  %conv1 = sext i1 %cmp to i64
136  store i64 %conv1, i64* @glob, align 8
137  ret void
138}
139