1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
9@glob = common local_unnamed_addr global i64 0, align 8
10
11; Function Attrs: norecurse nounwind readnone
12define i64 @test_lllesll(i64 %a, i64 %b)  {
13; CHECK-LABEL: test_lllesll:
14; CHECK:       # BB#0: # %entry
15; CHECK-NEXT:    sradi r5, r4, 63
16; CHECK-NEXT:    rldicl r6, r3, 1, 63
17; CHECK-NEXT:    subfc r12, r3, r4
18; CHECK-NEXT:    adde r3, r5, r6
19; CHECK-NEXT:    blr
20entry:
21  %cmp = icmp sle i64 %a, %b
22  %conv1 = zext i1 %cmp to i64
23  ret i64 %conv1
24}
25
26; Function Attrs: norecurse nounwind readnone
27define i64 @test_lllesll_sext(i64 %a, i64 %b)  {
28; CHECK-LABEL: test_lllesll_sext:
29; CHECK:       # BB#0: # %entry
30; CHECK-NEXT:    sradi r5, r4, 63
31; CHECK-NEXT:    rldicl r6, r3, 1, 63
32; CHECK-NEXT:    subfc r12, r3, r4
33; CHECK-NEXT:    adde r3, r5, r6
34; CHECK-NEXT:    neg r3, r3
35; CHECK-NEXT:    blr
36entry:
37  %cmp = icmp sle i64 %a, %b
38  %conv1 = sext i1 %cmp to i64
39  ret i64 %conv1
40}
41
42; Function Attrs: norecurse nounwind readnone
43define i64 @test_lllesll_z(i64 %a)  {
44; CHECK-LABEL: test_lllesll_z:
45; CHECK:       # BB#0: # %entry
46; CHECK-NEXT:    addi r4, r3, -1
47; CHECK-NEXT:    or r3, r4, r3
48; CHECK-NEXT:    rldicl r3, r3, 1, 63
49; CHECK-NEXT:    blr
50entry:
51  %cmp = icmp slt i64 %a, 1
52  %conv1 = zext i1 %cmp to i64
53  ret i64 %conv1
54}
55
56; Function Attrs: norecurse nounwind readnone
57define i64 @test_lllesll_sext_z(i64 %a)  {
58; CHECK-LABEL: test_lllesll_sext_z:
59; CHECK:       # BB#0: # %entry
60; CHECK-NEXT:    addi r4, r3, -1
61; CHECK-NEXT:    or r3, r4, r3
62; CHECK-NEXT:    sradi r3, r3, 63
63; CHECK-NEXT:    blr
64entry:
65  %cmp = icmp slt i64 %a, 1
66  %conv1 = sext i1 %cmp to i64
67  ret i64 %conv1
68}
69
70; Function Attrs: norecurse nounwind
71define void @test_lllesll_store(i64 %a, i64 %b) {
72; CHECK-LABEL: test_lllesll_store:
73; CHECK:       # BB#0: # %entry
74; CHECK:    sradi r6, r4, 63
75; CHECK:    subfc r4, r3, r4
76; CHECK:    rldicl r3, r3, 1, 63
77; CHECK:    adde r3, r6, r3
78; CHECK:    std r3,
79; CHECK-NEXT:    blr
80entry:
81  %cmp = icmp sle i64 %a, %b
82  %conv1 = zext i1 %cmp to i64
83  store i64 %conv1, i64* @glob, align 8
84  ret void
85}
86
87; Function Attrs: norecurse nounwind
88define void @test_lllesll_sext_store(i64 %a, i64 %b) {
89; CHECK-LABEL: test_lllesll_sext_store:
90; CHECK:       # BB#0: # %entry
91; CHECK:    sradi r6, r4, 63
92; CHECK-DAG:    rldicl r3, r3, 1, 63
93; CHECK-DAG:    subfc r4, r3, r4
94; CHECK:    adde r3, r6, r3
95; CHECK:    neg r3, r3
96; CHECK:    std r3, 0(r4)
97; CHECK-NEXT:    blr
98entry:
99  %cmp = icmp sle i64 %a, %b
100  %conv1 = sext i1 %cmp to i64
101  store i64 %conv1, i64* @glob, align 8
102  ret void
103}
104
105; Function Attrs: norecurse nounwind
106define void @test_lllesll_z_store(i64 %a) {
107; CHECK-LABEL: test_lllesll_z_store:
108; CHECK:       # BB#0: # %entry
109; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
110; CHECK-NEXT:    addi r5, r3, -1
111; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
112; CHECK-NEXT:    or r3, r5, r3
113; CHECK-NEXT:    rldicl r3, r3, 1, 63
114; CHECK-NEXT:    std r3, 0(r4)
115; CHECK-NEXT:    blr
116entry:
117  %cmp = icmp slt i64 %a, 1
118  %conv1 = zext i1 %cmp to i64
119  store i64 %conv1, i64* @glob, align 8
120  ret void
121}
122
123; Function Attrs: norecurse nounwind
124define void @test_lllesll_sext_z_store(i64 %a) {
125; CHECK-LABEL: test_lllesll_sext_z_store:
126; CHECK:       # BB#0: # %entry
127; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
128; CHECK-NEXT:    addi r5, r3, -1
129; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
130; CHECK-NEXT:    or r3, r5, r3
131; CHECK-NEXT:    sradi r3, r3, 63
132; CHECK-NEXT:    std r3, 0(r4)
133; CHECK-NEXT:    blr
134entry:
135  %cmp = icmp slt i64 %a, 1
136  %conv1 = sext i1 %cmp to i64
137  store i64 %conv1, i64* @glob, align 8
138  ret void
139}
140