1; XFAIL: * 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = common local_unnamed_addr global i16 0, align 2 10 11; Function Attrs: norecurse nounwind readnone 12define i64 @test_llgtus(i16 zeroext %a, i16 zeroext %b) { 13; CHECK-LABEL: test_llgtus: 14; CHECK: # BB#0: # %entry 15; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 16; CHECK-NEXT: rldicl r3, [[REG]], 1, 63 17; CHECK-NEXT: blr 18entry: 19 %cmp = icmp ugt i16 %a, %b 20 %conv3 = zext i1 %cmp to i64 21 ret i64 %conv3 22} 23 24; Function Attrs: norecurse nounwind readnone 25define i64 @test_llgtus_sext(i16 zeroext %a, i16 zeroext %b) { 26; CHECK-LABEL: test_llgtus_sext: 27; CHECK: # BB#0: # %entry 28; CHECK-NEXT: sub [[REG:r[0-9]+]], r4, r3 29; CHECK-NEXT: sradi r3, [[REG]], 63 30; CHECK-NEXT: blr 31entry: 32 %cmp = icmp ugt i16 %a, %b 33 %conv3 = sext i1 %cmp to i64 34 ret i64 %conv3 35} 36 37; Function Attrs: norecurse nounwind readnone 38define i64 @test_llgtus_z(i16 zeroext %a) { 39; CHECK-LABEL: test_llgtus_z: 40; CHECK: # BB#0: # %entry 41; CHECK-NEXT: cntlzw r3, r3 42; CHECK-NEXT: srwi r3, r3, 5 43; CHECK-NEXT: xori r3, r3, 1 44; CHECK-NEXT: blr 45entry: 46 %cmp = icmp ne i16 %a, 0 47 %conv2 = zext i1 %cmp to i64 48 ret i64 %conv2 49} 50 51; Function Attrs: norecurse nounwind readnone 52define i64 @test_llgtus_sext_z(i16 zeroext %a) { 53; CHECK-LABEL: test_llgtus_sext_z: 54; CHECK: # BB#0: # %entry 55; CHECK-NEXT: cntlzw r3, r3 56; CHECK-NEXT: srwi r3, r3, 5 57; CHECK-NEXT: xori r3, r3, 1 58; CHECK-NEXT: neg r3, r3 59; CHECK-NEXT: blr 60entry: 61 %cmp = icmp ne i16 %a, 0 62 %conv2 = sext i1 %cmp to i64 63 ret i64 %conv2 64} 65 66; Function Attrs: norecurse nounwind 67define void @test_llgtus_store(i16 zeroext %a, i16 zeroext %b) { 68; CHECK-LABEL: test_llgtus_store: 69; CHECK: # BB#0: # %entry 70; CHECK: sub [[REG:r[0-9]+]], r4, r3 71; CHECK: rldicl {{r[0-9]+}}, [[REG]], 1, 63 72entry: 73 %cmp = icmp ugt i16 %a, %b 74 %conv3 = zext i1 %cmp to i16 75 store i16 %conv3, i16* @glob, align 2 76 ret void 77} 78 79; Function Attrs: norecurse nounwind 80define void @test_llgtus_sext_store(i16 zeroext %a, i16 zeroext %b) { 81; CHECK-LABEL: test_llgtus_sext_store: 82; CHECK: # BB#0: # %entry 83; CHECK: sub [[REG:r[0-9]+]], r4, r3 84; CHECK: sradi {{r[0-9]+}}, [[REG]], 63 85entry: 86 %cmp = icmp ugt i16 %a, %b 87 %conv3 = sext i1 %cmp to i16 88 store i16 %conv3, i16* @glob, align 2 89 ret void 90} 91 92; Function Attrs: norecurse nounwind 93define void @test_llgtus_z_store(i16 zeroext %a) { 94; CHECK-LABEL: test_llgtus_z_store: 95; CHECK: # BB#0: # %entry 96; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 97; CHECK-NEXT: cntlzw r3, r3 98; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 99; CHECK-NEXT: srwi r3, r3, 5 100; CHECK-NEXT: xori r3, r3, 1 101; CHECK-NEXT: sth r3, 0(r4) 102; CHECK-NEXT: blr 103entry: 104 %cmp = icmp ne i16 %a, 0 105 %conv2 = zext i1 %cmp to i16 106 store i16 %conv2, i16* @glob, align 2 107 ret void 108} 109 110; Function Attrs: norecurse nounwind 111define void @test_llgtus_sext_z_store(i16 zeroext %a) { 112; CHECK-LABEL: test_llgtus_sext_z_store: 113; CHECK: # BB#0: # %entry 114; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 115; CHECK-NEXT: cntlzw r3, r3 116; CHECK-NEXT: srwi r3, r3, 5 117; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 118; CHECK-NEXT: xori r3, r3, 1 119; CHECK-NEXT: neg r3, r3 120; CHECK-NEXT: sth r3, 0(r4) 121; CHECK-NEXT: blr 122entry: 123 %cmp = icmp ne i16 %a, 0 124 %conv2 = sext i1 %cmp to i16 125 store i16 %conv2, i16* @glob, align 2 126 ret void 127} 128 129