1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = common local_unnamed_addr global i32 0, align 4
10
11; Function Attrs: norecurse nounwind readnone
12define i64 @test_llgeui(i32 zeroext %a, i32 zeroext %b) {
13entry:
14  %cmp = icmp uge i32 %a, %b
15  %conv1 = zext i1 %cmp to i64
16  ret i64 %conv1
17; CHECK-LABEL: test_llgeui:
18; CHECK: sub [[REG1:r[0-9]+]], r3, r4
19; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
20; CHECK-NEXT: xori r3, [[REG2]], 1
21; CHECK: blr
22}
23
24; Function Attrs: norecurse nounwind readnone
25define i64 @test_llgeui_sext(i32 zeroext %a, i32 zeroext %b) {
26entry:
27  %cmp = icmp uge i32 %a, %b
28  %conv1 = sext i1 %cmp to i64
29  ret i64 %conv1
30; CHECK-LABEL: @test_llgeui_sext
31; CHECK: sub [[REG1:r[0-9]+]], r3, r4
32; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
33; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
34; CHECK-NEXT: blr
35}
36
37; Function Attrs: norecurse nounwind readnone
38define i64 @test_llgeui_z(i32 zeroext %a) {
39entry:
40  %cmp = icmp uge i32 %a, 0
41  %conv1 = zext i1 %cmp to i64
42  ret i64 %conv1
43; CHECK-LABEL: @test_llgeui_z
44; CHECK: li r3, 1
45; CHECK: blr
46}
47
48; Function Attrs: norecurse nounwind readnone
49define i64 @test_llgeui_sext_z(i32 zeroext %a) {
50entry:
51  %cmp = icmp uge i32 %a, 0
52  %conv1 = sext i1 %cmp to i64
53  ret i64 %conv1
54; CHECK-LABEL: @test_llgeui_sext_z
55; CHECK: li r3, -1
56; CHECK-NEXT: blr
57}
58
59; Function Attrs: norecurse nounwind
60define void @test_llgeui_store(i32 zeroext %a, i32 zeroext %b) {
61entry:
62  %cmp = icmp uge i32 %a, %b
63  %conv = zext i1 %cmp to i32
64  store i32 %conv, i32* @glob
65  ret void
66; CHECK_LABEL: test_igeuc_store:
67; CHECK: sub [[REG1:r[0-9]+]], r3, r4
68; CHECK: rldicl [[REG2:r[0-9]+]], [[REG2]], 1, 63
69; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
70; CHECK: blr
71}
72
73; Function Attrs: norecurse nounwind
74define void @test_llgeui_sext_store(i32 zeroext %a, i32 zeroext %b) {
75entry:
76  %cmp = icmp uge i32 %a, %b
77  %sub = sext i1 %cmp to i32
78  store i32 %sub, i32* @glob
79  ret void
80; CHECK-LABEL: @test_llgeui_sext_store
81; CHECK: sub [[REG1:r[0-9]+]], r3, r4
82; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
83; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
84; CHECK: stw  [[REG3]]
85; CHECK: blr
86}
87
88; Function Attrs: norecurse nounwind
89define void @test_llgeui_z_store(i32 zeroext %a) {
90entry:
91  %cmp = icmp uge i32 %a, 0
92  %sub = zext i1 %cmp to i32
93  store i32 %sub, i32* @glob
94  ret void
95; CHECK-LABEL: @test_llgeui_z_store
96; CHECK: li [[REG1:r[0-9]+]], 1
97; CHECK: stw [[REG1]]
98; CHECK: blr
99}
100
101; Function Attrs: norecurse nounwind
102define void @test_llgeui_sext_z_store(i32 zeroext %a) {
103entry:
104  %cmp = icmp uge i32 %a, 0
105  %sub = sext i1 %cmp to i32
106  store i32 %sub, i32* @glob
107  ret void
108; CHECK-LABEL: @test_llgeui_sext_z_store
109; CHECK: li [[REG1:r[0-9]+]], -1
110; CHECK: stw [[REG1]]
111; CHECK: blr
112}
113
114