1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
9@glob = common local_unnamed_addr global i64 0, align 8
10
11define i64 @test_llgesll(i64 %a, i64 %b) {
12; CHECK-LABEL: test_llgesll:
13; CHECK:       # BB#0: # %entry
14; CHECK-NEXT:    sradi r5, r3, 63
15; CHECK-NEXT:    rldicl r6, r4, 1, 63
16; CHECK-NEXT:    subfc r3, r4, r3
17; CHECK-NEXT:    adde r3, r5, r6
18; CHECK-NEXT:    blr
19entry:
20  %cmp = icmp sge i64 %a, %b
21  %conv1 = zext i1 %cmp to i64
22  ret i64 %conv1
23}
24
25define i64 @test_llgesll_sext(i64 %a, i64 %b) {
26; CHECK-LABEL: test_llgesll_sext:
27; CHECK:       # BB#0: # %entry
28; CHECK-NEXT:    sradi r5, r3, 63
29; CHECK-NEXT:    rldicl r6, r4, 1, 63
30; CHECK-NEXT:    subfc r3, r4, r3
31; CHECK-NEXT:    adde r3, r5, r6
32; CHECK-NEXT:    neg r3, r3
33; CHECK-NEXT:    blr
34entry:
35  %cmp = icmp sge i64 %a, %b
36  %conv1 = sext i1 %cmp to i64
37  ret i64 %conv1
38}
39
40define i64 @test_llgesll_z(i64 %a) {
41; CHECK-LABEL: test_llgesll_z:
42; CHECK:       # BB#0: # %entry
43; CHECK-NEXT:    rldicl r3, r3, 1, 63
44; CHECK-NEXT:    xori r3, r3, 1
45; CHECK-NEXT:    blr
46entry:
47  %cmp = icmp sgt i64 %a, -1
48  %conv1 = zext i1 %cmp to i64
49  ret i64 %conv1
50}
51
52define i64 @test_llgesll_sext_z(i64 %a) {
53; CHECK-LABEL: test_llgesll_sext_z:
54; CHECK:       # BB#0: # %entry
55; CHECK-NEXT:    sradi r3, r3, 63
56; CHECK-NEXT:    not r3, r3
57; CHECK-NEXT:    blr
58entry:
59  %cmp = icmp sgt i64 %a, -1
60  %conv1 = sext i1 %cmp to i64
61  ret i64 %conv1
62}
63
64define void @test_llgesll_store(i64 %a, i64 %b) {
65; CHECK-LABEL: test_llgesll_store:
66; CHECK:       # BB#0: # %entry
67; CHECK:    sradi r6, r3, 63
68; CHECK:    subfc r3, r4, r3
69; CHECK:    rldicl r3, r4, 1, 63
70; CHECK:    adde r3, r6, r3
71; CHECK:    std r3,
72; CHECK-NEXT:    blr
73entry:
74  %cmp = icmp sge i64 %a, %b
75  %conv1 = zext i1 %cmp to i64
76  store i64 %conv1, i64* @glob, align 8
77  ret void
78}
79
80define void @test_llgesll_sext_store(i64 %a, i64 %b) {
81; CHECK-LABEL: test_llgesll_sext_store:
82; CHECK:       # BB#0: # %entry
83; CHECK-NEXT:    sradi r6, r3, 63
84; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
85; CHECK-NEXT:    subfc r3, r4, r3
86; CHECK-NEXT:    rldicl r3, r4, 1, 63
87; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
88; CHECK-NEXT:    adde r3, r6, r3
89; CHECK-NEXT:    neg r3, r3
90; CHECK-NEXT:    std r3, 0(r4)
91; CHECK-NEXT:    blr
92entry:
93  %cmp = icmp sge i64 %a, %b
94  %conv1 = sext i1 %cmp to i64
95  store i64 %conv1, i64* @glob, align 8
96  ret void
97}
98
99define void @test_llgesll_z_store(i64 %a) {
100; CHECK-LABEL: test_llgesll_z_store:
101; CHECK:       # BB#0: # %entry
102; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
103; CHECK-NEXT:    rldicl r3, r3, 1, 63
104; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
105; CHECK-NEXT:    xori r3, r3, 1
106; CHECK-NEXT:    std r3, 0(r4)
107; CHECK-NEXT:    blr
108entry:
109  %cmp = icmp sgt i64 %a, -1
110  %conv1 = zext i1 %cmp to i64
111  store i64 %conv1, i64* @glob, align 8
112  ret void
113}
114
115define void @test_llgesll_sext_z_store(i64 %a) {
116; CHECK-LABEL: test_llgesll_sext_z_store:
117; CHECK:       # BB#0: # %entry
118; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
119; CHECK-NEXT:    sradi r3, r3, 63
120; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
121; CHECK-NEXT:    not r3, r3
122; CHECK-NEXT:    std r3, 0(r4)
123; CHECK-NEXT:    blr
124entry:
125  %cmp = icmp sgt i64 %a, -1
126  %conv1 = sext i1 %cmp to i64
127  store i64 %conv1, i64* @glob, align 8
128  ret void
129}
130