1; XFAIL: *
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
4; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
5; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
6; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
7; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
8; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
9
10@glob = common local_unnamed_addr global i32 0, align 4
11
12; Function Attrs: norecurse nounwind readnone
13define i64 @test_lleqsi(i32 signext %a, i32 signext %b) {
14; CHECK-LABEL: test_lleqsi:
15; CHECK:       # BB#0: # %entry
16; CHECK-NEXT:    xor r3, r3, r4
17; CHECK-NEXT:    cntlzw r3, r3
18; CHECK-NEXT:    srwi r3, r3, 5
19; CHECK-NEXT:    blr
20entry:
21  %cmp = icmp eq i32 %a, %b
22  %conv1 = zext i1 %cmp to i64
23  ret i64 %conv1
24}
25
26; Function Attrs: norecurse nounwind readnone
27define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) {
28; CHECK-LABEL: test_lleqsi_sext:
29; CHECK:       # BB#0: # %entry
30; CHECK-NEXT:    xor r3, r3, r4
31; CHECK-NEXT:    cntlzw r3, r3
32; CHECK-NEXT:    srwi r3, r3, 5
33; CHECK-NEXT:    neg r3, r3
34; CHECK-NEXT:    blr
35entry:
36  %cmp = icmp eq i32 %a, %b
37  %conv1 = sext i1 %cmp to i64
38  ret i64 %conv1
39}
40
41; Function Attrs: norecurse nounwind readnone
42define i64 @test_lleqsi_z(i32 signext %a) {
43; CHECK-LABEL: test_lleqsi_z:
44; CHECK:       # BB#0: # %entry
45; CHECK-NEXT:    cntlzw r3, r3
46; CHECK-NEXT:    srwi r3, r3, 5
47; CHECK-NEXT:    blr
48entry:
49  %cmp = icmp eq i32 %a, 0
50  %conv1 = zext i1 %cmp to i64
51  ret i64 %conv1
52}
53
54; Function Attrs: norecurse nounwind readnone
55define i64 @test_lleqsi_sext_z(i32 signext %a) {
56; CHECK-LABEL: test_lleqsi_sext_z:
57; CHECK:       # BB#0: # %entry
58; CHECK-NEXT:    cntlzw r3, r3
59; CHECK-NEXT:    srwi r3, r3, 5
60; CHECK-NEXT:    neg r3, r3
61; CHECK-NEXT:    blr
62entry:
63  %cmp = icmp eq i32 %a, 0
64  %conv1 = sext i1 %cmp to i64
65  ret i64 %conv1
66}
67
68; Function Attrs: norecurse nounwind
69define void @test_lleqsi_store(i32 signext %a, i32 signext %b) {
70; CHECK-LABEL: test_lleqsi_store:
71; CHECK:       # BB#0: # %entry
72; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
73; CHECK-NEXT:    xor r3, r3, r4
74; CHECK-NEXT:    ld r12, .LC0@toc@l(r5)
75; CHECK-NEXT:    cntlzw r3, r3
76; CHECK-NEXT:    srwi r3, r3, 5
77; CHECK-NEXT:    stw r3, 0(r12)
78; CHECK-NEXT:    blr
79entry:
80  %cmp = icmp eq i32 %a, %b
81  %conv = zext i1 %cmp to i32
82  store i32 %conv, i32* @glob, align 4
83  ret void
84}
85
86; Function Attrs: norecurse nounwind
87define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) {
88; CHECK-LABEL: test_lleqsi_sext_store:
89; CHECK:       # BB#0: # %entry
90; CHECK-NEXT:    xor r3, r3, r4
91; CHECK-NEXT:    addis r5, r2, .LC0@toc@ha
92; CHECK-NEXT:    cntlzw r3, r3
93; CHECK-NEXT:    ld r4, .LC0@toc@l(r5)
94; CHECK-NEXT:    srwi r3, r3, 5
95; CHECK-NEXT:    neg r3, r3
96; CHECK-NEXT:    stw r3, 0(r4)
97; CHECK-NEXT:    blr
98entry:
99  %cmp = icmp eq i32 %a, %b
100  %sub = sext i1 %cmp to i32
101  store i32 %sub, i32* @glob, align 4
102  ret void
103}
104
105; Function Attrs: norecurse nounwind
106define void @test_lleqsi_z_store(i32 signext %a) {
107; CHECK-LABEL: test_lleqsi_z_store:
108; CHECK:       # BB#0: # %entry
109; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
110; CHECK-NEXT:    cntlzw r3, r3
111; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
112; CHECK-NEXT:    srwi r3, r3, 5
113; CHECK-NEXT:    stw r3, 0(r4)
114; CHECK-NEXT:    blr
115; CHECKNEXT:    blr
116entry:
117  %cmp = icmp eq i32 %a, 0
118  %conv = zext i1 %cmp to i32
119  store i32 %conv, i32* @glob, align 4
120  ret void
121}
122
123; Function Attrs: norecurse nounwind
124define void @test_lleqsi_sext_z_store(i32 signext %a) {
125; CHECK-LABEL: test_lleqsi_sext_z_store:
126; CHECK:       # BB#0: # %entry
127; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
128; CHECK-NEXT:    cntlzw r3, r3
129; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
130; CHECK-NEXT:    srwi r3, r3, 5
131; CHECK-NEXT:    neg r3, r3
132; CHECK-NEXT:    stw r3, 0(r4)
133; CHECK-NEXT:    blr
134entry:
135  %cmp = icmp eq i32 %a, 0
136  %sub = sext i1 %cmp to i32
137  store i32 %sub, i32* @glob, align 4
138  ret void
139}
140