1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
9
10@glob = common local_unnamed_addr global i64 0, align 8
11
12; Function Attrs: norecurse nounwind readnone
13define signext i32 @test_iltsll(i64 %a, i64 %b) {
14; CHECK-LABEL: test_iltsll:
15; CHECK:       # BB#0: # %entry
16; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
17; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
18; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
19; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
20; CHECK-NEXT:    xori r3, [[REG4]], 1
21; CHECK-NEXT:    blr
22entry:
23  %cmp = icmp slt i64 %a, %b
24  %conv = zext i1 %cmp to i32
25  ret i32 %conv
26}
27
28; Function Attrs: norecurse nounwind readnone
29define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
30; CHECK-LABEL: test_iltsll_sext:
31; CHECK:       # BB#0: # %entry
32; CHECK-NEXT:    sradi [[REG1:r[0-9]+]], r3, 63
33; CHECK-NEXT:    rldicl [[REG2:r[0-9]+]], r4, 1, 63
34; CHECK-NEXT:    subfc [[REG3:r[0-9]+]], r4, r3
35; CHECK-NEXT:    adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
36; CHECK-NEXT:    xori [[REG5:r[0-9]+]], [[REG4]], 1
37; CHECK-NEXT:    neg r3, [[REG5]]
38; CHECK-NEXT:    blr
39entry:
40  %cmp = icmp slt i64 %a, %b
41  %sub = sext i1 %cmp to i32
42  ret i32 %sub
43}
44
45; Function Attrs: norecurse nounwind readnone
46define signext i32 @test_iltsll_sext_z(i64 %a) {
47; CHECK-LABEL: test_iltsll_sext_z:
48; CHECK:       # BB#0: # %entry
49; CHECK-NEXT:    sradi r3, r3, 63
50; CHECK-NEXT:    blr
51entry:
52  %cmp = icmp slt i64 %a, 0
53  %sub = sext i1 %cmp to i32
54  ret i32 %sub
55}
56
57; Function Attrs: norecurse nounwind
58define void @test_iltsll_store(i64 %a, i64 %b) {
59; CHECK-LABEL: test_iltsll_store:
60; CHECK:       # BB#0: # %entry
61; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
62; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
63; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
64; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
65; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
66; CHECK-NOT:     neg {{r[0-9]+}}, [[REG5]]
67entry:
68  %cmp = icmp slt i64 %a, %b
69  %conv1 = zext i1 %cmp to i64
70  store i64 %conv1, i64* @glob, align 8
71  ret void
72}
73
74; Function Attrs: norecurse nounwind
75define void @test_iltsll_sext_store(i64 %a, i64 %b) {
76; CHECK-LABEL: test_iltsll_sext_store:
77; CHECK:       # BB#0: # %entry
78; CHECK:         sradi [[REG1:r[0-9]+]], r3, 63
79; CHECK:         rldicl [[REG2:r[0-9]+]], r4, 1, 63
80; CHECK-DIAG:    subfc [[REG3:r[0-9]+]], r4, r3
81; CHECK:         adde [[REG4:r[0-9]+]], [[REG2]], [[REG1]]
82; CHECK:         xori [[REG5:r[0-9]+]], [[REG4]], 1
83; CHECK:         neg {{r[0-9]+}}, [[REG5]]
84entry:
85  %cmp = icmp slt i64 %a, %b
86  %conv1 = sext i1 %cmp to i64
87  store i64 %conv1, i64* @glob, align 8
88  ret void
89}
90
91; Function Attrs: norecurse nounwind
92define void @test_iltsll_sext_z_store(i64 %a) {
93; CHECK-LABEL: test_iltsll_sext_z_store:
94; CHECK:    sradi r3, r3, 63
95entry:
96  %cmp = icmp slt i64 %a, 0
97  %conv2 = sext i1 %cmp to i64
98  store i64 %conv2, i64* @glob, align 8
99  ret void
100}
101