1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8
9@glob = common local_unnamed_addr global i32 0, align 4
10
11; Function Attrs: norecurse nounwind readnone
12define signext i32 @test_ileui(i32 zeroext %a, i32 zeroext %b) {
13entry:
14  %cmp = icmp ule i32 %a, %b
15  %sub = zext i1 %cmp to i32
16  ret i32 %sub
17; CHECK-LABEL: test_ileui:
18; CHECK: sub [[REG1:r[0-9]+]], r4, r3
19; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
20; CHECK-NEXT: xori r3, [[REG2]], 1
21; CHECK: blr
22}
23
24; Function Attrs: norecurse nounwind readnone
25define signext i32 @test_ileui_sext(i32 zeroext %a, i32 zeroext %b) {
26entry:
27  %cmp = icmp ule i32 %a, %b
28  %sub = sext i1 %cmp to i32
29  ret i32 %sub
30; CHECK-LABEL: @test_ileui_sext
31; CHECK: sub [[REG1:r[0-9]+]], r4, r3
32; CHECK-NEXT: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
33; CHECK-NEXT: addi [[REG3:r[0-9]+]], [[REG2]], -1
34; CHECK-NEXT: blr
35}
36
37; Function Attrs: norecurse nounwind readnone
38define signext i32 @test_ileui_z(i32 zeroext %a) {
39entry:
40  %cmp = icmp eq i32 %a, 0
41  %sub = zext i1 %cmp to i32
42  ret i32 %sub
43; CHECK-LABEL: test_ileui_z:
44; CHECK: cntlzw [[REG1:r[0-9]+]], r3
45; CHECK: srwi r3, [[REG1]], 5
46; CHECK: blr
47}
48
49; Function Attrs: norecurse nounwind readnone
50define signext i32 @test_ileui_sext_z(i32 zeroext %a) {
51entry:
52  %cmp = icmp eq i32 %a, 0
53  %sub = sext i1 %cmp to i32
54  ret i32 %sub
55; CHECK-LABEL: @test_ileui_sext_z
56; CHECK: cntlzw [[REG1:r[0-9]+]], r3
57; CHECK-NEXT: srwi [[REG2:r[0-9]+]], [[REG1]], 5
58; CHECK-NEXT: neg r3, [[REG2]]
59; CHECK: blr
60}
61
62; Function Attrs: norecurse nounwind
63define void @test_ileui_store(i32 zeroext %a, i32 zeroext %b) {
64entry:
65  %cmp = icmp ule i32 %a, %b
66  %sub = zext i1 %cmp to i32
67  store i32 %sub, i32* @glob
68  ret void
69; CHECK-LABEL: test_ileui_store:
70; CHECK: sub [[REG1:r[0-9]+]], r4, r3
71; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
72; CHECK: xori {{r[0-9]+}}, [[REG2]], 1
73; CHECK: blr
74}
75
76; Function Attrs: norecurse nounwind
77define void @test_ileui_sext_store(i32 zeroext %a, i32 zeroext %b) {
78entry:
79  %cmp = icmp ule i32 %a, %b
80  %sub = sext i1 %cmp to i32
81  store i32 %sub, i32* @glob
82  ret void
83; CHECK-LABEL: @test_ileui_sext_store
84; CHECK: sub [[REG1:r[0-9]+]], r4, r3
85; CHECK: rldicl [[REG2:r[0-9]+]], [[REG1]], 1, 63
86; CHECK: addi [[REG3:r[0-9]+]], [[REG2]], -1
87; CHECK: stw  [[REG3]]
88; CHECK: blr
89}
90
91; Function Attrs: norecurse nounwind
92define void @test_ileui_z_store(i32 zeroext %a) {
93entry:
94  %cmp = icmp eq i32 %a, 0
95  %sub = zext i1 %cmp to i32
96  store i32 %sub, i32* @glob
97  ret void
98; CHECK-LABEL: test_ileui_z_store:
99; CHECK: cntlzw [[REG1:r[0-9]+]], r3
100; CHECK: srwi {{r[0-9]+}}, [[REG1]], 5
101; CHECK: blr
102}
103
104; Function Attrs: norecurse nounwind
105define void @test_ileui_sext_z_store(i32 zeroext %a) {
106entry:
107  %cmp = icmp eq i32 %a, 0
108  %sub = sext i1 %cmp to i32
109  store i32 %sub, i32* @glob
110  ret void
111; CHECK-LABEL: @test_ileui_sext_z_store
112; CHECK: cntlzw [[REG1:r[0-9]+]], r3
113; CHECK: srwi [[REG2:r[0-9]+]], [[REG1]], 5
114; CHECK: neg [[REG3:r[0-9]+]], [[REG2]]
115; CHECK: stw [[REG3]]
116; CHECK: blr
117}
118
119