1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
8@glob = common local_unnamed_addr global i64 0, align 8
9
10define signext i32 @test_ilesll(i64 %a, i64 %b) {
11; CHECK-LABEL: test_ilesll:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    sradi r5, r4, 63
14; CHECK-NEXT:    rldicl r6, r3, 1, 63
15; CHECK-NEXT:    subfc r12, r3, r4
16; CHECK-NEXT:    adde r3, r5, r6
17; CHECK-NEXT:    blr
18entry:
19  %cmp = icmp sle i64 %a, %b
20  %conv = zext i1 %cmp to i32
21  ret i32 %conv
22}
23
24define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
25; CHECK-LABEL: test_ilesll_sext:
26; CHECK:       # %bb.0: # %entry
27; CHECK-NEXT:    sradi r5, r4, 63
28; CHECK-NEXT:    rldicl r6, r3, 1, 63
29; CHECK-NEXT:    subfc r12, r3, r4
30; CHECK-NEXT:    adde r3, r5, r6
31; CHECK-NEXT:    neg r3, r3
32; CHECK-NEXT:    blr
33entry:
34  %cmp = icmp sle i64 %a, %b
35  %sub = sext i1 %cmp to i32
36  ret i32 %sub
37}
38
39define signext i32 @test_ilesll_z(i64 %a) {
40; CHECK-LABEL: test_ilesll_z:
41; CHECK:       # %bb.0: # %entry
42; CHECK-NEXT:    addi r4, r3, -1
43; CHECK-NEXT:    or r3, r4, r3
44; CHECK-NEXT:    rldicl r3, r3, 1, 63
45; CHECK-NEXT:    blr
46entry:
47  %cmp = icmp slt i64 %a, 1
48  %conv = zext i1 %cmp to i32
49  ret i32 %conv
50}
51
52define signext i32 @test_ilesll_sext_z(i64 %a) {
53; CHECK-LABEL: test_ilesll_sext_z:
54; CHECK:       # %bb.0: # %entry
55; CHECK-NEXT:    addi r4, r3, -1
56; CHECK-NEXT:    or r3, r4, r3
57; CHECK-NEXT:    sradi r3, r3, 63
58; CHECK-NEXT:    blr
59entry:
60  %cmp = icmp slt i64 %a, 1
61  %sub = sext i1 %cmp to i32
62  ret i32 %sub
63}
64
65define void @test_ilesll_store(i64 %a, i64 %b) {
66; CHECK-LABEL: test_ilesll_store:
67; CHECK:       # %bb.0: # %entry
68; CHECK:    sradi r6, r4, 63
69; CHECK:    subfc r4, r3, r4
70; CHECK:    rldicl r3, r3, 1, 63
71; CHECK:    adde r3, r6, r3
72; CHECK:    std r3,
73; CHECK-NEXT:    blr
74entry:
75  %cmp = icmp sle i64 %a, %b
76  %conv1 = zext i1 %cmp to i64
77  store i64 %conv1, i64* @glob, align 8
78  ret void
79}
80
81define void @test_ilesll_sext_store(i64 %a, i64 %b) {
82; CHECK-LABEL: test_ilesll_sext_store:
83; CHECK:       # %bb.0: # %entry
84; CHECK:    sradi r6, r4, 63
85; CHECK-DAG:    rldicl r3, r3, 1, 63
86; CHECK-DAG:    subfc r4, r3, r4
87; CHECK:    adde r3, r6, r3
88; CHECK:    neg r3, r3
89; CHECK:    std r3,
90; CHECK-NEXT:    blr
91entry:
92  %cmp = icmp sle i64 %a, %b
93  %conv1 = sext i1 %cmp to i64
94  store i64 %conv1, i64* @glob, align 8
95  ret void
96}
97
98define void @test_ilesll_z_store(i64 %a) {
99; CHECK-LABEL: test_ilesll_z_store:
100; CHECK:       # %bb.0: # %entry
101; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
102; CHECK-NEXT:    addi r5, r3, -1
103; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
104; CHECK-NEXT:    or r3, r5, r3
105; CHECK-NEXT:    rldicl r3, r3, 1, 63
106; CHECK-NEXT:    std r3, 0(r4)
107; CHECK-NEXT:    blr
108entry:
109  %cmp = icmp slt i64 %a, 1
110  %conv1 = zext i1 %cmp to i64
111  store i64 %conv1, i64* @glob, align 8
112  ret void
113}
114
115define void @test_ilesll_sext_z_store(i64 %a) {
116; CHECK-LABEL: test_ilesll_sext_z_store:
117; CHECK:       # %bb.0: # %entry
118; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
119; CHECK-NEXT:    addi r5, r3, -1
120; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
121; CHECK-NEXT:    or r3, r5, r3
122; CHECK-NEXT:    sradi r3, r3, 63
123; CHECK-NEXT:    std r3, 0(r4)
124; CHECK-NEXT:    blr
125entry:
126  %cmp = icmp slt i64 %a, 1
127  %conv1 = sext i1 %cmp to i64
128  store i64 %conv1, i64* @glob, align 8
129  ret void
130}
131