1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
9@glob = common local_unnamed_addr global i64 0, align 8
10
11define signext i32 @test_ilesll(i64 %a, i64 %b) {
12; CHECK-LABEL: test_ilesll:
13; CHECK:       # BB#0: # %entry
14; CHECK-NEXT:    sradi r5, r4, 63
15; CHECK-NEXT:    rldicl r6, r3, 1, 63
16; CHECK-NEXT:    subfc r12, r3, r4
17; CHECK-NEXT:    adde r3, r5, r6
18; CHECK-NEXT:    blr
19entry:
20  %cmp = icmp sle i64 %a, %b
21  %conv = zext i1 %cmp to i32
22  ret i32 %conv
23}
24
25define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
26; CHECK-LABEL: test_ilesll_sext:
27; CHECK:       # BB#0: # %entry
28; CHECK-NEXT:    sradi r5, r4, 63
29; CHECK-NEXT:    rldicl r6, r3, 1, 63
30; CHECK-NEXT:    subfc r12, r3, r4
31; CHECK-NEXT:    adde r3, r5, r6
32; CHECK-NEXT:    neg r3, r3
33; CHECK-NEXT:    blr
34entry:
35  %cmp = icmp sle i64 %a, %b
36  %sub = sext i1 %cmp to i32
37  ret i32 %sub
38}
39
40define signext i32 @test_ilesll_z(i64 %a) {
41; CHECK-LABEL: test_ilesll_z:
42; CHECK:       # BB#0: # %entry
43; CHECK-NEXT:    addi r4, r3, -1
44; CHECK-NEXT:    or r3, r4, r3
45; CHECK-NEXT:    rldicl r3, r3, 1, 63
46; CHECK-NEXT:    blr
47entry:
48  %cmp = icmp slt i64 %a, 1
49  %conv = zext i1 %cmp to i32
50  ret i32 %conv
51}
52
53define signext i32 @test_ilesll_sext_z(i64 %a) {
54; CHECK-LABEL: test_ilesll_sext_z:
55; CHECK:       # BB#0: # %entry
56; CHECK-NEXT:    addi r4, r3, -1
57; CHECK-NEXT:    or r3, r4, r3
58; CHECK-NEXT:    sradi r3, r3, 63
59; CHECK-NEXT:    blr
60entry:
61  %cmp = icmp slt i64 %a, 1
62  %sub = sext i1 %cmp to i32
63  ret i32 %sub
64}
65
66define void @test_ilesll_store(i64 %a, i64 %b) {
67; CHECK-LABEL: test_ilesll_store:
68; CHECK:       # BB#0: # %entry
69; CHECK:    sradi r6, r4, 63
70; CHECK:    subfc r4, r3, r4
71; CHECK:    rldicl r3, r3, 1, 63
72; CHECK:    adde r3, r6, r3
73; CHECK:    std r3,
74; CHECK-NEXT:    blr
75entry:
76  %cmp = icmp sle i64 %a, %b
77  %conv1 = zext i1 %cmp to i64
78  store i64 %conv1, i64* @glob, align 8
79  ret void
80}
81
82define void @test_ilesll_sext_store(i64 %a, i64 %b) {
83; CHECK-LABEL: test_ilesll_sext_store:
84; CHECK:       # BB#0: # %entry
85; CHECK:    sradi r6, r4, 63
86; CHECK-DAG:    rldicl r3, r3, 1, 63
87; CHECK-DAG:    subfc r4, r3, r4
88; CHECK:    adde r3, r6, r3
89; CHECK:    neg r3, r3
90; CHECK:    std r3,
91; CHECK-NEXT:    blr
92entry:
93  %cmp = icmp sle i64 %a, %b
94  %conv1 = sext i1 %cmp to i64
95  store i64 %conv1, i64* @glob, align 8
96  ret void
97}
98
99define void @test_ilesll_z_store(i64 %a) {
100; CHECK-LABEL: test_ilesll_z_store:
101; CHECK:       # BB#0: # %entry
102; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
103; CHECK-NEXT:    addi r5, r3, -1
104; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
105; CHECK-NEXT:    or r3, r5, r3
106; CHECK-NEXT:    rldicl r3, r3, 1, 63
107; CHECK-NEXT:    std r3, 0(r4)
108; CHECK-NEXT:    blr
109entry:
110  %cmp = icmp slt i64 %a, 1
111  %conv1 = zext i1 %cmp to i64
112  store i64 %conv1, i64* @glob, align 8
113  ret void
114}
115
116define void @test_ilesll_sext_z_store(i64 %a) {
117; CHECK-LABEL: test_ilesll_sext_z_store:
118; CHECK:       # BB#0: # %entry
119; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
120; CHECK-NEXT:    addi r5, r3, -1
121; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
122; CHECK-NEXT:    or r3, r5, r3
123; CHECK-NEXT:    sradi r3, r3, 63
124; CHECK-NEXT:    std r3, 0(r4)
125; CHECK-NEXT:    blr
126entry:
127  %cmp = icmp slt i64 %a, 1
128  %conv1 = sext i1 %cmp to i64
129  store i64 %conv1, i64* @glob, align 8
130  ret void
131}
132