1; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
2; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
3; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
4; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
5; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
6; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
7
8@glob = common local_unnamed_addr global i32 0, align 4
9
10; Function Attrs: norecurse nounwind readnone
11define signext i32 @test_igtsi(i32 signext %a, i32 signext %b) {
12; CHECK-LABEL: test_igtsi:
13; CHECK:       # %bb.0: # %entry
14; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
15; CHECK-NEXT:    rldicl r3, [[REG]], 1, 63
16; CHECK-NEXT:    blr
17entry:
18  %cmp = icmp sgt i32 %a, %b
19  %conv = zext i1 %cmp to i32
20  ret i32 %conv
21}
22
23; Function Attrs: norecurse nounwind readnone
24define signext i32 @test_igtsi_sext(i32 signext %a, i32 signext %b) {
25; CHECK-LABEL: test_igtsi_sext:
26; CHECK:       # %bb.0: # %entry
27; CHECK-NEXT:    sub [[REG:r[0-9]+]], r4, r3
28; CHECK-NEXT:    sradi r3, [[REG]], 63
29; CHECK-NEXT:    blr
30entry:
31  %cmp = icmp sgt i32 %a, %b
32  %sub = sext i1 %cmp to i32
33  ret i32 %sub
34}
35
36; FIXME
37; Function Attrs: norecurse nounwind readnone
38define signext i32 @test_igtsi_z(i32 signext %a) {
39; CHECK-LABEL: test_igtsi_z:
40; CHECK:       # %bb.0: # %entry
41; CHECK-NEXT:    neg r3, r3
42; CHECK-NEXT:    rldicl r3, r3, 1, 63
43; CHECK-NEXT:    blr
44entry:
45  %cmp = icmp sgt i32 %a, 0
46  %conv = zext i1 %cmp to i32
47  ret i32 %conv
48}
49
50; Function Attrs: norecurse nounwind readnone
51define signext i32 @test_igtsi_sext_z(i32 signext %a) {
52; CHECK-LABEL: test_igtsi_sext_z:
53; CHECK:  neg [[REG2:r[0-9]+]], r3
54; CHECK-NEXT: sradi r3, [[REG2]], 63
55; CHECK-NEXT: blr
56entry:
57  %cmp = icmp sgt i32 %a, 0
58  %sub = sext i1 %cmp to i32
59  ret i32 %sub
60}
61
62; Function Attrs: norecurse nounwind
63define void @test_igtsi_store(i32 signext %a, i32 signext %b) {
64; CHECK-LABEL: test_igtsi_store:
65; CHECK:       # %bb.0: # %entry
66; CHECK:         sub [[REG:r[0-9]+]], r4, r3
67; CHECK:         rldicl {{r[0-9]+}}, [[REG]], 1, 63
68entry:
69  %cmp = icmp sgt i32 %a, %b
70  %conv = zext i1 %cmp to i32
71  store i32 %conv, i32* @glob, align 4
72  ret void
73}
74
75; Function Attrs: norecurse nounwind
76define void @test_igtsi_sext_store(i32 signext %a, i32 signext %b) {
77; CHECK-LABEL: test_igtsi_sext_store:
78; CHECK:       # %bb.0: # %entry
79; CHECK:         sub [[REG:r[0-9]+]], r4, r3
80; CHECK:         sradi {{r[0-9]+}}, [[REG]], 63
81entry:
82  %cmp = icmp sgt i32 %a, %b
83  %sub = sext i1 %cmp to i32
84  store i32 %sub, i32* @glob, align 4
85  ret void
86}
87
88; FIXME
89; Function Attrs: norecurse nounwind
90define void @test_igtsi_z_store(i32 signext %a) {
91; CHECK-LABEL: test_igtsi_z_store:
92; CHECK:       # %bb.0: # %entry
93; CHECK-NEXT:    addis r4, r2, .LC0@toc@ha
94; CHECK-NEXT:    neg r3, r3
95; CHECK-NEXT:    ld r4, .LC0@toc@l(r4)
96; CHECK-NEXT:    rldicl r3, r3, 1, 63
97; CHECK-NEXT:    stw r3, 0(r4)
98; CHECK-NEXT:    blr
99entry:
100  %cmp = icmp sgt i32 %a, 0
101  %conv = zext i1 %cmp to i32
102  store i32 %conv, i32* @glob, align 4
103  ret void
104}
105
106; Function Attrs: norecurse nounwind
107define void @test_igtsi_sext_z_store(i32 signext %a) {
108; CHECK-LABEL: test_igtsi_sext_z_store:
109; CHECK: neg [[REG:r[0-9]+]], r3
110; CHECK: sradi {{r[0-9]+}}, [[REG]], 63
111entry:
112  %cmp = icmp sgt i32 %a, 0
113  %sub = sext i1 %cmp to i32
114  store i32 %sub, i32* @glob, align 4
115  ret void
116}
117