1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \ 3; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: -O3 < %s | FileCheck %s 5 6; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 7; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 8; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \ 9; RUN: --implicit-check-not xxswapd 10 11; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \ 12; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \ 13; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR 14 15; These tests verify that VSX swap optimization works when loading a scalar 16; into a vector register. 17 18 19@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16 20@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16 21@y = global double 1.780000e+00, align 8 22 23define void @bar0() { 24; CHECK-LABEL: bar0: 25; CHECK: # %bb.0: # %entry 26; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 27; CHECK-NEXT: addis r4, r2, .LC1@toc@ha 28; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 29; CHECK-NEXT: lfdx f0, 0, r3 30; CHECK-NEXT: ld r3, .LC1@toc@l(r4) 31; CHECK-NEXT: lxvd2x vs1, 0, r3 32; CHECK-NEXT: xxswapd vs0, vs0 33; CHECK-NEXT: addis r3, r2, .LC2@toc@ha 34; CHECK-NEXT: ld r3, .LC2@toc@l(r3) 35; CHECK-NEXT: xxmrgld vs0, vs0, vs1 36; CHECK-NEXT: stxvd2x vs0, 0, r3 37; CHECK-NEXT: blr 38; 39; CHECK-P9-LABEL: bar0: 40; CHECK-P9: # %bb.0: # %entry 41; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha 42; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) 43; CHECK-P9-NEXT: lxvx vs0, 0, r3 44; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha 45; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3) 46; CHECK-P9-NEXT: lfd f1, 0(r3) 47; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha 48; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3) 49; CHECK-P9-NEXT: xxmrghd vs0, vs0, vs1 50; CHECK-P9-NEXT: stxvx vs0, 0, r3 51; CHECK-P9-NEXT: blr 52; 53; CHECK-P9-NOVECTOR-LABEL: bar0: 54; CHECK-P9-NOVECTOR: # %bb.0: # %entry 55; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha 56; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3) 57; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r3 58; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha 59; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3) 60; CHECK-P9-NOVECTOR-NEXT: lfdx f1, 0, r3 61; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha 62; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3) 63; CHECK-P9-NOVECTOR-NEXT: xxswapd vs1, vs1 64; CHECK-P9-NOVECTOR-NEXT: xxmrgld vs0, vs1, vs0 65; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r3 66; CHECK-P9-NOVECTOR-NEXT: blr 67entry: 68 %0 = load <2 x double>, <2 x double>* @x, align 16 69 %1 = load double, double* @y, align 8 70 %vecins = insertelement <2 x double> %0, double %1, i32 0 71 store <2 x double> %vecins, <2 x double>* @z, align 16 72 ret void 73} 74 75define void @bar1() { 76; CHECK-LABEL: bar1: 77; CHECK: # %bb.0: # %entry 78; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 79; CHECK-NEXT: addis r4, r2, .LC1@toc@ha 80; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 81; CHECK-NEXT: lfdx f0, 0, r3 82; CHECK-NEXT: ld r3, .LC1@toc@l(r4) 83; CHECK-NEXT: lxvd2x vs1, 0, r3 84; CHECK-NEXT: xxswapd vs0, vs0 85; CHECK-NEXT: addis r3, r2, .LC2@toc@ha 86; CHECK-NEXT: ld r3, .LC2@toc@l(r3) 87; CHECK-NEXT: xxpermdi vs0, vs1, vs0, 1 88; CHECK-NEXT: stxvd2x vs0, 0, r3 89; CHECK-NEXT: blr 90; 91; CHECK-P9-LABEL: bar1: 92; CHECK-P9: # %bb.0: # %entry 93; CHECK-P9-NEXT: addis r3, r2, .LC0@toc@ha 94; CHECK-P9-NEXT: ld r3, .LC0@toc@l(r3) 95; CHECK-P9-NEXT: lxvx vs0, 0, r3 96; CHECK-P9-NEXT: addis r3, r2, .LC1@toc@ha 97; CHECK-P9-NEXT: ld r3, .LC1@toc@l(r3) 98; CHECK-P9-NEXT: lfd f1, 0(r3) 99; CHECK-P9-NEXT: addis r3, r2, .LC2@toc@ha 100; CHECK-P9-NEXT: ld r3, .LC2@toc@l(r3) 101; CHECK-P9-NEXT: xxpermdi vs0, vs1, vs0, 1 102; CHECK-P9-NEXT: stxvx vs0, 0, r3 103; CHECK-P9-NEXT: blr 104; 105; CHECK-P9-NOVECTOR-LABEL: bar1: 106; CHECK-P9-NOVECTOR: # %bb.0: # %entry 107; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC0@toc@ha 108; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC0@toc@l(r3) 109; CHECK-P9-NOVECTOR-NEXT: lxvd2x vs0, 0, r3 110; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC1@toc@ha 111; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC1@toc@l(r3) 112; CHECK-P9-NOVECTOR-NEXT: lfdx f1, 0, r3 113; CHECK-P9-NOVECTOR-NEXT: addis r3, r2, .LC2@toc@ha 114; CHECK-P9-NOVECTOR-NEXT: ld r3, .LC2@toc@l(r3) 115; CHECK-P9-NOVECTOR-NEXT: xxswapd vs1, vs1 116; CHECK-P9-NOVECTOR-NEXT: xxpermdi vs0, vs0, vs1, 1 117; CHECK-P9-NOVECTOR-NEXT: stxvd2x vs0, 0, r3 118; CHECK-P9-NOVECTOR-NEXT: blr 119entry: 120 %0 = load <2 x double>, <2 x double>* @x, align 16 121 %1 = load double, double* @y, align 8 122 %vecins = insertelement <2 x double> %0, double %1, i32 1 123 store <2 x double> %vecins, <2 x double>* @z, align 16 124 ret void 125} 126 127