1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3target triple = "powerpc64le-linux-gnu"
4
5define i8 @test000(i8 %a, i8 %b) {
6; CHECK-LABEL: test000:
7; CHECK:       # BB#0:
8; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
9; CHECK-NEXT:    slw 3, 3, 4
10; CHECK-NEXT:    blr
11  %rem = and i8 %b, 7
12  %shl = shl i8 %a, %rem
13  ret i8 %shl
14}
15
16define i16 @test001(i16 %a, i16 %b) {
17; CHECK-LABEL: test001:
18; CHECK:       # BB#0:
19; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
20; CHECK-NEXT:    slw 3, 3, 4
21; CHECK-NEXT:    blr
22  %rem = and i16 %b, 15
23  %shl = shl i16 %a, %rem
24  ret i16 %shl
25}
26
27define i32 @test002(i32 %a, i32 %b) {
28; CHECK-LABEL: test002:
29; CHECK:       # BB#0:
30; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
31; CHECK-NEXT:    slw 3, 3, 4
32; CHECK-NEXT:    blr
33  %rem = and i32 %b, 31
34  %shl = shl i32 %a, %rem
35  ret i32 %shl
36}
37
38define i64 @test003(i64 %a, i64 %b) {
39; CHECK-LABEL: test003:
40; CHECK:       # BB#0:
41; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
42; CHECK-NEXT:    sld 3, 3, 4
43; CHECK-NEXT:    blr
44  %rem = and i64 %b, 63
45  %shl = shl i64 %a, %rem
46  ret i64 %shl
47}
48
49define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) {
50; CHECK-LABEL: test010:
51; CHECK:       # BB#0:
52; CHECK-NEXT:    vspltisb 4, 7
53; CHECK-NEXT:    xxland 35, 35, 36
54; CHECK-NEXT:    vslb 2, 2, 3
55; CHECK-NEXT:    blr
56  %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
57  %shl = shl <16 x i8> %a, %rem
58  ret <16 x i8> %shl
59}
60
61define <8 x i16> @test011(<8 x i16> %a, <8 x i16> %b) {
62; CHECK-LABEL: test011:
63; CHECK:       # BB#0:
64; CHECK-NEXT:    vspltish 4, 15
65; CHECK-NEXT:    xxland 35, 35, 36
66; CHECK-NEXT:    vslh 2, 2, 3
67; CHECK-NEXT:    blr
68  %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
69  %shl = shl <8 x i16> %a, %rem
70  ret <8 x i16> %shl
71}
72
73define <4 x i32> @test012(<4 x i32> %a, <4 x i32> %b) {
74; CHECK-LABEL: test012:
75; CHECK:       # BB#0:
76; CHECK-NEXT:    vspltisw 4, -16
77; CHECK-NEXT:    vspltisw 5, 15
78; CHECK-NEXT:    vsubuwm 4, 5, 4
79; CHECK-NEXT:    xxland 35, 35, 36
80; CHECK-NEXT:    vslw 2, 2, 3
81; CHECK-NEXT:    blr
82  %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
83  %shl = shl <4 x i32> %a, %rem
84  ret <4 x i32> %shl
85}
86
87define <2 x i64> @test013(<2 x i64> %a, <2 x i64> %b) {
88; CHECK-LABEL: test013:
89; CHECK:       # BB#0:
90; CHECK-NEXT:    addis 3, 2, .LCPI7_0@toc@ha
91; CHECK-NEXT:    addi 3, 3, .LCPI7_0@toc@l
92; CHECK-NEXT:    lxvd2x 0, 0, 3
93; CHECK-NEXT:    xxswapd 36, 0
94; CHECK-NEXT:    xxland 35, 35, 36
95; CHECK-NEXT:    vsld 2, 2, 3
96; CHECK-NEXT:    blr
97  %rem = and <2 x i64> %b, <i64 63, i64 63>
98  %shl = shl <2 x i64> %a, %rem
99  ret <2 x i64> %shl
100}
101
102define i8 @test100(i8 %a, i8 %b) {
103; CHECK-LABEL: test100:
104; CHECK:       # BB#0:
105; CHECK-NEXT:    rlwinm 3, 3, 0, 24, 31
106; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
107; CHECK-NEXT:    srw 3, 3, 4
108; CHECK-NEXT:    blr
109  %rem = and i8 %b, 7
110  %lshr = lshr i8 %a, %rem
111  ret i8 %lshr
112}
113
114define i16 @test101(i16 %a, i16 %b) {
115; CHECK-LABEL: test101:
116; CHECK:       # BB#0:
117; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 31
118; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
119; CHECK-NEXT:    srw 3, 3, 4
120; CHECK-NEXT:    blr
121  %rem = and i16 %b, 15
122  %lshr = lshr i16 %a, %rem
123  ret i16 %lshr
124}
125
126define i32 @test102(i32 %a, i32 %b) {
127; CHECK-LABEL: test102:
128; CHECK:       # BB#0:
129; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
130; CHECK-NEXT:    srw 3, 3, 4
131; CHECK-NEXT:    blr
132  %rem = and i32 %b, 31
133  %lshr = lshr i32 %a, %rem
134  ret i32 %lshr
135}
136
137define i64 @test103(i64 %a, i64 %b) {
138; CHECK-LABEL: test103:
139; CHECK:       # BB#0:
140; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
141; CHECK-NEXT:    srd 3, 3, 4
142; CHECK-NEXT:    blr
143  %rem = and i64 %b, 63
144  %lshr = lshr i64 %a, %rem
145  ret i64 %lshr
146}
147
148define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) {
149; CHECK-LABEL: test110:
150; CHECK:       # BB#0:
151; CHECK-NEXT:    vspltisb 4, 7
152; CHECK-NEXT:    xxland 35, 35, 36
153; CHECK-NEXT:    vsrb 2, 2, 3
154; CHECK-NEXT:    blr
155  %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
156  %lshr = lshr <16 x i8> %a, %rem
157  ret <16 x i8> %lshr
158}
159
160define <8 x i16> @test111(<8 x i16> %a, <8 x i16> %b) {
161; CHECK-LABEL: test111:
162; CHECK:       # BB#0:
163; CHECK-NEXT:    vspltish 4, 15
164; CHECK-NEXT:    xxland 35, 35, 36
165; CHECK-NEXT:    vsrh 2, 2, 3
166; CHECK-NEXT:    blr
167  %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
168  %lshr = lshr <8 x i16> %a, %rem
169  ret <8 x i16> %lshr
170}
171
172define <4 x i32> @test112(<4 x i32> %a, <4 x i32> %b) {
173; CHECK-LABEL: test112:
174; CHECK:       # BB#0:
175; CHECK-NEXT:    vspltisw 4, -16
176; CHECK-NEXT:    vspltisw 5, 15
177; CHECK-NEXT:    vsubuwm 4, 5, 4
178; CHECK-NEXT:    xxland 35, 35, 36
179; CHECK-NEXT:    vsrw 2, 2, 3
180; CHECK-NEXT:    blr
181  %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
182  %lshr = lshr <4 x i32> %a, %rem
183  ret <4 x i32> %lshr
184}
185
186define <2 x i64> @test113(<2 x i64> %a, <2 x i64> %b) {
187; CHECK-LABEL: test113:
188; CHECK:       # BB#0:
189; CHECK-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
190; CHECK-NEXT:    addi 3, 3, .LCPI15_0@toc@l
191; CHECK-NEXT:    lxvd2x 0, 0, 3
192; CHECK-NEXT:    xxswapd 36, 0
193; CHECK-NEXT:    xxland 35, 35, 36
194; CHECK-NEXT:    vsrd 2, 2, 3
195; CHECK-NEXT:    blr
196  %rem = and <2 x i64> %b, <i64 63, i64 63>
197  %lshr = lshr <2 x i64> %a, %rem
198  ret <2 x i64> %lshr
199}
200
201define i8 @test200(i8 %a, i8 %b) {
202; CHECK-LABEL: test200:
203; CHECK:       # BB#0:
204; CHECK-NEXT:    extsb 3, 3
205; CHECK-NEXT:    rlwinm 4, 4, 0, 29, 31
206; CHECK-NEXT:    sraw 3, 3, 4
207; CHECK-NEXT:    blr
208  %rem = and i8 %b, 7
209  %ashr = ashr i8 %a, %rem
210  ret i8 %ashr
211}
212
213define i16 @test201(i16 %a, i16 %b) {
214; CHECK-LABEL: test201:
215; CHECK:       # BB#0:
216; CHECK-NEXT:    extsh 3, 3
217; CHECK-NEXT:    rlwinm 4, 4, 0, 28, 31
218; CHECK-NEXT:    sraw 3, 3, 4
219; CHECK-NEXT:    blr
220  %rem = and i16 %b, 15
221  %ashr = ashr i16 %a, %rem
222  ret i16 %ashr
223}
224
225define i32 @test202(i32 %a, i32 %b) {
226; CHECK-LABEL: test202:
227; CHECK:       # BB#0:
228; CHECK-NEXT:    rlwinm 4, 4, 0, 27, 31
229; CHECK-NEXT:    sraw 3, 3, 4
230; CHECK-NEXT:    blr
231  %rem = and i32 %b, 31
232  %ashr = ashr i32 %a, %rem
233  ret i32 %ashr
234}
235
236define i64 @test203(i64 %a, i64 %b) {
237; CHECK-LABEL: test203:
238; CHECK:       # BB#0:
239; CHECK-NEXT:    rlwinm 4, 4, 0, 26, 31
240; CHECK-NEXT:    srad 3, 3, 4
241; CHECK-NEXT:    blr
242  %rem = and i64 %b, 63
243  %ashr = ashr i64 %a, %rem
244  ret i64 %ashr
245}
246
247define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) {
248; CHECK-LABEL: test210:
249; CHECK:       # BB#0:
250; CHECK-NEXT:    vspltisb 4, 7
251; CHECK-NEXT:    xxland 35, 35, 36
252; CHECK-NEXT:    vsrab 2, 2, 3
253; CHECK-NEXT:    blr
254  %rem = and <16 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
255  %ashr = ashr <16 x i8> %a, %rem
256  ret <16 x i8> %ashr
257}
258
259define <8 x i16> @test211(<8 x i16> %a, <8 x i16> %b) {
260; CHECK-LABEL: test211:
261; CHECK:       # BB#0:
262; CHECK-NEXT:    vspltish 4, 15
263; CHECK-NEXT:    xxland 35, 35, 36
264; CHECK-NEXT:    vsrah 2, 2, 3
265; CHECK-NEXT:    blr
266  %rem = and <8 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
267  %ashr = ashr <8 x i16> %a, %rem
268  ret <8 x i16> %ashr
269}
270
271define <4 x i32> @test212(<4 x i32> %a, <4 x i32> %b) {
272; CHECK-LABEL: test212:
273; CHECK:       # BB#0:
274; CHECK-NEXT:    vspltisw 4, -16
275; CHECK-NEXT:    vspltisw 5, 15
276; CHECK-NEXT:    vsubuwm 4, 5, 4
277; CHECK-NEXT:    xxland 35, 35, 36
278; CHECK-NEXT:    vsraw 2, 2, 3
279; CHECK-NEXT:    blr
280  %rem = and <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
281  %ashr = ashr <4 x i32> %a, %rem
282  ret <4 x i32> %ashr
283}
284
285define <2 x i64> @test213(<2 x i64> %a, <2 x i64> %b) {
286; CHECK-LABEL: test213:
287; CHECK:       # BB#0:
288; CHECK-NEXT:    addis 3, 2, .LCPI23_0@toc@ha
289; CHECK-NEXT:    addi 3, 3, .LCPI23_0@toc@l
290; CHECK-NEXT:    lxvd2x 0, 0, 3
291; CHECK-NEXT:    xxswapd 36, 0
292; CHECK-NEXT:    xxland 35, 35, 36
293; CHECK-NEXT:    vsrad 2, 2, 3
294; CHECK-NEXT:    blr
295  %rem = and <2 x i64> %b, <i64 63, i64 63>
296  %ashr = ashr <2 x i64> %a, %rem
297  ret <2 x i64> %ashr
298}
299