1; XFAIL: *
2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
3; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown | FileCheck %s
4
5define zeroext i1 @all_bits_clear(i32 %P, i32 %Q)  {
6; CHECK-LABEL: all_bits_clear:
7; CHECK:       # BB#0:
8; CHECK-NEXT:    or 3, 3, 4
9; CHECK-NEXT:    cntlzw 3, 3
10; CHECK-NEXT:    srwi 3, 3, 5
11; CHECK-NEXT:    blr
12  %a = icmp eq i32 %P, 0
13  %b = icmp eq i32 %Q, 0
14  %c = and i1 %a, %b
15  ret i1 %c
16}
17
18define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
19; CHECK-LABEL: all_sign_bits_clear:
20; CHECK:       # BB#0:
21; CHECK-NEXT:    or 3, 3, 4
22; CHECK-NEXT:    nor 3, 3, 3
23; CHECK-NEXT:    srwi 3, 3, 31
24; CHECK-NEXT:    blr
25  %a = icmp sgt i32 %P, -1
26  %b = icmp sgt i32 %Q, -1
27  %c = and i1 %a, %b
28  ret i1 %c
29}
30
31define zeroext i1 @all_bits_set(i32 %P, i32 %Q)  {
32; CHECK-LABEL: all_bits_set:
33; CHECK:       # BB#0:
34; CHECK-NEXT:    li 5, -1
35; CHECK-NEXT:    and 3, 3, 4
36; CHECK-NEXT:    xor 3, 3, 5
37; CHECK-NEXT:    cntlzw 3, 3
38; CHECK-NEXT:    srwi 3, 3, 5
39; CHECK-NEXT:    blr
40  %a = icmp eq i32 %P, -1
41  %b = icmp eq i32 %Q, -1
42  %c = and i1 %a, %b
43  ret i1 %c
44}
45
46define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q)  {
47; CHECK-LABEL: all_sign_bits_set:
48; CHECK:       # BB#0:
49; CHECK-NEXT:    and 3, 3, 4
50; CHECK-NEXT:    srwi 3, 3, 31
51; CHECK-NEXT:    blr
52  %a = icmp slt i32 %P, 0
53  %b = icmp slt i32 %Q, 0
54  %c = and i1 %a, %b
55  ret i1 %c
56}
57
58define zeroext i1 @any_bits_set(i32 %P, i32 %Q)  {
59; CHECK-LABEL: any_bits_set:
60; CHECK:       # BB#0:
61; CHECK-NEXT:    or 3, 3, 4
62; CHECK-NEXT:    cntlzw 3, 3
63; CHECK-NEXT:    srwi 3, 3, 5
64; CHECK-NEXT:    xori 3, 3, 1
65; CHECK-NEXT:    blr
66  %a = icmp ne i32 %P, 0
67  %b = icmp ne i32 %Q, 0
68  %c = or i1 %a, %b
69  ret i1 %c
70}
71
72define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q)  {
73; CHECK-LABEL: any_sign_bits_set:
74; CHECK:       # BB#0:
75; CHECK-NEXT:    or 3, 3, 4
76; CHECK-NEXT:    srwi 3, 3, 31
77; CHECK-NEXT:    blr
78  %a = icmp slt i32 %P, 0
79  %b = icmp slt i32 %Q, 0
80  %c = or i1 %a, %b
81  ret i1 %c
82}
83
84define zeroext i1 @any_bits_clear(i32 %P, i32 %Q)  {
85; CHECK-LABEL: any_bits_clear:
86; CHECK:       # BB#0:
87; CHECK-NEXT:    li 5, -1
88; CHECK-NEXT:    and 3, 3, 4
89; CHECK-NEXT:    xor 3, 3, 5
90; CHECK-NEXT:    cntlzw   3, 3
91; CHECK-NEXT:    srwi 3, 3, 5
92; CHECK-NEXT:    xori 3, 3, 1
93; CHECK-NEXT:    blr
94  %a = icmp ne i32 %P, -1
95  %b = icmp ne i32 %Q, -1
96  %c = or i1 %a, %b
97  ret i1 %c
98}
99
100define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
101; CHECK-LABEL: any_sign_bits_clear:
102; CHECK:       # BB#0:
103; CHECK-NEXT:    and 3, 3, 4
104; CHECK-NEXT:    nor 3, 3, 3
105; CHECK-NEXT:    srwi 3, 3, 31
106; CHECK-NEXT:    blr
107  %a = icmp sgt i32 %P, -1
108  %b = icmp sgt i32 %Q, -1
109  %c = or i1 %a, %b
110  ret i1 %c
111}
112
113; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
114define i32 @all_bits_clear_branch(i32* %P, i32* %Q)  {
115; CHECK-LABEL: all_bits_clear_branch:
116; CHECK:       # BB#0: # %entry
117; CHECK-NEXT:    or. 3, 3, 4
118; CHECK-NEXT:    bne 0, .LBB8_2
119; CHECK-NEXT:  # BB#1: # %bb1
120; CHECK-NEXT:    li 3, 4
121; CHECK-NEXT:    blr
122; CHECK-NEXT:  .LBB8_2: # %return
123; CHECK-NEXT:    li 3, 192
124; CHECK-NEXT:    blr
125entry:
126  %a = icmp eq i32* %P, null
127  %b = icmp eq i32* %Q, null
128  %c = and i1 %a, %b
129  br i1 %c, label %bb1, label %return
130
131bb1:
132  ret i32 4
133
134return:
135  ret i32 192
136}
137
138define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q)  {
139; CHECK-LABEL: all_sign_bits_clear_branch:
140; CHECK:       # BB#0: # %entry
141; CHECK-NEXT:    or 3, 3, 4
142; CHECK-NEXT:    cmpwi 0, 3, 0
143; CHECK-NEXT:    blt 0, .LBB9_2
144; CHECK-NEXT:  # BB#1: # %bb1
145; CHECK-NEXT:    li 3, 4
146; CHECK-NEXT:    blr
147; CHECK-NEXT:  .LBB9_2: # %return
148; CHECK-NEXT:    li 3, 192
149; CHECK-NEXT:    blr
150entry:
151  %a = icmp sgt i32 %P, -1
152  %b = icmp sgt i32 %Q, -1
153  %c = and i1 %a, %b
154  br i1 %c, label %bb1, label %return
155
156bb1:
157  ret i32 4
158
159return:
160  ret i32 192
161}
162
163define i32 @all_bits_set_branch(i32 %P, i32 %Q)  {
164; CHECK-LABEL: all_bits_set_branch:
165; CHECK:       # BB#0: # %entry
166; CHECK-NEXT:    and 3, 3, 4
167; CHECK-NEXT:    cmpwi 0, 3, -1
168; CHECK-NEXT:    bne 0, .LBB10_2
169; CHECK-NEXT:  # BB#1: # %bb1
170; CHECK-NEXT:    li 3, 4
171; CHECK-NEXT:    blr
172; CHECK-NEXT:  .LBB10_2: # %return
173; CHECK-NEXT:    li 3, 192
174; CHECK-NEXT:    blr
175entry:
176  %a = icmp eq i32 %P, -1
177  %b = icmp eq i32 %Q, -1
178  %c = and i1 %a, %b
179  br i1 %c, label %bb1, label %return
180
181bb1:
182  ret i32 4
183
184return:
185  ret i32 192
186}
187
188define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q)  {
189; CHECK-LABEL: all_sign_bits_set_branch:
190; CHECK:       # BB#0: # %entry
191; CHECK-NEXT:    and 3, 3, 4
192; CHECK-NEXT:    cmpwi 0, 3, -1
193; CHECK-NEXT:    bgt 0, .LBB11_2
194; CHECK-NEXT:  # BB#1: # %bb1
195; CHECK-NEXT:    li 3, 4
196; CHECK-NEXT:    blr
197; CHECK-NEXT:  .LBB11_2: # %return
198; CHECK-NEXT:    li 3, 192
199; CHECK-NEXT:    blr
200entry:
201  %a = icmp slt i32 %P, 0
202  %b = icmp slt i32 %Q, 0
203  %c = and i1 %a, %b
204  br i1 %c, label %bb1, label %return
205
206bb1:
207  ret i32 4
208
209return:
210  ret i32 192
211}
212
213; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
214define i32 @any_bits_set_branch(i32* %P, i32* %Q)  {
215; CHECK-LABEL: any_bits_set_branch:
216; CHECK:       # BB#0: # %entry
217; CHECK-NEXT:    or. 3, 3, 4
218; CHECK-NEXT:    beq 0, .LBB12_2
219; CHECK-NEXT:  # BB#1: # %bb1
220; CHECK-NEXT:    li 3, 4
221; CHECK-NEXT:    blr
222; CHECK-NEXT:  .LBB12_2: # %return
223; CHECK-NEXT:    li 3, 192
224; CHECK-NEXT:    blr
225entry:
226  %a = icmp ne i32* %P, null
227  %b = icmp ne i32* %Q, null
228  %c = or i1 %a, %b
229  br i1 %c, label %bb1, label %return
230
231bb1:
232  ret i32 4
233
234return:
235  ret i32 192
236}
237
238define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q)  {
239; CHECK-LABEL: any_sign_bits_set_branch:
240; CHECK:       # BB#0: # %entry
241; CHECK-NEXT:    or 3, 3, 4
242; CHECK-NEXT:    cmpwi 0, 3, -1
243; CHECK-NEXT:    bgt 0, .LBB13_2
244; CHECK-NEXT:  # BB#1: # %bb1
245; CHECK-NEXT:    li 3, 4
246; CHECK-NEXT:    blr
247; CHECK-NEXT:  .LBB13_2: # %return
248; CHECK-NEXT:    li 3, 192
249; CHECK-NEXT:    blr
250entry:
251  %a = icmp slt i32 %P, 0
252  %b = icmp slt i32 %Q, 0
253  %c = or i1 %a, %b
254  br i1 %c, label %bb1, label %return
255
256bb1:
257  ret i32 4
258
259return:
260  ret i32 192
261}
262
263define i32 @any_bits_clear_branch(i32 %P, i32 %Q)  {
264; CHECK-LABEL: any_bits_clear_branch:
265; CHECK:       # BB#0: # %entry
266; CHECK-NEXT:    and 3, 3, 4
267; CHECK-NEXT:    cmpwi 0, 3, -1
268; CHECK-NEXT:    beq 0, .LBB14_2
269; CHECK-NEXT:  # BB#1: # %bb1
270; CHECK-NEXT:    li 3, 4
271; CHECK-NEXT:    blr
272; CHECK-NEXT:  .LBB14_2: # %return
273; CHECK-NEXT:    li 3, 192
274; CHECK-NEXT:    blr
275entry:
276  %a = icmp ne i32 %P, -1
277  %b = icmp ne i32 %Q, -1
278  %c = or i1 %a, %b
279  br i1 %c, label %bb1, label %return
280
281bb1:
282  ret i32 4
283
284return:
285  ret i32 192
286}
287
288define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q)  {
289; CHECK-LABEL: any_sign_bits_clear_branch:
290; CHECK:       # BB#0: # %entry
291; CHECK-NEXT:    and 3, 3, 4
292; CHECK-NEXT:    cmpwi 0, 3, 0
293; CHECK-NEXT:    blt 0, .LBB15_2
294; CHECK-NEXT:  # BB#1: # %bb1
295; CHECK-NEXT:    li 3, 4
296; CHECK-NEXT:    blr
297; CHECK-NEXT:  .LBB15_2: # %return
298; CHECK-NEXT:    li 3, 192
299; CHECK-NEXT:    blr
300entry:
301  %a = icmp sgt i32 %P, -1
302  %b = icmp sgt i32 %Q, -1
303  %c = or i1 %a, %b
304  br i1 %c, label %bb1, label %return
305
306bb1:
307  ret i32 4
308
309return:
310  ret i32 192
311}
312
313define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
314; CHECK-LABEL: all_bits_clear_vec:
315; CHECK:       # BB#0:
316; CHECK-NEXT:    xxlxor 36, 36, 36
317; CHECK-NEXT:    xxlor 34, 34, 35
318; CHECK-NEXT:    vcmpequw 2, 2, 4
319; CHECK-NEXT:    blr
320  %a = icmp eq <4 x i32> %P, zeroinitializer
321  %b = icmp eq <4 x i32> %Q, zeroinitializer
322  %c = and <4 x i1> %a, %b
323  ret <4 x i1> %c
324}
325
326define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
327; CHECK-LABEL: all_sign_bits_clear_vec:
328; CHECK:       # BB#0:
329; CHECK-NEXT:    vspltisb 4, -1
330; CHECK-NEXT:    xxlor 34, 34, 35
331; CHECK-NEXT:    vcmpgtsw 2, 2, 4
332; CHECK-NEXT:    blr
333  %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
334  %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
335  %c = and <4 x i1> %a, %b
336  ret <4 x i1> %c
337}
338
339define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
340; CHECK-LABEL: all_bits_set_vec:
341; CHECK:       # BB#0:
342; CHECK-NEXT:    vspltisb 4, -1
343; CHECK-NEXT:    xxland 34, 34, 35
344; CHECK-NEXT:    vcmpequw 2, 2, 4
345; CHECK-NEXT:    blr
346  %a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
347  %b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
348  %c = and <4 x i1> %a, %b
349  ret <4 x i1> %c
350}
351
352define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
353; CHECK-LABEL: all_sign_bits_set_vec:
354; CHECK:       # BB#0:
355; CHECK-NEXT:    xxlxor 36, 36, 36
356; CHECK-NEXT:    xxland 34, 34, 35
357; CHECK-NEXT:    vcmpgtsw 2, 4, 2
358; CHECK-NEXT:    blr
359  %a = icmp slt <4 x i32> %P, zeroinitializer
360  %b = icmp slt <4 x i32> %Q, zeroinitializer
361  %c = and <4 x i1> %a, %b
362  ret <4 x i1> %c
363}
364
365define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
366; CHECK-LABEL: any_bits_set_vec:
367; CHECK:       # BB#0:
368; CHECK-NEXT:    xxlxor 36, 36, 36
369; CHECK-NEXT:    xxlor 34, 34, 35
370; CHECK-NEXT:    vcmpequw 2, 2, 4
371; CHECK-NEXT:    xxlnor 34, 34, 34
372; CHECK-NEXT:    blr
373  %a = icmp ne <4 x i32> %P, zeroinitializer
374  %b = icmp ne <4 x i32> %Q, zeroinitializer
375  %c = or <4 x i1> %a, %b
376  ret <4 x i1> %c
377}
378
379define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
380; CHECK-LABEL: any_sign_bits_set_vec:
381; CHECK:       # BB#0:
382; CHECK-NEXT:    xxlxor 36, 36, 36
383; CHECK-NEXT:    xxlor 34, 34, 35
384; CHECK-NEXT:    vcmpgtsw 2, 4, 2
385; CHECK-NEXT:    blr
386  %a = icmp slt <4 x i32> %P, zeroinitializer
387  %b = icmp slt <4 x i32> %Q, zeroinitializer
388  %c = or <4 x i1> %a, %b
389  ret <4 x i1> %c
390}
391
392define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
393; CHECK-LABEL: any_bits_clear_vec:
394; CHECK:       # BB#0:
395; CHECK-NEXT:    vspltisb 4, -1
396; CHECK-NEXT:    xxland 34, 34, 35
397; CHECK-NEXT:    vcmpequw 2, 2, 4
398; CHECK-NEXT:    xxlnor 34, 34, 34
399; CHECK-NEXT:    blr
400  %a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
401  %b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
402  %c = or <4 x i1> %a, %b
403  ret <4 x i1> %c
404}
405
406define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
407; CHECK-LABEL: any_sign_bits_clear_vec:
408; CHECK:       # BB#0:
409; CHECK-NEXT:    vspltisb 4, -1
410; CHECK-NEXT:    xxland 34, 34, 35
411; CHECK-NEXT:    vcmpgtsw 2, 2, 4
412; CHECK-NEXT:    blr
413  %a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
414  %b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
415  %c = or <4 x i1> %a, %b
416  ret <4 x i1> %c
417}
418
419define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
420; CHECK-LABEL: ne_neg1_and_ne_zero:
421; CHECK:       # BB#0:
422; CHECK-NEXT:    addi 3, 3, 1
423; CHECK-NEXT:    li 4, 0
424; CHECK-NEXT:    li 12, 1
425; CHECK-NEXT:    cmpldi 3, 1
426; CHECK-NEXT:    isel 3, 12, 4, 1
427; CHECK-NEXT:    blr
428  %cmp1 = icmp ne i64 %x, -1
429  %cmp2 = icmp ne i64 %x, 0
430  %and = and i1 %cmp1, %cmp2
431  ret i1 %and
432}
433
434; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
435
436define zeroext i1 @and_eq(i16 zeroext  %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
437; CHECK-LABEL: and_eq:
438; CHECK:       # BB#0:
439; CHECK-NEXT:    xor 5, 5, 6
440; CHECK-NEXT:    xor 3, 3, 4
441; CHECK-NEXT:    or 3, 3, 5
442; CHECK-NEXT:    cntlzw 3, 3
443; CHECK-NEXT:    srwi 3, 3, 5
444; CHECK-NEXT:    blr
445  %cmp1 = icmp eq i16 %a, %b
446  %cmp2 = icmp eq i16 %c, %d
447  %and = and i1 %cmp1, %cmp2
448  ret i1 %and
449}
450
451define zeroext i1 @or_ne(i32 %a, i32 %b, i32 %c, i32 %d) {
452; CHECK-LABEL: or_ne:
453; CHECK:       # BB#0:
454; CHECK-NEXT:    xor 5, 5, 6
455; CHECK-NEXT:    xor 3, 3, 4
456; CHECK-NEXT:    or 3, 3, 5
457; CHECK-NEXT:    cntlzw 3, 3
458; CHECK-NEXT:    srwi 3, 3, 5
459; CHECK-NEXT:    xori 3, 3, 1
460; CHECK-NEXT:    blr
461  %cmp1 = icmp ne i32 %a, %b
462  %cmp2 = icmp ne i32 %c, %d
463  %or = or i1 %cmp1, %cmp2
464  ret i1 %or
465}
466
467; This should not be transformed because vector compares + bitwise logic are faster.
468
469define <4 x i1> @and_eq_vec(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
470; CHECK-LABEL: and_eq_vec:
471; CHECK:       # BB#0:
472; CHECK-NEXT:    vcmpequw 2, 2, 3
473; CHECK-NEXT:    vcmpequw 19, 4, 5
474; CHECK-NEXT:    xxland 34, 34, 51
475; CHECK-NEXT:    blr
476  %cmp1 = icmp eq <4 x i32> %a, %b
477  %cmp2 = icmp eq <4 x i32> %c, %d
478  %and = and <4 x i1> %cmp1, %cmp2
479  ret <4 x i1> %and
480}
481
482