1; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
2; RUN:     -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     < %s | FileCheck %s
4
5; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
6; RUN:     -mtriple=powerpc64-unknown-linux-gnu \
7; RUN:     < %s | FileCheck %s --check-prefix=P9BE
8
9; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
10; RUN:     -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi \
11; RUN:     < %s | FileCheck %s --check-prefix=P9BE
12
13; RUN: llc -mcpu=pwr9 -O3 -verify-machineinstrs -ppc-vsr-nums-as-vr \
14; RUN:     -mtriple=powerpc-ibm-aix-xcoff -vec-extabi \
15; RUN:     < %s | FileCheck %s --check-prefix=P9BE-32
16
17define void @test64(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
18; CHECK-LABEL: test64:
19; CHECK-NOT: ldux
20; CHECK-NOT: mtvsrd
21; CHECK: lxsdx [[REG:[0-9]+]]
22; CHECK: vperm {{[0-9]+}}, [[REG]]
23; P9BE-LABEL: test64:
24; P9BE-NOT: ldux
25; P9BE-NOT: mtvsrd
26; P9BE: lxsdx [[REG:[0-9]+]]
27; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
28; P9BE-32-LABEL: test64:
29; P9BE-32: lwzux [[REG1:[0-9]+]]
30; P9BE-32: mtfprwz [[REG2:[0-9]+]], [[REG1]]
31; P9BE-32: xxinsertw [[REG3:[0-9]+]], [[REG2]]
32; P9BE-32: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG3]]
33entry:
34  %idx.ext63 = sext i32 %i_pix2 to i64
35  %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
36  %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
37  %0 = bitcast i8* %add.ptr64 to <4 x i16>*
38  %1 = load <4 x i16>, <4 x i16>* %0, align 1
39  %reorder_shuffle117 = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
40  %2 = zext <4 x i16> %reorder_shuffle117 to <4 x i32>
41  %3 = sub nsw <4 x i32> zeroinitializer, %2
42  %4 = bitcast i8* %arrayidx5.1 to <4 x i16>*
43  %5 = load <4 x i16>, <4 x i16>* %4, align 1
44  %reorder_shuffle115 = shufflevector <4 x i16> %5, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
45  %6 = zext <4 x i16> %reorder_shuffle115 to <4 x i32>
46  %7 = sub nsw <4 x i32> zeroinitializer, %6
47  %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16>
48  %9 = add nsw <4 x i32> %8, %3
49  %10 = sub nsw <4 x i32> %9, zeroinitializer
50  %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5>
51  %12 = add nsw <4 x i32> zeroinitializer, %11
52  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
53  store <4 x i32> %13, <4 x i32>* undef, align 16
54  ret void
55}
56
57define void @test32(i8* nocapture readonly %pix2, i32 signext %i_pix2) {
58; CHECK-LABEL: test32:
59; CHECK-NOT: lwzux
60; CHECK-NOT: mtvsrwz
61; CHECK: lxsiwzx [[REG:[0-9]+]]
62; CHECK: vperm {{[0-9]+}}, [[REG]]
63; P9BE-LABEL: test32:
64; P9BE-NOT: lwzux
65; P9BE-NOT: mtvsrwz
66; P9BE: lxsiwzx [[REG:[0-9]+]]
67; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
68; P9BE-32-LABEL: test32:
69; P9BE-32: lwzx [[REG1:[0-9]+]]
70; P9BE-32: mtvsrwz [[REG2:[0-9]+]], [[REG1]]
71; P9BE-32: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
72entry:
73  %idx.ext63 = sext i32 %i_pix2 to i64
74  %add.ptr64 = getelementptr inbounds i8, i8* %pix2, i64 %idx.ext63
75  %arrayidx5.1 = getelementptr inbounds i8, i8* %add.ptr64, i64 4
76  %0 = bitcast i8* %add.ptr64 to <4 x i8>*
77  %1 = load <4 x i8>, <4 x i8>* %0, align 1
78  %reorder_shuffle117 = shufflevector <4 x i8> %1, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
79  %2 = zext <4 x i8> %reorder_shuffle117 to <4 x i32>
80  %3 = sub nsw <4 x i32> zeroinitializer, %2
81  %4 = bitcast i8* %arrayidx5.1 to <4 x i8>*
82  %5 = load <4 x i8>, <4 x i8>* %4, align 1
83  %reorder_shuffle115 = shufflevector <4 x i8> %5, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
84  %6 = zext <4 x i8> %reorder_shuffle115 to <4 x i32>
85  %7 = sub nsw <4 x i32> zeroinitializer, %6
86  %8 = shl nsw <4 x i32> %7, <i32 16, i32 16, i32 16, i32 16>
87  %9 = add nsw <4 x i32> %8, %3
88  %10 = sub nsw <4 x i32> %9, zeroinitializer
89  %11 = shufflevector <4 x i32> undef, <4 x i32> %10, <4 x i32> <i32 2, i32 7, i32 0, i32 5>
90  %12 = add nsw <4 x i32> zeroinitializer, %11
91  %13 = shufflevector <4 x i32> %12, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
92  store <4 x i32> %13, <4 x i32>* undef, align 16
93  ret void
94}
95
96define void @test16(i16* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
97; CHECK-LABEL: test16
98; CHECK-NOT: lhzux
99; CHECK: lxsihzx [[REG:[0-9]+]]
100; CHECK: vmrghh {{[0-9]+}}, {{[0-9]+}}, [[REG]]
101; P9BE-LABEL: test16
102; P9BE-NOT: lhzux
103; P9BE: lxsihzx [[REG:[0-9]+]]
104; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
105; P9BE-32-LABEL: test16:
106; P9BE-32: lhzux [[REG1:[0-9]+]]
107; P9BE-32: vmrghh {{[0-9]+}}, {{[0-9]+}}, [[REG1]]
108entry:
109  %idxprom = sext i32 %delta to i64
110  %add14 = add nsw i32 %delta, 8
111  %idxprom15 = sext i32 %add14 to i64
112  br label %for.body
113
114for.body:                                         ; preds = %entry
115  %arrayidx8 = getelementptr inbounds i16, i16* %sums, i64 %idxprom
116  %0 = load i16, i16* %arrayidx8, align 2
117  %arrayidx16 = getelementptr inbounds i16, i16* %sums, i64 %idxprom15
118  %1 = load i16, i16* %arrayidx16, align 2
119  %2 = insertelement <4 x i16> undef, i16 %0, i32 2
120  %3 = insertelement <4 x i16> %2, i16 %1, i32 3
121  %4 = zext <4 x i16> %3 to <4 x i32>
122  %5 = sub nsw <4 x i32> zeroinitializer, %4
123  %6 = sub nsw <4 x i32> zeroinitializer, %5
124  %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
125  %bin.rdx = add <4 x i32> %7, zeroinitializer
126  %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
127  %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
128  %8 = extractelement <4 x i32> %bin.rdx55, i32 0
129  %op.extra = add nuw i32 %8, 0
130  %cmp25 = icmp slt i32 %op.extra, %thresh
131  br i1 %cmp25, label %if.then, label %if.end
132
133if.then:                                          ; preds = %for.body
134  unreachable
135
136if.end:                                           ; preds = %for.body
137  ret void
138}
139
140define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
141; CHECK-LABEL: test8:
142; CHECK-NOT: lbzux
143; CHECK: lxsibzx [[REG:[0-9]+]]
144; CHECK: vmrghb {{[0-9]+}}, {{[0-9]+}}, [[REG]]
145; P9BE-LABEL: test8:
146; P9BE-NOT: lbzux
147; P9BE: lxsibzx [[REG:[0-9]+]]
148; P9BE: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
149; P9BE-32-LABEL: test8:
150; P9BE-32: lxsibzx [[REG:[0-9]+]]
151; P9BE-32: vperm {{[0-9]+}}, {{[0-9]+}}, [[REG]]
152entry:
153  %idxprom = sext i32 %delta to i64
154  %add14 = add nsw i32 %delta, 8
155  %idxprom15 = sext i32 %add14 to i64
156  br label %for.body
157
158for.body:                                         ; preds = %entry
159  %arrayidx8 = getelementptr inbounds i8, i8* %sums, i64 %idxprom
160  %0 = load i8, i8* %arrayidx8, align 2
161  %arrayidx16 = getelementptr inbounds i8, i8* %sums, i64 %idxprom15
162  %1 = load i8, i8* %arrayidx16, align 2
163  %2 = insertelement <4 x i8> undef, i8 %0, i32 2
164  %3 = insertelement <4 x i8> %2, i8 %1, i32 3
165  %4 = zext <4 x i8> %3 to <4 x i32>
166  %5 = sub nsw <4 x i32> zeroinitializer, %4
167  %6 = sub nsw <4 x i32> zeroinitializer, %5
168  %7 = select <4 x i1> undef, <4 x i32> %6, <4 x i32> %5
169  %bin.rdx = add <4 x i32> %7, zeroinitializer
170  %rdx.shuf54 = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
171  %bin.rdx55 = add <4 x i32> %bin.rdx, %rdx.shuf54
172  %8 = extractelement <4 x i32> %bin.rdx55, i32 0
173  %op.extra = add nuw i32 %8, 0
174  %cmp25 = icmp slt i32 %op.extra, %thresh
175  br i1 %cmp25, label %if.then, label %if.end
176
177if.then:                                          ; preds = %for.body
178  unreachable
179
180if.end:                                           ; preds = %for.body
181  ret void
182}
183