1; RUN: llc -verify-machineinstrs < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; CHECK-LABEL: test:
6; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
7
8; CHECK-LABEL: property_access1:
9; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
10
11; CHECK-LABEL: property_access2:
12; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
13
14; CHECK-LABEL: property_access3:
15; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
16
17; CHECK-LABEL: anyreg_test1:
18; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
19
20; CHECK-LABEL: anyreg_test2:
21; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
22
23; CHECK-LABEL: patchpoint_spilldef:
24; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
25
26; CHECK-LABEL: patchpoint_spillargs:
27; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
28
29
30; Stackmap Header: no constants - 6 callsites
31; CHECK-LABEL: .section	.llvm_stackmaps
32; CHECK-NEXT:  __LLVM_StackMaps:
33; Header
34; CHECK-NEXT:   .byte 3
35; CHECK-NEXT:   .byte 0
36; CHECK-NEXT:   .short 0
37; Num Functions
38; CHECK-NEXT:   .long 8
39; Num LargeConstants
40; CHECK-NEXT:   .long 0
41; Num Callsites
42; CHECK-NEXT:   .long 8
43
44; Functions and stack size
45; CHECK-NEXT:   .quad test
46; CHECK-NEXT:   .quad 128
47; CHECK-NEXT:   .quad 1
48; CHECK-NEXT:   .quad property_access1
49; CHECK-NEXT:   .quad 128
50; CHECK-NEXT:   .quad 1
51; CHECK-NEXT:   .quad property_access2
52; CHECK-NEXT:   .quad 128
53; CHECK-NEXT:   .quad 1
54; CHECK-NEXT:   .quad property_access3
55; CHECK-NEXT:   .quad 128
56; CHECK-NEXT:   .quad 1
57; CHECK-NEXT:   .quad anyreg_test1
58; CHECK-NEXT:   .quad 144
59; CHECK-NEXT:   .quad 1
60; CHECK-NEXT:   .quad anyreg_test2
61; CHECK-NEXT:   .quad 144
62; CHECK-NEXT:   .quad 1
63; CHECK-NEXT:   .quad patchpoint_spilldef
64; CHECK-NEXT:   .quad 256
65; CHECK-NEXT:   .quad 1
66; CHECK-NEXT:   .quad patchpoint_spillargs
67; CHECK-NEXT:   .quad 288
68; CHECK-NEXT:   .quad 1
69
70
71; test
72; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
73; CHECK-NEXT:   .short  0
74; 3 locations
75; CHECK-NEXT:   .short  3
76; Loc 0: Register
77; CHECK-NEXT:   .byte 1
78; CHECK-NEXT:   .byte 0
79; CHECK-NEXT:   .short 4
80; CHECK-NEXT:   .short {{[0-9]+}}
81; CHECK-NEXT:   .short 0
82; CHECK-NEXT:   .long 0
83; Loc 1: Register
84; CHECK-NEXT:   .byte 1
85; CHECK-NEXT:   .byte 0
86; CHECK-NEXT:   .short 4
87; CHECK-NEXT:   .short {{[0-9]+}}
88; CHECK-NEXT:   .short 0
89; CHECK-NEXT:   .long 0
90; Loc 2: Constant 3
91; CHECK-NEXT:   .byte 4
92; CHECK-NEXT:   .byte 0
93; CHECK-NEXT:   .short 8
94; CHECK-NEXT:   .short 0
95; CHECK-NEXT:   .short 0
96; CHECK-NEXT:   .long 3
97define i64 @test() nounwind ssp uwtable {
98entry:
99  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
100  ret i64 0
101}
102
103; property access 1 - %obj is an anyreg call argument and should therefore be in a register
104; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
105; CHECK-NEXT:   .short 0
106; 2 locations
107; CHECK-NEXT:   .short  2
108; Loc 0: Register <-- this is the return register
109; CHECK-NEXT:   .byte 1
110; CHECK-NEXT:   .byte 0
111; CHECK-NEXT:   .short 8
112; CHECK-NEXT:   .short {{[0-9]+}}
113; CHECK-NEXT:   .short 0
114; CHECK-NEXT:   .long 0
115; Loc 1: Register
116; CHECK-NEXT:   .byte 1
117; CHECK-NEXT:   .byte 0
118; CHECK-NEXT:   .short 8
119; CHECK-NEXT:   .short {{[0-9]+}}
120; CHECK-NEXT:   .short 0
121; CHECK-NEXT:   .long 0
122define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
123entry:
124  %f = inttoptr i64 281474417671919 to i8*
125  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
126  ret i64 %ret
127}
128
129; property access 2 - %obj is an anyreg call argument and should therefore be in a register
130; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
131; CHECK-NEXT:   .short 0
132; 2 locations
133; CHECK-NEXT:   .short  2
134; Loc 0: Register <-- this is the return register
135; CHECK-NEXT:   .byte 1
136; CHECK-NEXT:   .byte 0
137; CHECK-NEXT:   .short 8
138; CHECK-NEXT:   .short {{[0-9]+}}
139; CHECK-NEXT:   .short 0
140; CHECK-NEXT:   .long 0
141; Loc 1: Register
142; CHECK-NEXT:   .byte 1
143; CHECK-NEXT:   .byte 0
144; CHECK-NEXT:   .short 8
145; CHECK-NEXT:   .short {{[0-9]+}}
146; CHECK-NEXT:   .short 0
147; CHECK-NEXT:   .long 0
148define i64 @property_access2() nounwind ssp uwtable {
149entry:
150  %obj = alloca i64, align 8
151  %f = inttoptr i64 281474417671919 to i8*
152  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
153  ret i64 %ret
154}
155
156; property access 3 - %obj is a frame index
157; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
158; CHECK-NEXT:   .short 0
159; 2 locations
160; CHECK-NEXT:   .short  2
161; Loc 0: Register <-- this is the return register
162; CHECK-NEXT:   .byte 1
163; CHECK-NEXT:   .byte 0
164; CHECK-NEXT:   .short 8
165; CHECK-NEXT:   .short {{[0-9]+}}
166; CHECK-NEXT:   .short 0
167; CHECK-NEXT:   .long 0
168; Loc 1: Direct FP - 8
169; CHECK-NEXT:   .byte 2
170; CHECK-NEXT:   .byte 0
171; CHECK-NEXT:   .short 8
172; CHECK-NEXT:   .short 31
173; CHECK-NEXT:   .short 0
174; CHECK-NEXT:   .long 112
175define i64 @property_access3() nounwind ssp uwtable {
176entry:
177  %obj = alloca i64, align 8
178  %f = inttoptr i64 281474417671919 to i8*
179  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
180  ret i64 %ret
181}
182
183; anyreg_test1
184; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
185; CHECK-NEXT:   .short 0
186; 14 locations
187; CHECK-NEXT:   .short  14
188; Loc 0: Register <-- this is the return register
189; CHECK-NEXT:   .byte 1
190; CHECK-NEXT:   .byte 0
191; CHECK-NEXT:   .short 8
192; CHECK-NEXT:   .short {{[0-9]+}}
193; CHECK-NEXT:   .short 0
194; CHECK-NEXT:   .long 0
195; Loc 1: Register
196; CHECK-NEXT:   .byte 1
197; CHECK-NEXT:   .byte 0
198; CHECK-NEXT:   .short 8
199; CHECK-NEXT:   .short {{[0-9]+}}
200; CHECK-NEXT:   .short 0
201; CHECK-NEXT:   .long 0
202; Loc 2: Register
203; CHECK-NEXT:   .byte 1
204; CHECK-NEXT:   .byte 0
205; CHECK-NEXT:   .short 8
206; CHECK-NEXT:   .short {{[0-9]+}}
207; CHECK-NEXT:   .short 0
208; CHECK-NEXT:   .long 0
209; Loc 3: Register
210; CHECK-NEXT:   .byte 1
211; CHECK-NEXT:   .byte 0
212; CHECK-NEXT:   .short 8
213; CHECK-NEXT:   .short {{[0-9]+}}
214; CHECK-NEXT:   .short 0
215; CHECK-NEXT:   .long 0
216; Loc 4: Register
217; CHECK-NEXT:   .byte 1
218; CHECK-NEXT:   .byte 0
219; CHECK-NEXT:   .short 8
220; CHECK-NEXT:   .short {{[0-9]+}}
221; CHECK-NEXT:   .short 0
222; CHECK-NEXT:   .long 0
223; Loc 5: Register
224; CHECK-NEXT:   .byte 1
225; CHECK-NEXT:   .byte 0
226; CHECK-NEXT:   .short 8
227; CHECK-NEXT:   .short {{[0-9]+}}
228; CHECK-NEXT:   .short 0
229; CHECK-NEXT:   .long 0
230; Loc 6: Register
231; CHECK-NEXT:   .byte 1
232; CHECK-NEXT:   .byte 0
233; CHECK-NEXT:   .short 8
234; CHECK-NEXT:   .short {{[0-9]+}}
235; CHECK-NEXT:   .short 0
236; CHECK-NEXT:   .long 0
237; Loc 7: Register
238; CHECK-NEXT:   .byte 1
239; CHECK-NEXT:   .byte 0
240; CHECK-NEXT:   .short 8
241; CHECK-NEXT:   .short {{[0-9]+}}
242; CHECK-NEXT:   .short 0
243; CHECK-NEXT:   .long 0
244; Loc 8: Register
245; CHECK-NEXT:   .byte 1
246; CHECK-NEXT:   .byte 0
247; CHECK-NEXT:   .short 8
248; CHECK-NEXT:   .short {{[0-9]+}}
249; CHECK-NEXT:   .short 0
250; CHECK-NEXT:   .long 0
251; Loc 9: Register
252; CHECK-NEXT:   .byte 1
253; CHECK-NEXT:   .byte 0
254; CHECK-NEXT:   .short 8
255; CHECK-NEXT:   .short {{[0-9]+}}
256; CHECK-NEXT:   .short 0
257; CHECK-NEXT:   .long 0
258; Loc 10: Register
259; CHECK-NEXT:   .byte 1
260; CHECK-NEXT:   .byte 0
261; CHECK-NEXT:   .short 8
262; CHECK-NEXT:   .short {{[0-9]+}}
263; CHECK-NEXT:   .short 0
264; CHECK-NEXT:   .long 0
265; Loc 11: Register
266; CHECK-NEXT:   .byte 1
267; CHECK-NEXT:   .byte 0
268; CHECK-NEXT:   .short 8
269; CHECK-NEXT:   .short {{[0-9]+}}
270; CHECK-NEXT:   .short 0
271; CHECK-NEXT:   .long 0
272; Loc 12: Register
273; CHECK-NEXT:   .byte 1
274; CHECK-NEXT:   .byte 0
275; CHECK-NEXT:   .short 8
276; CHECK-NEXT:   .short {{[0-9]+}}
277; CHECK-NEXT:   .short 0
278; CHECK-NEXT:   .long 0
279; Loc 13: Register
280; CHECK-NEXT:   .byte 1
281; CHECK-NEXT:   .byte 0
282; CHECK-NEXT:   .short 8
283; CHECK-NEXT:   .short {{[0-9]+}}
284; CHECK-NEXT:   .short 0
285; CHECK-NEXT:   .long 0
286define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
287entry:
288  %f = inttoptr i64 281474417671919 to i8*
289  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
290  ret i64 %ret
291}
292
293; anyreg_test2
294; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
295; CHECK-NEXT:   .short 0
296; 14 locations
297; CHECK-NEXT:   .short  14
298; Loc 0: Register <-- this is the return register
299; CHECK-NEXT:   .byte 1
300; CHECK-NEXT:   .byte 0
301; CHECK-NEXT:   .short 8
302; CHECK-NEXT:   .short {{[0-9]+}}
303; CHECK-NEXT:   .short 0
304; CHECK-NEXT:   .long 0
305; Loc 1: Register
306; CHECK-NEXT:   .byte 1
307; CHECK-NEXT:   .byte 0
308; CHECK-NEXT:   .short 8
309; CHECK-NEXT:   .short {{[0-9]+}}
310; CHECK-NEXT:   .short 0
311; CHECK-NEXT:   .long 0
312; Loc 2: Register
313; CHECK-NEXT:   .byte 1
314; CHECK-NEXT:   .byte 0
315; CHECK-NEXT:   .short 8
316; CHECK-NEXT:   .short {{[0-9]+}}
317; CHECK-NEXT:   .short 0
318; CHECK-NEXT:   .long 0
319; Loc 3: Register
320; CHECK-NEXT:   .byte 1
321; CHECK-NEXT:   .byte 0
322; CHECK-NEXT:   .short 8
323; CHECK-NEXT:   .short {{[0-9]+}}
324; CHECK-NEXT:   .short 0
325; CHECK-NEXT:   .long 0
326; Loc 4: Register
327; CHECK-NEXT:   .byte 1
328; CHECK-NEXT:   .byte 0
329; CHECK-NEXT:   .short 8
330; CHECK-NEXT:   .short {{[0-9]+}}
331; CHECK-NEXT:   .short 0
332; CHECK-NEXT:   .long 0
333; Loc 5: Register
334; CHECK-NEXT:   .byte 1
335; CHECK-NEXT:   .byte 0
336; CHECK-NEXT:   .short 8
337; CHECK-NEXT:   .short {{[0-9]+}}
338; CHECK-NEXT:   .short 0
339; CHECK-NEXT:   .long 0
340; Loc 6: Register
341; CHECK-NEXT:   .byte 1
342; CHECK-NEXT:   .byte 0
343; CHECK-NEXT:   .short 8
344; CHECK-NEXT:   .short {{[0-9]+}}
345; CHECK-NEXT:   .short 0
346; CHECK-NEXT:   .long 0
347; Loc 7: Register
348; CHECK-NEXT:   .byte 1
349; CHECK-NEXT:   .byte 0
350; CHECK-NEXT:   .short 8
351; CHECK-NEXT:   .short {{[0-9]+}}
352; CHECK-NEXT:   .short 0
353; CHECK-NEXT:   .long 0
354; Loc 8: Register
355; CHECK-NEXT:   .byte 1
356; CHECK-NEXT:   .byte 0
357; CHECK-NEXT:   .short 8
358; CHECK-NEXT:   .short {{[0-9]+}}
359; CHECK-NEXT:   .short 0
360; CHECK-NEXT:   .long 0
361; Loc 9: Register
362; CHECK-NEXT:   .byte 1
363; CHECK-NEXT:   .byte 0
364; CHECK-NEXT:   .short 8
365; CHECK-NEXT:   .short {{[0-9]+}}
366; CHECK-NEXT:   .short 0
367; CHECK-NEXT:   .long 0
368; Loc 10: Register
369; CHECK-NEXT:   .byte 1
370; CHECK-NEXT:   .byte 0
371; CHECK-NEXT:   .short 8
372; CHECK-NEXT:   .short {{[0-9]+}}
373; CHECK-NEXT:   .short 0
374; CHECK-NEXT:   .long 0
375; Loc 11: Register
376; CHECK-NEXT:   .byte 1
377; CHECK-NEXT:   .byte 0
378; CHECK-NEXT:   .short 8
379; CHECK-NEXT:   .short {{[0-9]+}}
380; CHECK-NEXT:   .short 0
381; CHECK-NEXT:   .long 0
382; Loc 12: Register
383; CHECK-NEXT:   .byte 1
384; CHECK-NEXT:   .byte 0
385; CHECK-NEXT:   .short 8
386; CHECK-NEXT:   .short {{[0-9]+}}
387; CHECK-NEXT:   .short 0
388; CHECK-NEXT:   .long 0
389; Loc 13: Register
390; CHECK-NEXT:   .byte 1
391; CHECK-NEXT:   .byte 0
392; CHECK-NEXT:   .short 8
393; CHECK-NEXT:   .short {{[0-9]+}}
394; CHECK-NEXT:   .short 0
395; CHECK-NEXT:   .long 0
396define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
397entry:
398  %f = inttoptr i64 281474417671919 to i8*
399  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
400  ret i64 %ret
401}
402
403; Test spilling the return value of an anyregcc call.
404;
405; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
406;
407; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
408; CHECK-NEXT: .short 0
409; CHECK-NEXT: .short 3
410; Loc 0: Register (some register that will be spilled to the stack)
411; CHECK-NEXT: .byte  1
412; CHECK-NEXT: .byte 0
413; CHECK-NEXT: .short 8
414; CHECK-NEXT: .short {{[0-9]+}}
415; CHECK-NEXT: .short 0
416; CHECK-NEXT: .long  0
417; Loc 1: Register
418; CHECK-NEXT: .byte  1
419; CHECK-NEXT: .byte 0
420; CHECK-NEXT: .short 8
421; CHECK-NEXT: .short {{[0-9]+}}
422; CHECK-NEXT: .short 0
423; CHECK-NEXT: .long  0
424; Loc 1: Register
425; CHECK-NEXT: .byte  1
426; CHECK-NEXT: .byte 0
427; CHECK-NEXT: .short 8
428; CHECK-NEXT: .short {{[0-9]+}}
429; CHECK-NEXT: .short 0
430; CHECK-NEXT: .long  0
431define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
432entry:
433  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
434  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
435},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
436  ret i64 %result
437}
438
439; Test spilling the arguments of an anyregcc call.
440;
441; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
442;
443; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
444; CHECK-NEXT: .short 0
445; CHECK-NEXT: .short 5
446; Loc 0: Return a register
447; CHECK-NEXT: .byte  1
448; CHECK-NEXT: .byte 0
449; CHECK-NEXT: .short 8
450; CHECK-NEXT: .short {{[0-9]+}}
451; CHECK-NEXT: .short 0
452; CHECK-NEXT: .long  0
453; Loc 1: Arg0 in a Register
454; CHECK-NEXT: .byte  1
455; CHECK-NEXT: .byte 0
456; CHECK-NEXT: .short 8
457; CHECK-NEXT: .short {{[0-9]+}}
458; CHECK-NEXT: .short 0
459; CHECK-NEXT: .long  0
460; Loc 2: Arg1 in a Register
461; CHECK-NEXT: .byte  1
462; CHECK-NEXT: .byte 0
463; CHECK-NEXT: .short 8
464; CHECK-NEXT: .short {{[0-9]+}}
465; CHECK-NEXT: .short 0
466; CHECK-NEXT: .long  0
467; Loc 3: Arg2 spilled to FP -96
468; CHECK-NEXT: .byte  3
469; CHECK-NEXT: .byte 0
470; CHECK-NEXT: .short 8
471; CHECK-NEXT: .short 31
472; CHECK-NEXT: .short 0
473; CHECK-NEXT: .long 128
474; Loc 4: Arg3 spilled to FP - 88
475; CHECK-NEXT: .byte  3
476; CHECK-NEXT: .byte 0
477; CHECK-NEXT: .short 8
478; CHECK-NEXT: .short 31
479; CHECK-NEXT: .short 0
480; CHECK-NEXT: .long 136
481define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
482entry:
483  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
484},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
485  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
486  ret i64 %result
487}
488
489declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
490declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
491