1; RUN: llc < %s | FileCheck %s
2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; CHECK-LABEL: test:
6; CHECK: {{^}}.L[[test_BEGIN:.*]]:{{$}}
7
8; CHECK-LABEL: property_access1:
9; CHECK: {{^}}.L[[property_access1_BEGIN:.*]]:{{$}}
10
11; CHECK-LABEL: property_access2:
12; CHECK: {{^}}.L[[property_access2_BEGIN:.*]]:{{$}}
13
14; CHECK-LABEL: property_access3:
15; CHECK: {{^}}.L[[property_access3_BEGIN:.*]]:{{$}}
16
17; CHECK-LABEL: anyreg_test1:
18; CHECK: {{^}}.L[[anyreg_test1_BEGIN:.*]]:{{$}}
19
20; CHECK-LABEL: anyreg_test2:
21; CHECK: {{^}}.L[[anyreg_test2_BEGIN:.*]]:{{$}}
22
23; CHECK-LABEL: patchpoint_spilldef:
24; CHECK: {{^}}.L[[patchpoint_spilldef_BEGIN:.*]]:{{$}}
25
26; CHECK-LABEL: patchpoint_spillargs:
27; CHECK: {{^}}.L[[patchpoint_spillargs_BEGIN:.*]]:{{$}}
28
29
30; Stackmap Header: no constants - 6 callsites
31; CHECK-LABEL: .section	.llvm_stackmaps
32; CHECK-NEXT:  __LLVM_StackMaps:
33; Header
34; CHECK-NEXT:   .byte 2
35; CHECK-NEXT:   .byte 0
36; CHECK-NEXT:   .short 0
37; Num Functions
38; CHECK-NEXT:   .long 8
39; Num LargeConstants
40; CHECK-NEXT:   .long 0
41; Num Callsites
42; CHECK-NEXT:   .long 8
43
44; Functions and stack size
45; CHECK-NEXT:   .quad test
46; CHECK-NEXT:   .quad 128
47; CHECK-NEXT:   .quad 1
48; CHECK-NEXT:   .quad property_access1
49; CHECK-NEXT:   .quad 128
50; CHECK-NEXT:   .quad 1
51; CHECK-NEXT:   .quad property_access2
52; CHECK-NEXT:   .quad 128
53; CHECK-NEXT:   .quad 1
54; CHECK-NEXT:   .quad property_access3
55; CHECK-NEXT:   .quad 128
56; CHECK-NEXT:   .quad 1
57; CHECK-NEXT:   .quad anyreg_test1
58; CHECK-NEXT:   .quad 144
59; CHECK-NEXT:   .quad 1
60; CHECK-NEXT:   .quad anyreg_test2
61; CHECK-NEXT:   .quad 144
62; CHECK-NEXT:   .quad 1
63; CHECK-NEXT:   .quad patchpoint_spilldef
64; CHECK-NEXT:   .quad 256
65; CHECK-NEXT:   .quad 1
66; CHECK-NEXT:   .quad patchpoint_spillargs
67; CHECK-NEXT:   .quad 288
68; CHECK-NEXT:   .quad 1
69
70
71; test
72; CHECK:  .long   .L{{.*}}-.L[[test_BEGIN]]
73; CHECK-NEXT:   .short  0
74; 3 locations
75; CHECK-NEXT:   .short  3
76; Loc 0: Register
77; CHECK-NEXT:   .byte 1
78; CHECK-NEXT:   .byte 4
79; CHECK-NEXT:   .short {{[0-9]+}}
80; CHECK-NEXT:   .long 0
81; Loc 1: Register
82; CHECK-NEXT:   .byte 1
83; CHECK-NEXT:   .byte 4
84; CHECK-NEXT:   .short {{[0-9]+}}
85; CHECK-NEXT:   .long 0
86; Loc 2: Constant 3
87; CHECK-NEXT:   .byte 4
88; CHECK-NEXT:   .byte 8
89; CHECK-NEXT:   .short  0
90; CHECK-NEXT:   .long 3
91define i64 @test() nounwind ssp uwtable {
92entry:
93  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 40, i8* null, i32 2, i32 1, i32 2, i64 3)
94  ret i64 0
95}
96
97; property access 1 - %obj is an anyreg call argument and should therefore be in a register
98; CHECK:  .long   .L{{.*}}-.L[[property_access1_BEGIN]]
99; CHECK-NEXT:   .short  0
100; 2 locations
101; CHECK-NEXT:   .short  2
102; Loc 0: Register <-- this is the return register
103; CHECK-NEXT:   .byte 1
104; CHECK-NEXT:   .byte 8
105; CHECK-NEXT:   .short {{[0-9]+}}
106; CHECK-NEXT:   .long 0
107; Loc 1: Register
108; CHECK-NEXT:   .byte 1
109; CHECK-NEXT:   .byte 8
110; CHECK-NEXT:   .short {{[0-9]+}}
111; CHECK-NEXT:   .long 0
112define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
113entry:
114  %f = inttoptr i64 281474417671919 to i8*
115  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 40, i8* %f, i32 1, i8* %obj)
116  ret i64 %ret
117}
118
119; property access 2 - %obj is an anyreg call argument and should therefore be in a register
120; CHECK:  .long   .L{{.*}}-.L[[property_access2_BEGIN]]
121; CHECK-NEXT:   .short  0
122; 2 locations
123; CHECK-NEXT:   .short  2
124; Loc 0: Register <-- this is the return register
125; CHECK-NEXT:   .byte 1
126; CHECK-NEXT:   .byte 8
127; CHECK-NEXT:   .short {{[0-9]+}}
128; CHECK-NEXT:   .long 0
129; Loc 1: Register
130; CHECK-NEXT:   .byte 1
131; CHECK-NEXT:   .byte 8
132; CHECK-NEXT:   .short {{[0-9]+}}
133; CHECK-NEXT:   .long 0
134define i64 @property_access2() nounwind ssp uwtable {
135entry:
136  %obj = alloca i64, align 8
137  %f = inttoptr i64 281474417671919 to i8*
138  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 40, i8* %f, i32 1, i64* %obj)
139  ret i64 %ret
140}
141
142; property access 3 - %obj is a frame index
143; CHECK:  .long   .L{{.*}}-.L[[property_access3_BEGIN]]
144; CHECK-NEXT:   .short  0
145; 2 locations
146; CHECK-NEXT:   .short  2
147; Loc 0: Register <-- this is the return register
148; CHECK-NEXT:   .byte 1
149; CHECK-NEXT:   .byte 8
150; CHECK-NEXT:   .short {{[0-9]+}}
151; CHECK-NEXT:   .long 0
152; Loc 1: Direct FP - 8
153; CHECK-NEXT:   .byte 2
154; CHECK-NEXT:   .byte 8
155; CHECK-NEXT:   .short 31
156; CHECK-NEXT:   .long 112
157define i64 @property_access3() nounwind ssp uwtable {
158entry:
159  %obj = alloca i64, align 8
160  %f = inttoptr i64 281474417671919 to i8*
161  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 40, i8* %f, i32 0, i64* %obj)
162  ret i64 %ret
163}
164
165; anyreg_test1
166; CHECK:  .long   .L{{.*}}-.L[[anyreg_test1_BEGIN]]
167; CHECK-NEXT:   .short  0
168; 14 locations
169; CHECK-NEXT:   .short  14
170; Loc 0: Register <-- this is the return register
171; CHECK-NEXT:   .byte 1
172; CHECK-NEXT:   .byte 8
173; CHECK-NEXT:   .short {{[0-9]+}}
174; CHECK-NEXT:   .long 0
175; Loc 1: Register
176; CHECK-NEXT:   .byte 1
177; CHECK-NEXT:   .byte 8
178; CHECK-NEXT:   .short {{[0-9]+}}
179; CHECK-NEXT:   .long 0
180; Loc 2: Register
181; CHECK-NEXT:   .byte 1
182; CHECK-NEXT:   .byte 8
183; CHECK-NEXT:   .short {{[0-9]+}}
184; CHECK-NEXT:   .long 0
185; Loc 3: Register
186; CHECK-NEXT:   .byte 1
187; CHECK-NEXT:   .byte 8
188; CHECK-NEXT:   .short {{[0-9]+}}
189; CHECK-NEXT:   .long 0
190; Loc 4: Register
191; CHECK-NEXT:   .byte 1
192; CHECK-NEXT:   .byte 8
193; CHECK-NEXT:   .short {{[0-9]+}}
194; CHECK-NEXT:   .long 0
195; Loc 5: Register
196; CHECK-NEXT:   .byte 1
197; CHECK-NEXT:   .byte 8
198; CHECK-NEXT:   .short {{[0-9]+}}
199; CHECK-NEXT:   .long 0
200; Loc 6: Register
201; CHECK-NEXT:   .byte 1
202; CHECK-NEXT:   .byte 8
203; CHECK-NEXT:   .short {{[0-9]+}}
204; CHECK-NEXT:   .long 0
205; Loc 7: Register
206; CHECK-NEXT:   .byte 1
207; CHECK-NEXT:   .byte 8
208; CHECK-NEXT:   .short {{[0-9]+}}
209; CHECK-NEXT:   .long 0
210; Loc 8: Register
211; CHECK-NEXT:   .byte 1
212; CHECK-NEXT:   .byte 8
213; CHECK-NEXT:   .short {{[0-9]+}}
214; CHECK-NEXT:   .long 0
215; Loc 9: Register
216; CHECK-NEXT:   .byte 1
217; CHECK-NEXT:   .byte 8
218; CHECK-NEXT:   .short {{[0-9]+}}
219; CHECK-NEXT:   .long 0
220; Loc 10: Register
221; CHECK-NEXT:   .byte 1
222; CHECK-NEXT:   .byte 8
223; CHECK-NEXT:   .short {{[0-9]+}}
224; CHECK-NEXT:   .long 0
225; Loc 11: Register
226; CHECK-NEXT:   .byte 1
227; CHECK-NEXT:   .byte 8
228; CHECK-NEXT:   .short {{[0-9]+}}
229; CHECK-NEXT:   .long 0
230; Loc 12: Register
231; CHECK-NEXT:   .byte 1
232; CHECK-NEXT:   .byte 8
233; CHECK-NEXT:   .short {{[0-9]+}}
234; CHECK-NEXT:   .long 0
235; Loc 13: Register
236; CHECK-NEXT:   .byte 1
237; CHECK-NEXT:   .byte 8
238; CHECK-NEXT:   .short {{[0-9]+}}
239; CHECK-NEXT:   .long 0
240define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
241entry:
242  %f = inttoptr i64 281474417671919 to i8*
243  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 40, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
244  ret i64 %ret
245}
246
247; anyreg_test2
248; CHECK:  .long   .L{{.*}}-.L[[anyreg_test2_BEGIN]]
249; CHECK-NEXT:   .short  0
250; 14 locations
251; CHECK-NEXT:   .short  14
252; Loc 0: Register <-- this is the return register
253; CHECK-NEXT:   .byte 1
254; CHECK-NEXT:   .byte 8
255; CHECK-NEXT:   .short {{[0-9]+}}
256; CHECK-NEXT:   .long 0
257; Loc 1: Register
258; CHECK-NEXT:   .byte 1
259; CHECK-NEXT:   .byte 8
260; CHECK-NEXT:   .short {{[0-9]+}}
261; CHECK-NEXT:   .long 0
262; Loc 2: Register
263; CHECK-NEXT:   .byte 1
264; CHECK-NEXT:   .byte 8
265; CHECK-NEXT:   .short {{[0-9]+}}
266; CHECK-NEXT:   .long 0
267; Loc 3: Register
268; CHECK-NEXT:   .byte 1
269; CHECK-NEXT:   .byte 8
270; CHECK-NEXT:   .short {{[0-9]+}}
271; CHECK-NEXT:   .long 0
272; Loc 4: Register
273; CHECK-NEXT:   .byte 1
274; CHECK-NEXT:   .byte 8
275; CHECK-NEXT:   .short {{[0-9]+}}
276; CHECK-NEXT:   .long 0
277; Loc 5: Register
278; CHECK-NEXT:   .byte 1
279; CHECK-NEXT:   .byte 8
280; CHECK-NEXT:   .short {{[0-9]+}}
281; CHECK-NEXT:   .long 0
282; Loc 6: Register
283; CHECK-NEXT:   .byte 1
284; CHECK-NEXT:   .byte 8
285; CHECK-NEXT:   .short {{[0-9]+}}
286; CHECK-NEXT:   .long 0
287; Loc 7: Register
288; CHECK-NEXT:   .byte 1
289; CHECK-NEXT:   .byte 8
290; CHECK-NEXT:   .short {{[0-9]+}}
291; CHECK-NEXT:   .long 0
292; Loc 8: Register
293; CHECK-NEXT:   .byte 1
294; CHECK-NEXT:   .byte 8
295; CHECK-NEXT:   .short {{[0-9]+}}
296; CHECK-NEXT:   .long 0
297; Loc 9: Register
298; CHECK-NEXT:   .byte 1
299; CHECK-NEXT:   .byte 8
300; CHECK-NEXT:   .short {{[0-9]+}}
301; CHECK-NEXT:   .long 0
302; Loc 10: Register
303; CHECK-NEXT:   .byte 1
304; CHECK-NEXT:   .byte 8
305; CHECK-NEXT:   .short {{[0-9]+}}
306; CHECK-NEXT:   .long 0
307; Loc 11: Register
308; CHECK-NEXT:   .byte 1
309; CHECK-NEXT:   .byte 8
310; CHECK-NEXT:   .short {{[0-9]+}}
311; CHECK-NEXT:   .long 0
312; Loc 12: Register
313; CHECK-NEXT:   .byte 1
314; CHECK-NEXT:   .byte 8
315; CHECK-NEXT:   .short {{[0-9]+}}
316; CHECK-NEXT:   .long 0
317; Loc 13: Register
318; CHECK-NEXT:   .byte 1
319; CHECK-NEXT:   .byte 8
320; CHECK-NEXT:   .short {{[0-9]+}}
321; CHECK-NEXT:   .long 0
322define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable {
323entry:
324  %f = inttoptr i64 281474417671919 to i8*
325  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 40, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13)
326  ret i64 %ret
327}
328
329; Test spilling the return value of an anyregcc call.
330;
331; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
332;
333; CHECK: .long .L{{.*}}-.L[[patchpoint_spilldef_BEGIN]]
334; CHECK-NEXT: .short 0
335; CHECK-NEXT: .short 3
336; Loc 0: Register (some register that will be spilled to the stack)
337; CHECK-NEXT: .byte  1
338; CHECK-NEXT: .byte  8
339; CHECK-NEXT: .short {{[0-9]+}}
340; CHECK-NEXT: .long  0
341; Loc 1: Register
342; CHECK-NEXT: .byte  1
343; CHECK-NEXT: .byte  8
344; CHECK-NEXT: .short {{[0-9]+}}
345; CHECK-NEXT: .long  0
346; Loc 1: Register
347; CHECK-NEXT: .byte  1
348; CHECK-NEXT: .byte  8
349; CHECK-NEXT: .short {{[0-9]+}}
350; CHECK-NEXT: .long  0
351define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
352entry:
353  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
354  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
355},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
356  ret i64 %result
357}
358
359; Test spilling the arguments of an anyregcc call.
360;
361; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
362;
363; CHECK: .long .L{{.*}}-.L[[patchpoint_spillargs_BEGIN]]
364; CHECK-NEXT: .short 0
365; CHECK-NEXT: .short 5
366; Loc 0: Return a register
367; CHECK-NEXT: .byte  1
368; CHECK-NEXT: .byte  8
369; CHECK-NEXT: .short {{[0-9]+}}
370; CHECK-NEXT: .long  0
371; Loc 1: Arg0 in a Register
372; CHECK-NEXT: .byte  1
373; CHECK-NEXT: .byte  8
374; CHECK-NEXT: .short {{[0-9]+}}
375; CHECK-NEXT: .long  0
376; Loc 2: Arg1 in a Register
377; CHECK-NEXT: .byte  1
378; CHECK-NEXT: .byte  8
379; CHECK-NEXT: .short {{[0-9]+}}
380; CHECK-NEXT: .long  0
381; Loc 3: Arg2 spilled to FP -96
382; CHECK-NEXT: .byte  3
383; CHECK-NEXT: .byte  8
384; CHECK-NEXT: .short 31
385; CHECK-NEXT: .long 128
386; Loc 4: Arg3 spilled to FP - 88
387; CHECK-NEXT: .byte  3
388; CHECK-NEXT: .byte  8
389; CHECK-NEXT: .short 31
390; CHECK-NEXT: .long 136
391define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
392entry:
393  tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17
394},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
395  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 40, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
396  ret i64 %result
397}
398
399declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
400declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
401