1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-LE
3; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-BE
4; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR8 -implicit-check-not vabsdu
5; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR7 -implicit-check-not vmaxsd
6
7define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
8; CHECK-PWR9-LABEL: simple_absv_32:
9; CHECK-PWR9:       # %bb.0: # %entry
10; CHECK-PWR9-NEXT:    vnegw v3, v2
11; CHECK-PWR9-NEXT:    vmaxsw v2, v2, v3
12; CHECK-PWR9-NEXT:    blr
13;
14; CHECK-PWR78-LABEL: simple_absv_32:
15; CHECK-PWR78:       # %bb.0: # %entry
16; CHECK-PWR78-NEXT:    xxlxor v3, v3, v3
17; CHECK-PWR78-NEXT:    vsubuwm v3, v3, v2
18; CHECK-PWR78-NEXT:    vmaxsw v2, v2, v3
19; CHECK-PWR78-NEXT:    blr
20entry:
21  %sub.i = sub <4 x i32> zeroinitializer, %a
22  %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
23  ret <4 x i32> %0
24}
25
26define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {
27; CHECK-PWR9-LABEL: simple_absv_32_swap:
28; CHECK-PWR9:       # %bb.0: # %entry
29; CHECK-PWR9-NEXT:    vnegw v3, v2
30; CHECK-PWR9-NEXT:    vmaxsw v2, v2, v3
31; CHECK-PWR9-NEXT:    blr
32;
33; CHECK-PWR78-LABEL: simple_absv_32_swap:
34; CHECK-PWR78:       # %bb.0: # %entry
35; CHECK-PWR78-NEXT:    xxlxor v3, v3, v3
36; CHECK-PWR78-NEXT:    vsubuwm v3, v3, v2
37; CHECK-PWR78-NEXT:    vmaxsw v2, v3, v2
38; CHECK-PWR78-NEXT:    blr
39entry:
40  %sub.i = sub <4 x i32> zeroinitializer, %a
41  %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
42  ret <4 x i32> %0
43}
44
45define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr {
46; CHECK-LABEL: simple_absv_16:
47; CHECK:       # %bb.0: # %entry
48; CHECK-NEXT:    xxlxor v3, v3, v3
49; CHECK-NEXT:    vsubuhm v3, v3, v2
50; CHECK-NEXT:    vmaxsh v2, v2, v3
51; CHECK-NEXT:    blr
52entry:
53  %sub.i = sub <8 x i16> zeroinitializer, %a
54  %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
55  ret <8 x i16> %0
56}
57
58define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {
59; CHECK-LABEL: simple_absv_8:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    xxlxor v3, v3, v3
62; CHECK-NEXT:    vsububm v3, v3, v2
63; CHECK-NEXT:    vmaxsb v2, v2, v3
64; CHECK-NEXT:    blr
65entry:
66  %sub.i = sub <16 x i8> zeroinitializer, %a
67  %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)
68  ret <16 x i8> %0
69}
70
71; v2i64 vmax isn't avaiable on pwr7
72define <2 x i64> @sub_absv_64(<2 x i64> %a, <2 x i64> %b) local_unnamed_addr {
73; CHECK-PWR9-LABEL: sub_absv_64:
74; CHECK-PWR9:       # %bb.0: # %entry
75; CHECK-PWR9-NEXT:    vsubudm v2, v2, v3
76; CHECK-PWR9-NEXT:    vnegd v3, v2
77; CHECK-PWR9-NEXT:    vmaxsd v2, v2, v3
78; CHECK-PWR9-NEXT:    blr
79;
80; CHECK-PWR8-LABEL: sub_absv_64:
81; CHECK-PWR8:       # %bb.0: # %entry
82; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
83; CHECK-PWR8-NEXT:    vsubudm v2, v2, v3
84; CHECK-PWR8-NEXT:    vsubudm v3, v4, v2
85; CHECK-PWR8-NEXT:    vmaxsd v2, v2, v3
86; CHECK-PWR8-NEXT:    blr
87;
88; CHECK-PWR7-LABEL: sub_absv_64:
89; CHECK-PWR7:       # %bb.0: # %entry
90; CHECK-PWR7-NEXT:    addi r3, r1, -48
91; CHECK-PWR7-NEXT:    addi r4, r1, -32
92; CHECK-PWR7-NEXT:    stxvd2x v2, 0, r3
93; CHECK-PWR7-NEXT:    stxvd2x v3, 0, r4
94; CHECK-PWR7-NEXT:    ld r3, -40(r1)
95; CHECK-PWR7-NEXT:    ld r4, -24(r1)
96; CHECK-PWR7-NEXT:    ld r5, -48(r1)
97; CHECK-PWR7-NEXT:    ld r6, -32(r1)
98; CHECK-PWR7-NEXT:    sub r3, r3, r4
99; CHECK-PWR7-NEXT:    sub r4, r5, r6
100; CHECK-PWR7-NEXT:    sradi r5, r3, 63
101; CHECK-PWR7-NEXT:    sradi r6, r4, 63
102; CHECK-PWR7-NEXT:    xor r3, r3, r5
103; CHECK-PWR7-NEXT:    xor r4, r4, r6
104; CHECK-PWR7-NEXT:    sub r3, r3, r5
105; CHECK-PWR7-NEXT:    sub r4, r4, r6
106; CHECK-PWR7-NEXT:    std r3, -8(r1)
107; CHECK-PWR7-NEXT:    addi r3, r1, -16
108; CHECK-PWR7-NEXT:    std r4, -16(r1)
109; CHECK-PWR7-NEXT:    lxvd2x v2, 0, r3
110; CHECK-PWR7-NEXT:    blr
111entry:
112  %0 = sub nsw <2 x i64> %a, %b
113  %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>
114  %2 = sub <2 x i64> zeroinitializer, %0
115  %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2
116  ret <2 x i64> %3
117}
118
119; The select pattern can only be detected for v4i32.
120define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
121; CHECK-PWR9-LABEL: sub_absv_32:
122; CHECK-PWR9:       # %bb.0: # %entry
123; CHECK-PWR9-NEXT:    xvnegsp v3, v3
124; CHECK-PWR9-NEXT:    xvnegsp v2, v2
125; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
126; CHECK-PWR9-NEXT:    blr
127;
128; CHECK-PWR78-LABEL: sub_absv_32:
129; CHECK-PWR78:       # %bb.0: # %entry
130; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
131; CHECK-PWR78-NEXT:    vsubuwm v2, v2, v3
132; CHECK-PWR78-NEXT:    vsubuwm v3, v4, v2
133; CHECK-PWR78-NEXT:    vmaxsw v2, v2, v3
134; CHECK-PWR78-NEXT:    blr
135entry:
136  %0 = sub nsw <4 x i32> %a, %b
137  %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>
138  %2 = sub <4 x i32> zeroinitializer, %0
139  %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
140  ret <4 x i32> %3
141}
142
143define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
144; CHECK-PWR9-LABEL: sub_absv_16:
145; CHECK-PWR9:       # %bb.0: # %entry
146; CHECK-PWR9-NEXT:    vsubuhm v2, v2, v3
147; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
148; CHECK-PWR9-NEXT:    vsubuhm v3, v3, v2
149; CHECK-PWR9-NEXT:    vmaxsh v2, v2, v3
150; CHECK-PWR9-NEXT:    blr
151;
152; CHECK-PWR78-LABEL: sub_absv_16:
153; CHECK-PWR78:       # %bb.0: # %entry
154; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
155; CHECK-PWR78-NEXT:    vsubuhm v2, v2, v3
156; CHECK-PWR78-NEXT:    vsubuhm v3, v4, v2
157; CHECK-PWR78-NEXT:    vmaxsh v2, v2, v3
158; CHECK-PWR78-NEXT:    blr
159entry:
160  %0 = sub nsw <8 x i16> %a, %b
161  %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
162  %2 = sub <8 x i16> zeroinitializer, %0
163  %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2
164  ret <8 x i16> %3
165}
166
167define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
168; CHECK-PWR9-LABEL: sub_absv_8:
169; CHECK-PWR9:       # %bb.0: # %entry
170; CHECK-PWR9-NEXT:    vsububm v2, v2, v3
171; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
172; CHECK-PWR9-NEXT:    vsububm v3, v3, v2
173; CHECK-PWR9-NEXT:    vmaxsb v2, v2, v3
174; CHECK-PWR9-NEXT:    blr
175;
176; CHECK-PWR78-LABEL: sub_absv_8:
177; CHECK-PWR78:       # %bb.0: # %entry
178; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
179; CHECK-PWR78-NEXT:    vsububm v2, v2, v3
180; CHECK-PWR78-NEXT:    vsububm v3, v4, v2
181; CHECK-PWR78-NEXT:    vmaxsb v2, v2, v3
182; CHECK-PWR78-NEXT:    blr
183entry:
184  %0 = sub nsw <16 x i8> %a, %b
185  %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
186  %2 = sub <16 x i8> zeroinitializer, %0
187  %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2
188  ret <16 x i8> %3
189}
190
191; FIXME: This does not produce the ISD::ABS that we are looking for.
192; We should fix the missing canonicalization.
193; We do manage to find the word version of ABS but not the halfword.
194; Threfore, we end up doing more work than is required with a pair of abs for word
195;  instead of just one for the halfword.
196define <8 x i16> @sub_absv_16_ext(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
197; CHECK-PWR9-LABEL: sub_absv_16_ext:
198; CHECK-PWR9:       # %bb.0: # %entry
199; CHECK-PWR9-NEXT:    vmrghh v4, v2, v2
200; CHECK-PWR9-NEXT:    vmrglh v2, v2, v2
201; CHECK-PWR9-NEXT:    vmrghh v5, v3, v3
202; CHECK-PWR9-NEXT:    vmrglh v3, v3, v3
203; CHECK-PWR9-NEXT:    vextsh2w v2, v2
204; CHECK-PWR9-NEXT:    vextsh2w v3, v3
205; CHECK-PWR9-NEXT:    vextsh2w v4, v4
206; CHECK-PWR9-NEXT:    vextsh2w v5, v5
207; CHECK-PWR9-NEXT:    xvnegsp v3, v3
208; CHECK-PWR9-NEXT:    xvnegsp v2, v2
209; CHECK-PWR9-NEXT:    xvnegsp v4, v4
210; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
211; CHECK-PWR9-NEXT:    xvnegsp v3, v5
212; CHECK-PWR9-NEXT:    vabsduw v3, v4, v3
213; CHECK-PWR9-NEXT:    vpkuwum v2, v3, v2
214; CHECK-PWR9-NEXT:    blr
215;
216; CHECK-PWR8-LABEL: sub_absv_16_ext:
217; CHECK-PWR8:       # %bb.0: # %entry
218; CHECK-PWR8-NEXT:    vmrglh v5, v2, v2
219; CHECK-PWR8-NEXT:    vspltisw v4, 8
220; CHECK-PWR8-NEXT:    vmrghh v2, v2, v2
221; CHECK-PWR8-NEXT:    vmrglh v0, v3, v3
222; CHECK-PWR8-NEXT:    vmrghh v3, v3, v3
223; CHECK-PWR8-NEXT:    vadduwm v4, v4, v4
224; CHECK-PWR8-NEXT:    vslw v5, v5, v4
225; CHECK-PWR8-NEXT:    vslw v2, v2, v4
226; CHECK-PWR8-NEXT:    vslw v0, v0, v4
227; CHECK-PWR8-NEXT:    vslw v3, v3, v4
228; CHECK-PWR8-NEXT:    vsraw v5, v5, v4
229; CHECK-PWR8-NEXT:    vsraw v2, v2, v4
230; CHECK-PWR8-NEXT:    vsraw v0, v0, v4
231; CHECK-PWR8-NEXT:    vsraw v3, v3, v4
232; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
233; CHECK-PWR8-NEXT:    vsubuwm v5, v5, v0
234; CHECK-PWR8-NEXT:    vsubuwm v2, v2, v3
235; CHECK-PWR8-NEXT:    vsubuwm v3, v4, v5
236; CHECK-PWR8-NEXT:    vsubuwm v4, v4, v2
237; CHECK-PWR8-NEXT:    vmaxsw v3, v5, v3
238; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v4
239; CHECK-PWR8-NEXT:    vpkuwum v2, v2, v3
240; CHECK-PWR8-NEXT:    blr
241;
242; CHECK-PWR7-LABEL: sub_absv_16_ext:
243; CHECK-PWR7:       # %bb.0: # %entry
244; CHECK-PWR7-NEXT:    vmrglh v5, v2, v2
245; CHECK-PWR7-NEXT:    vmrghh v2, v2, v2
246; CHECK-PWR7-NEXT:    vmrglh v0, v3, v3
247; CHECK-PWR7-NEXT:    vmrghh v3, v3, v3
248; CHECK-PWR7-NEXT:    vspltisw v4, 8
249; CHECK-PWR7-NEXT:    vadduwm v4, v4, v4
250; CHECK-PWR7-NEXT:    vslw v5, v5, v4
251; CHECK-PWR7-NEXT:    vslw v2, v2, v4
252; CHECK-PWR7-NEXT:    vslw v0, v0, v4
253; CHECK-PWR7-NEXT:    vslw v3, v3, v4
254; CHECK-PWR7-NEXT:    vsraw v5, v5, v4
255; CHECK-PWR7-NEXT:    vsraw v2, v2, v4
256; CHECK-PWR7-NEXT:    vsraw v0, v0, v4
257; CHECK-PWR7-NEXT:    vsraw v3, v3, v4
258; CHECK-PWR7-NEXT:    xxlxor v4, v4, v4
259; CHECK-PWR7-NEXT:    vsubuwm v5, v5, v0
260; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
261; CHECK-PWR7-NEXT:    vsubuwm v3, v4, v5
262; CHECK-PWR7-NEXT:    vsubuwm v4, v4, v2
263; CHECK-PWR7-NEXT:    vmaxsw v3, v5, v3
264; CHECK-PWR7-NEXT:    vmaxsw v2, v2, v4
265; CHECK-PWR7-NEXT:    vpkuwum v2, v2, v3
266; CHECK-PWR7-NEXT:    blr
267entry:
268  %0 = sext <8 x i16> %a to <8 x i32>
269  %1 = sext <8 x i16> %b to <8 x i32>
270  %2 = sub nsw <8 x i32> %0, %1
271  %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
272  %4 = sub nsw <8 x i32> zeroinitializer, %2
273  %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4
274  %6 = trunc <8 x i32> %5 to <8 x i16>
275  ret <8 x i16> %6
276}
277
278; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly!
279; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8.
280; Function Attrs: norecurse nounwind readnone
281define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
282; CHECK-PWR9-LE-LABEL: sub_absv_8_ext:
283; CHECK-PWR9-LE:       # %bb.0: # %entry
284; CHECK-PWR9-LE-NEXT:    li r3, 0
285; CHECK-PWR9-LE-NEXT:    li r5, 2
286; CHECK-PWR9-LE-NEXT:    li r4, 1
287; CHECK-PWR9-LE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
288; CHECK-PWR9-LE-NEXT:    vextubrx r6, r3, v2
289; CHECK-PWR9-LE-NEXT:    vextubrx r3, r3, v3
290; CHECK-PWR9-LE-NEXT:    vextubrx r8, r5, v2
291; CHECK-PWR9-LE-NEXT:    vextubrx r5, r5, v3
292; CHECK-PWR9-LE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
293; CHECK-PWR9-LE-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
294; CHECK-PWR9-LE-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
295; CHECK-PWR9-LE-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
296; CHECK-PWR9-LE-NEXT:    std r25, -56(r1) # 8-byte Folded Spill
297; CHECK-PWR9-LE-NEXT:    clrlwi r6, r6, 24
298; CHECK-PWR9-LE-NEXT:    clrlwi r3, r3, 24
299; CHECK-PWR9-LE-NEXT:    vextubrx r7, r4, v2
300; CHECK-PWR9-LE-NEXT:    vextubrx r4, r4, v3
301; CHECK-PWR9-LE-NEXT:    clrlwi r8, r8, 24
302; CHECK-PWR9-LE-NEXT:    sub r3, r6, r3
303; CHECK-PWR9-LE-NEXT:    clrlwi r5, r5, 24
304; CHECK-PWR9-LE-NEXT:    clrlwi r7, r7, 24
305; CHECK-PWR9-LE-NEXT:    clrlwi r4, r4, 24
306; CHECK-PWR9-LE-NEXT:    sub r5, r8, r5
307; CHECK-PWR9-LE-NEXT:    sub r4, r7, r4
308; CHECK-PWR9-LE-NEXT:    srawi r6, r3, 31
309; CHECK-PWR9-LE-NEXT:    srawi r7, r4, 31
310; CHECK-PWR9-LE-NEXT:    xor r3, r3, r6
311; CHECK-PWR9-LE-NEXT:    xor r4, r4, r7
312; CHECK-PWR9-LE-NEXT:    sub r6, r3, r6
313; CHECK-PWR9-LE-NEXT:    srawi r3, r5, 31
314; CHECK-PWR9-LE-NEXT:    sub r4, r4, r7
315; CHECK-PWR9-LE-NEXT:    xor r5, r5, r3
316; CHECK-PWR9-LE-NEXT:    sub r3, r5, r3
317; CHECK-PWR9-LE-NEXT:    li r5, 3
318; CHECK-PWR9-LE-NEXT:    vextubrx r7, r5, v2
319; CHECK-PWR9-LE-NEXT:    vextubrx r5, r5, v3
320; CHECK-PWR9-LE-NEXT:    clrlwi r7, r7, 24
321; CHECK-PWR9-LE-NEXT:    clrlwi r5, r5, 24
322; CHECK-PWR9-LE-NEXT:    sub r5, r7, r5
323; CHECK-PWR9-LE-NEXT:    srawi r7, r5, 31
324; CHECK-PWR9-LE-NEXT:    xor r5, r5, r7
325; CHECK-PWR9-LE-NEXT:    sub r5, r5, r7
326; CHECK-PWR9-LE-NEXT:    li r7, 4
327; CHECK-PWR9-LE-NEXT:    vextubrx r8, r7, v2
328; CHECK-PWR9-LE-NEXT:    vextubrx r7, r7, v3
329; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r5
330; CHECK-PWR9-LE-NEXT:    clrlwi r8, r8, 24
331; CHECK-PWR9-LE-NEXT:    clrlwi r7, r7, 24
332; CHECK-PWR9-LE-NEXT:    sub r7, r8, r7
333; CHECK-PWR9-LE-NEXT:    srawi r8, r7, 31
334; CHECK-PWR9-LE-NEXT:    xor r7, r7, r8
335; CHECK-PWR9-LE-NEXT:    sub r7, r7, r8
336; CHECK-PWR9-LE-NEXT:    li r8, 5
337; CHECK-PWR9-LE-NEXT:    vextubrx r9, r8, v2
338; CHECK-PWR9-LE-NEXT:    vextubrx r8, r8, v3
339; CHECK-PWR9-LE-NEXT:    clrlwi r9, r9, 24
340; CHECK-PWR9-LE-NEXT:    clrlwi r8, r8, 24
341; CHECK-PWR9-LE-NEXT:    sub r8, r9, r8
342; CHECK-PWR9-LE-NEXT:    srawi r9, r8, 31
343; CHECK-PWR9-LE-NEXT:    xor r8, r8, r9
344; CHECK-PWR9-LE-NEXT:    sub r8, r8, r9
345; CHECK-PWR9-LE-NEXT:    li r9, 6
346; CHECK-PWR9-LE-NEXT:    vextubrx r10, r9, v2
347; CHECK-PWR9-LE-NEXT:    vextubrx r9, r9, v3
348; CHECK-PWR9-LE-NEXT:    clrlwi r10, r10, 24
349; CHECK-PWR9-LE-NEXT:    clrlwi r9, r9, 24
350; CHECK-PWR9-LE-NEXT:    sub r9, r10, r9
351; CHECK-PWR9-LE-NEXT:    srawi r10, r9, 31
352; CHECK-PWR9-LE-NEXT:    xor r9, r9, r10
353; CHECK-PWR9-LE-NEXT:    sub r9, r9, r10
354; CHECK-PWR9-LE-NEXT:    li r10, 7
355; CHECK-PWR9-LE-NEXT:    vextubrx r11, r10, v2
356; CHECK-PWR9-LE-NEXT:    vextubrx r10, r10, v3
357; CHECK-PWR9-LE-NEXT:    clrlwi r11, r11, 24
358; CHECK-PWR9-LE-NEXT:    clrlwi r10, r10, 24
359; CHECK-PWR9-LE-NEXT:    sub r10, r11, r10
360; CHECK-PWR9-LE-NEXT:    srawi r11, r10, 31
361; CHECK-PWR9-LE-NEXT:    xor r10, r10, r11
362; CHECK-PWR9-LE-NEXT:    sub r10, r10, r11
363; CHECK-PWR9-LE-NEXT:    li r11, 8
364; CHECK-PWR9-LE-NEXT:    vextubrx r12, r11, v2
365; CHECK-PWR9-LE-NEXT:    vextubrx r11, r11, v3
366; CHECK-PWR9-LE-NEXT:    mtvsrd v5, r10
367; CHECK-PWR9-LE-NEXT:    clrlwi r12, r12, 24
368; CHECK-PWR9-LE-NEXT:    clrlwi r11, r11, 24
369; CHECK-PWR9-LE-NEXT:    sub r11, r12, r11
370; CHECK-PWR9-LE-NEXT:    srawi r12, r11, 31
371; CHECK-PWR9-LE-NEXT:    xor r11, r11, r12
372; CHECK-PWR9-LE-NEXT:    sub r11, r11, r12
373; CHECK-PWR9-LE-NEXT:    li r12, 9
374; CHECK-PWR9-LE-NEXT:    vextubrx r0, r12, v2
375; CHECK-PWR9-LE-NEXT:    vextubrx r12, r12, v3
376; CHECK-PWR9-LE-NEXT:    clrlwi r0, r0, 24
377; CHECK-PWR9-LE-NEXT:    clrlwi r12, r12, 24
378; CHECK-PWR9-LE-NEXT:    sub r12, r0, r12
379; CHECK-PWR9-LE-NEXT:    srawi r0, r12, 31
380; CHECK-PWR9-LE-NEXT:    xor r12, r12, r0
381; CHECK-PWR9-LE-NEXT:    sub r12, r12, r0
382; CHECK-PWR9-LE-NEXT:    li r0, 10
383; CHECK-PWR9-LE-NEXT:    vextubrx r30, r0, v2
384; CHECK-PWR9-LE-NEXT:    vextubrx r0, r0, v3
385; CHECK-PWR9-LE-NEXT:    clrlwi r30, r30, 24
386; CHECK-PWR9-LE-NEXT:    clrlwi r0, r0, 24
387; CHECK-PWR9-LE-NEXT:    sub r0, r30, r0
388; CHECK-PWR9-LE-NEXT:    srawi r30, r0, 31
389; CHECK-PWR9-LE-NEXT:    xor r0, r0, r30
390; CHECK-PWR9-LE-NEXT:    sub r0, r0, r30
391; CHECK-PWR9-LE-NEXT:    li r30, 11
392; CHECK-PWR9-LE-NEXT:    vextubrx r29, r30, v2
393; CHECK-PWR9-LE-NEXT:    vextubrx r30, r30, v3
394; CHECK-PWR9-LE-NEXT:    clrlwi r29, r29, 24
395; CHECK-PWR9-LE-NEXT:    clrlwi r30, r30, 24
396; CHECK-PWR9-LE-NEXT:    sub r30, r29, r30
397; CHECK-PWR9-LE-NEXT:    srawi r29, r30, 31
398; CHECK-PWR9-LE-NEXT:    xor r30, r30, r29
399; CHECK-PWR9-LE-NEXT:    sub r30, r30, r29
400; CHECK-PWR9-LE-NEXT:    li r29, 12
401; CHECK-PWR9-LE-NEXT:    vextubrx r28, r29, v2
402; CHECK-PWR9-LE-NEXT:    vextubrx r29, r29, v3
403; CHECK-PWR9-LE-NEXT:    clrlwi r28, r28, 24
404; CHECK-PWR9-LE-NEXT:    clrlwi r29, r29, 24
405; CHECK-PWR9-LE-NEXT:    sub r29, r28, r29
406; CHECK-PWR9-LE-NEXT:    srawi r28, r29, 31
407; CHECK-PWR9-LE-NEXT:    xor r29, r29, r28
408; CHECK-PWR9-LE-NEXT:    sub r29, r29, r28
409; CHECK-PWR9-LE-NEXT:    li r28, 13
410; CHECK-PWR9-LE-NEXT:    vextubrx r27, r28, v2
411; CHECK-PWR9-LE-NEXT:    vextubrx r28, r28, v3
412; CHECK-PWR9-LE-NEXT:    clrlwi r27, r27, 24
413; CHECK-PWR9-LE-NEXT:    clrlwi r28, r28, 24
414; CHECK-PWR9-LE-NEXT:    sub r28, r27, r28
415; CHECK-PWR9-LE-NEXT:    srawi r27, r28, 31
416; CHECK-PWR9-LE-NEXT:    xor r28, r28, r27
417; CHECK-PWR9-LE-NEXT:    sub r28, r28, r27
418; CHECK-PWR9-LE-NEXT:    li r27, 14
419; CHECK-PWR9-LE-NEXT:    vextubrx r26, r27, v2
420; CHECK-PWR9-LE-NEXT:    vextubrx r27, r27, v3
421; CHECK-PWR9-LE-NEXT:    clrlwi r26, r26, 24
422; CHECK-PWR9-LE-NEXT:    clrlwi r27, r27, 24
423; CHECK-PWR9-LE-NEXT:    sub r27, r26, r27
424; CHECK-PWR9-LE-NEXT:    srawi r26, r27, 31
425; CHECK-PWR9-LE-NEXT:    xor r27, r27, r26
426; CHECK-PWR9-LE-NEXT:    sub r27, r27, r26
427; CHECK-PWR9-LE-NEXT:    li r26, 15
428; CHECK-PWR9-LE-NEXT:    vextubrx r25, r26, v2
429; CHECK-PWR9-LE-NEXT:    vextubrx r26, r26, v3
430; CHECK-PWR9-LE-NEXT:    mtvsrd v2, r6
431; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r4
432; CHECK-PWR9-LE-NEXT:    vmrghb v2, v3, v2
433; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r3
434; CHECK-PWR9-LE-NEXT:    clrlwi r25, r25, 24
435; CHECK-PWR9-LE-NEXT:    clrlwi r26, r26, 24
436; CHECK-PWR9-LE-NEXT:    vmrghb v3, v4, v3
437; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r8
438; CHECK-PWR9-LE-NEXT:    sub r26, r25, r26
439; CHECK-PWR9-LE-NEXT:    vmrglh v2, v3, v2
440; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r7
441; CHECK-PWR9-LE-NEXT:    srawi r25, r26, 31
442; CHECK-PWR9-LE-NEXT:    vmrghb v3, v4, v3
443; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r9
444; CHECK-PWR9-LE-NEXT:    xor r26, r26, r25
445; CHECK-PWR9-LE-NEXT:    vmrghb v4, v5, v4
446; CHECK-PWR9-LE-NEXT:    sub r26, r26, r25
447; CHECK-PWR9-LE-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
448; CHECK-PWR9-LE-NEXT:    mtvsrd v5, r26
449; CHECK-PWR9-LE-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
450; CHECK-PWR9-LE-NEXT:    vmrglh v3, v4, v3
451; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r30
452; CHECK-PWR9-LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
453; CHECK-PWR9-LE-NEXT:    xxmrglw vs0, v3, v2
454; CHECK-PWR9-LE-NEXT:    mtvsrd v2, r11
455; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r12
456; CHECK-PWR9-LE-NEXT:    vmrghb v2, v3, v2
457; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r0
458; CHECK-PWR9-LE-NEXT:    vmrghb v3, v4, v3
459; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r28
460; CHECK-PWR9-LE-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
461; CHECK-PWR9-LE-NEXT:    vmrglh v2, v3, v2
462; CHECK-PWR9-LE-NEXT:    mtvsrd v3, r29
463; CHECK-PWR9-LE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
464; CHECK-PWR9-LE-NEXT:    vmrghb v3, v4, v3
465; CHECK-PWR9-LE-NEXT:    mtvsrd v4, r27
466; CHECK-PWR9-LE-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
467; CHECK-PWR9-LE-NEXT:    vmrghb v4, v5, v4
468; CHECK-PWR9-LE-NEXT:    vmrglh v3, v4, v3
469; CHECK-PWR9-LE-NEXT:    xxmrglw vs1, v3, v2
470; CHECK-PWR9-LE-NEXT:    xxmrgld v2, vs1, vs0
471; CHECK-PWR9-LE-NEXT:    blr
472;
473; CHECK-PWR9-BE-LABEL: sub_absv_8_ext:
474; CHECK-PWR9-BE:       # %bb.0: # %entry
475; CHECK-PWR9-BE-NEXT:    li r3, 0
476; CHECK-PWR9-BE-NEXT:    li r4, 1
477; CHECK-PWR9-BE-NEXT:    li r5, 2
478; CHECK-PWR9-BE-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
479; CHECK-PWR9-BE-NEXT:    vextublx r6, r3, v2
480; CHECK-PWR9-BE-NEXT:    vextublx r3, r3, v3
481; CHECK-PWR9-BE-NEXT:    vextublx r7, r4, v2
482; CHECK-PWR9-BE-NEXT:    vextublx r4, r4, v3
483; CHECK-PWR9-BE-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
484; CHECK-PWR9-BE-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
485; CHECK-PWR9-BE-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
486; CHECK-PWR9-BE-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
487; CHECK-PWR9-BE-NEXT:    std r25, -56(r1) # 8-byte Folded Spill
488; CHECK-PWR9-BE-NEXT:    clrlwi r6, r6, 24
489; CHECK-PWR9-BE-NEXT:    clrlwi r3, r3, 24
490; CHECK-PWR9-BE-NEXT:    clrlwi r7, r7, 24
491; CHECK-PWR9-BE-NEXT:    clrlwi r4, r4, 24
492; CHECK-PWR9-BE-NEXT:    vextublx r8, r5, v2
493; CHECK-PWR9-BE-NEXT:    vextublx r5, r5, v3
494; CHECK-PWR9-BE-NEXT:    sub r3, r6, r3
495; CHECK-PWR9-BE-NEXT:    sub r4, r7, r4
496; CHECK-PWR9-BE-NEXT:    clrlwi r8, r8, 24
497; CHECK-PWR9-BE-NEXT:    clrlwi r5, r5, 24
498; CHECK-PWR9-BE-NEXT:    sub r5, r8, r5
499; CHECK-PWR9-BE-NEXT:    srawi r6, r3, 31
500; CHECK-PWR9-BE-NEXT:    srawi r7, r4, 31
501; CHECK-PWR9-BE-NEXT:    srawi r8, r5, 31
502; CHECK-PWR9-BE-NEXT:    xor r3, r3, r6
503; CHECK-PWR9-BE-NEXT:    xor r4, r4, r7
504; CHECK-PWR9-BE-NEXT:    xor r5, r5, r8
505; CHECK-PWR9-BE-NEXT:    sub r3, r3, r6
506; CHECK-PWR9-BE-NEXT:    li r6, 3
507; CHECK-PWR9-BE-NEXT:    sub r4, r4, r7
508; CHECK-PWR9-BE-NEXT:    sub r5, r5, r8
509; CHECK-PWR9-BE-NEXT:    vextublx r7, r6, v2
510; CHECK-PWR9-BE-NEXT:    vextublx r6, r6, v3
511; CHECK-PWR9-BE-NEXT:    clrlwi r7, r7, 24
512; CHECK-PWR9-BE-NEXT:    clrlwi r6, r6, 24
513; CHECK-PWR9-BE-NEXT:    sub r6, r7, r6
514; CHECK-PWR9-BE-NEXT:    srawi r7, r6, 31
515; CHECK-PWR9-BE-NEXT:    xor r6, r6, r7
516; CHECK-PWR9-BE-NEXT:    sub r6, r6, r7
517; CHECK-PWR9-BE-NEXT:    li r7, 4
518; CHECK-PWR9-BE-NEXT:    vextublx r8, r7, v2
519; CHECK-PWR9-BE-NEXT:    vextublx r7, r7, v3
520; CHECK-PWR9-BE-NEXT:    clrlwi r8, r8, 24
521; CHECK-PWR9-BE-NEXT:    clrlwi r7, r7, 24
522; CHECK-PWR9-BE-NEXT:    sub r7, r8, r7
523; CHECK-PWR9-BE-NEXT:    srawi r8, r7, 31
524; CHECK-PWR9-BE-NEXT:    xor r7, r7, r8
525; CHECK-PWR9-BE-NEXT:    sub r7, r7, r8
526; CHECK-PWR9-BE-NEXT:    li r8, 5
527; CHECK-PWR9-BE-NEXT:    vextublx r9, r8, v2
528; CHECK-PWR9-BE-NEXT:    vextublx r8, r8, v3
529; CHECK-PWR9-BE-NEXT:    clrlwi r9, r9, 24
530; CHECK-PWR9-BE-NEXT:    clrlwi r8, r8, 24
531; CHECK-PWR9-BE-NEXT:    sub r8, r9, r8
532; CHECK-PWR9-BE-NEXT:    srawi r9, r8, 31
533; CHECK-PWR9-BE-NEXT:    xor r8, r8, r9
534; CHECK-PWR9-BE-NEXT:    sub r8, r8, r9
535; CHECK-PWR9-BE-NEXT:    li r9, 6
536; CHECK-PWR9-BE-NEXT:    vextublx r10, r9, v2
537; CHECK-PWR9-BE-NEXT:    vextublx r9, r9, v3
538; CHECK-PWR9-BE-NEXT:    clrlwi r10, r10, 24
539; CHECK-PWR9-BE-NEXT:    clrlwi r9, r9, 24
540; CHECK-PWR9-BE-NEXT:    sub r9, r10, r9
541; CHECK-PWR9-BE-NEXT:    srawi r10, r9, 31
542; CHECK-PWR9-BE-NEXT:    xor r9, r9, r10
543; CHECK-PWR9-BE-NEXT:    sub r9, r9, r10
544; CHECK-PWR9-BE-NEXT:    li r10, 7
545; CHECK-PWR9-BE-NEXT:    vextublx r11, r10, v2
546; CHECK-PWR9-BE-NEXT:    vextublx r10, r10, v3
547; CHECK-PWR9-BE-NEXT:    clrlwi r11, r11, 24
548; CHECK-PWR9-BE-NEXT:    clrlwi r10, r10, 24
549; CHECK-PWR9-BE-NEXT:    sub r10, r11, r10
550; CHECK-PWR9-BE-NEXT:    srawi r11, r10, 31
551; CHECK-PWR9-BE-NEXT:    xor r10, r10, r11
552; CHECK-PWR9-BE-NEXT:    sub r10, r10, r11
553; CHECK-PWR9-BE-NEXT:    li r11, 8
554; CHECK-PWR9-BE-NEXT:    vextublx r12, r11, v2
555; CHECK-PWR9-BE-NEXT:    vextublx r11, r11, v3
556; CHECK-PWR9-BE-NEXT:    clrlwi r12, r12, 24
557; CHECK-PWR9-BE-NEXT:    clrlwi r11, r11, 24
558; CHECK-PWR9-BE-NEXT:    sub r11, r12, r11
559; CHECK-PWR9-BE-NEXT:    srawi r12, r11, 31
560; CHECK-PWR9-BE-NEXT:    xor r11, r11, r12
561; CHECK-PWR9-BE-NEXT:    sub r11, r11, r12
562; CHECK-PWR9-BE-NEXT:    li r12, 9
563; CHECK-PWR9-BE-NEXT:    vextublx r0, r12, v2
564; CHECK-PWR9-BE-NEXT:    vextublx r12, r12, v3
565; CHECK-PWR9-BE-NEXT:    mtvsrwz v0, r11
566; CHECK-PWR9-BE-NEXT:    clrlwi r0, r0, 24
567; CHECK-PWR9-BE-NEXT:    clrlwi r12, r12, 24
568; CHECK-PWR9-BE-NEXT:    sub r12, r0, r12
569; CHECK-PWR9-BE-NEXT:    srawi r0, r12, 31
570; CHECK-PWR9-BE-NEXT:    xor r12, r12, r0
571; CHECK-PWR9-BE-NEXT:    sub r12, r12, r0
572; CHECK-PWR9-BE-NEXT:    li r0, 10
573; CHECK-PWR9-BE-NEXT:    vextublx r30, r0, v2
574; CHECK-PWR9-BE-NEXT:    vextublx r0, r0, v3
575; CHECK-PWR9-BE-NEXT:    clrlwi r30, r30, 24
576; CHECK-PWR9-BE-NEXT:    clrlwi r0, r0, 24
577; CHECK-PWR9-BE-NEXT:    sub r0, r30, r0
578; CHECK-PWR9-BE-NEXT:    srawi r30, r0, 31
579; CHECK-PWR9-BE-NEXT:    xor r0, r0, r30
580; CHECK-PWR9-BE-NEXT:    sub r0, r0, r30
581; CHECK-PWR9-BE-NEXT:    li r30, 11
582; CHECK-PWR9-BE-NEXT:    vextublx r29, r30, v2
583; CHECK-PWR9-BE-NEXT:    vextublx r30, r30, v3
584; CHECK-PWR9-BE-NEXT:    clrlwi r29, r29, 24
585; CHECK-PWR9-BE-NEXT:    clrlwi r30, r30, 24
586; CHECK-PWR9-BE-NEXT:    sub r30, r29, r30
587; CHECK-PWR9-BE-NEXT:    srawi r29, r30, 31
588; CHECK-PWR9-BE-NEXT:    xor r30, r30, r29
589; CHECK-PWR9-BE-NEXT:    sub r30, r30, r29
590; CHECK-PWR9-BE-NEXT:    li r29, 12
591; CHECK-PWR9-BE-NEXT:    vextublx r28, r29, v2
592; CHECK-PWR9-BE-NEXT:    vextublx r29, r29, v3
593; CHECK-PWR9-BE-NEXT:    clrlwi r28, r28, 24
594; CHECK-PWR9-BE-NEXT:    clrlwi r29, r29, 24
595; CHECK-PWR9-BE-NEXT:    sub r29, r28, r29
596; CHECK-PWR9-BE-NEXT:    srawi r28, r29, 31
597; CHECK-PWR9-BE-NEXT:    xor r29, r29, r28
598; CHECK-PWR9-BE-NEXT:    sub r29, r29, r28
599; CHECK-PWR9-BE-NEXT:    li r28, 13
600; CHECK-PWR9-BE-NEXT:    vextublx r27, r28, v2
601; CHECK-PWR9-BE-NEXT:    vextublx r28, r28, v3
602; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r29
603; CHECK-PWR9-BE-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
604; CHECK-PWR9-BE-NEXT:    clrlwi r27, r27, 24
605; CHECK-PWR9-BE-NEXT:    clrlwi r28, r28, 24
606; CHECK-PWR9-BE-NEXT:    sub r28, r27, r28
607; CHECK-PWR9-BE-NEXT:    srawi r27, r28, 31
608; CHECK-PWR9-BE-NEXT:    xor r28, r28, r27
609; CHECK-PWR9-BE-NEXT:    sub r28, r28, r27
610; CHECK-PWR9-BE-NEXT:    li r27, 14
611; CHECK-PWR9-BE-NEXT:    vextublx r26, r27, v2
612; CHECK-PWR9-BE-NEXT:    vextublx r27, r27, v3
613; CHECK-PWR9-BE-NEXT:    clrlwi r26, r26, 24
614; CHECK-PWR9-BE-NEXT:    clrlwi r27, r27, 24
615; CHECK-PWR9-BE-NEXT:    sub r27, r26, r27
616; CHECK-PWR9-BE-NEXT:    srawi r26, r27, 31
617; CHECK-PWR9-BE-NEXT:    xor r27, r27, r26
618; CHECK-PWR9-BE-NEXT:    sub r27, r27, r26
619; CHECK-PWR9-BE-NEXT:    li r26, 15
620; CHECK-PWR9-BE-NEXT:    vextublx r25, r26, v2
621; CHECK-PWR9-BE-NEXT:    vextublx r26, r26, v3
622; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r27
623; CHECK-PWR9-BE-NEXT:    addis r27, r2, .LCPI9_0@toc@ha
624; CHECK-PWR9-BE-NEXT:    addi r27, r27, .LCPI9_0@toc@l
625; CHECK-PWR9-BE-NEXT:    clrlwi r25, r25, 24
626; CHECK-PWR9-BE-NEXT:    clrlwi r26, r26, 24
627; CHECK-PWR9-BE-NEXT:    lxv v4, 0(r27)
628; CHECK-PWR9-BE-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
629; CHECK-PWR9-BE-NEXT:    sub r26, r25, r26
630; CHECK-PWR9-BE-NEXT:    srawi r25, r26, 31
631; CHECK-PWR9-BE-NEXT:    xor r26, r26, r25
632; CHECK-PWR9-BE-NEXT:    sub r26, r26, r25
633; CHECK-PWR9-BE-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
634; CHECK-PWR9-BE-NEXT:    mtvsrwz v2, r26
635; CHECK-PWR9-BE-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
636; CHECK-PWR9-BE-NEXT:    vperm v2, v3, v2, v4
637; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r28
638; CHECK-PWR9-BE-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
639; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
640; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r0
641; CHECK-PWR9-BE-NEXT:    vmrghh v2, v3, v2
642; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r30
643; CHECK-PWR9-BE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
644; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
645; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r12
646; CHECK-PWR9-BE-NEXT:    vperm v5, v0, v5, v4
647; CHECK-PWR9-BE-NEXT:    mtvsrwz v0, r3
648; CHECK-PWR9-BE-NEXT:    vmrghh v3, v5, v3
649; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r7
650; CHECK-PWR9-BE-NEXT:    xxmrghw vs0, v3, v2
651; CHECK-PWR9-BE-NEXT:    mtvsrwz v2, r10
652; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r9
653; CHECK-PWR9-BE-NEXT:    vperm v2, v3, v2, v4
654; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r8
655; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
656; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r5
657; CHECK-PWR9-BE-NEXT:    vmrghh v2, v3, v2
658; CHECK-PWR9-BE-NEXT:    mtvsrwz v3, r6
659; CHECK-PWR9-BE-NEXT:    vperm v3, v5, v3, v4
660; CHECK-PWR9-BE-NEXT:    mtvsrwz v5, r4
661; CHECK-PWR9-BE-NEXT:    vperm v4, v0, v5, v4
662; CHECK-PWR9-BE-NEXT:    vmrghh v3, v4, v3
663; CHECK-PWR9-BE-NEXT:    xxmrghw vs1, v3, v2
664; CHECK-PWR9-BE-NEXT:    xxmrghd v2, vs1, vs0
665; CHECK-PWR9-BE-NEXT:    blr
666;
667; CHECK-PWR8-LABEL: sub_absv_8_ext:
668; CHECK-PWR8:       # %bb.0: # %entry
669; CHECK-PWR8-NEXT:    xxswapd vs0, v2
670; CHECK-PWR8-NEXT:    mfvsrd r5, v2
671; CHECK-PWR8-NEXT:    std r26, -48(r1) # 8-byte Folded Spill
672; CHECK-PWR8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
673; CHECK-PWR8-NEXT:    std r25, -56(r1) # 8-byte Folded Spill
674; CHECK-PWR8-NEXT:    std r27, -40(r1) # 8-byte Folded Spill
675; CHECK-PWR8-NEXT:    mfvsrd r6, v3
676; CHECK-PWR8-NEXT:    xxswapd vs1, v3
677; CHECK-PWR8-NEXT:    clrldi r3, r5, 56
678; CHECK-PWR8-NEXT:    rldicl r7, r5, 56, 56
679; CHECK-PWR8-NEXT:    clrldi r4, r6, 56
680; CHECK-PWR8-NEXT:    rldicl r8, r6, 56, 56
681; CHECK-PWR8-NEXT:    mffprd r26, f0
682; CHECK-PWR8-NEXT:    clrlwi r3, r3, 24
683; CHECK-PWR8-NEXT:    clrlwi r7, r7, 24
684; CHECK-PWR8-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
685; CHECK-PWR8-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
686; CHECK-PWR8-NEXT:    rldicl r11, r5, 40, 56
687; CHECK-PWR8-NEXT:    rldicl r12, r6, 40, 56
688; CHECK-PWR8-NEXT:    clrlwi r4, r4, 24
689; CHECK-PWR8-NEXT:    clrlwi r8, r8, 24
690; CHECK-PWR8-NEXT:    rldicl r9, r5, 48, 56
691; CHECK-PWR8-NEXT:    rldicl r10, r6, 48, 56
692; CHECK-PWR8-NEXT:    sub r4, r3, r4
693; CHECK-PWR8-NEXT:    clrlwi r11, r11, 24
694; CHECK-PWR8-NEXT:    rldicl r3, r26, 16, 56
695; CHECK-PWR8-NEXT:    clrlwi r12, r12, 24
696; CHECK-PWR8-NEXT:    sub r7, r7, r8
697; CHECK-PWR8-NEXT:    clrlwi r9, r9, 24
698; CHECK-PWR8-NEXT:    clrlwi r10, r10, 24
699; CHECK-PWR8-NEXT:    std r24, -64(r1) # 8-byte Folded Spill
700; CHECK-PWR8-NEXT:    mffprd r24, f1
701; CHECK-PWR8-NEXT:    rldicl r0, r5, 32, 56
702; CHECK-PWR8-NEXT:    rldicl r30, r6, 32, 56
703; CHECK-PWR8-NEXT:    std r3, -160(r1) # 8-byte Folded Spill
704; CHECK-PWR8-NEXT:    sub r11, r11, r12
705; CHECK-PWR8-NEXT:    sub r9, r9, r10
706; CHECK-PWR8-NEXT:    srawi r3, r4, 31
707; CHECK-PWR8-NEXT:    srawi r12, r7, 31
708; CHECK-PWR8-NEXT:    clrlwi r10, r0, 24
709; CHECK-PWR8-NEXT:    clrlwi r0, r30, 24
710; CHECK-PWR8-NEXT:    xor r4, r4, r3
711; CHECK-PWR8-NEXT:    xor r7, r7, r12
712; CHECK-PWR8-NEXT:    sub r10, r10, r0
713; CHECK-PWR8-NEXT:    std r20, -96(r1) # 8-byte Folded Spill
714; CHECK-PWR8-NEXT:    std r21, -88(r1) # 8-byte Folded Spill
715; CHECK-PWR8-NEXT:    sub r3, r4, r3
716; CHECK-PWR8-NEXT:    srawi r4, r9, 31
717; CHECK-PWR8-NEXT:    sub r7, r7, r12
718; CHECK-PWR8-NEXT:    std r22, -80(r1) # 8-byte Folded Spill
719; CHECK-PWR8-NEXT:    rldicl r29, r5, 24, 56
720; CHECK-PWR8-NEXT:    rldicl r28, r6, 24, 56
721; CHECK-PWR8-NEXT:    xor r9, r9, r4
722; CHECK-PWR8-NEXT:    mtvsrd v3, r7
723; CHECK-PWR8-NEXT:    rldicl r27, r5, 16, 56
724; CHECK-PWR8-NEXT:    rldicl r25, r6, 16, 56
725; CHECK-PWR8-NEXT:    clrlwi r30, r29, 24
726; CHECK-PWR8-NEXT:    clrlwi r29, r28, 24
727; CHECK-PWR8-NEXT:    mtvsrd v2, r3
728; CHECK-PWR8-NEXT:    sub r4, r9, r4
729; CHECK-PWR8-NEXT:    srawi r7, r10, 31
730; CHECK-PWR8-NEXT:    srawi r3, r11, 31
731; CHECK-PWR8-NEXT:    clrlwi r9, r27, 24
732; CHECK-PWR8-NEXT:    clrlwi r12, r25, 24
733; CHECK-PWR8-NEXT:    sub r0, r30, r29
734; CHECK-PWR8-NEXT:    mtvsrd v4, r4
735; CHECK-PWR8-NEXT:    std r23, -72(r1) # 8-byte Folded Spill
736; CHECK-PWR8-NEXT:    xor r10, r10, r7
737; CHECK-PWR8-NEXT:    xor r11, r11, r3
738; CHECK-PWR8-NEXT:    sub r9, r9, r12
739; CHECK-PWR8-NEXT:    std r18, -112(r1) # 8-byte Folded Spill
740; CHECK-PWR8-NEXT:    std r19, -104(r1) # 8-byte Folded Spill
741; CHECK-PWR8-NEXT:    vmrghb v2, v3, v2
742; CHECK-PWR8-NEXT:    sub r7, r10, r7
743; CHECK-PWR8-NEXT:    rldicl r5, r5, 8, 56
744; CHECK-PWR8-NEXT:    sub r3, r11, r3
745; CHECK-PWR8-NEXT:    rldicl r6, r6, 8, 56
746; CHECK-PWR8-NEXT:    srawi r4, r0, 31
747; CHECK-PWR8-NEXT:    mtvsrd v0, r7
748; CHECK-PWR8-NEXT:    std r16, -128(r1) # 8-byte Folded Spill
749; CHECK-PWR8-NEXT:    std r17, -120(r1) # 8-byte Folded Spill
750; CHECK-PWR8-NEXT:    srawi r7, r9, 31
751; CHECK-PWR8-NEXT:    clrldi r23, r26, 56
752; CHECK-PWR8-NEXT:    mtvsrd v5, r3
753; CHECK-PWR8-NEXT:    clrlwi r3, r5, 24
754; CHECK-PWR8-NEXT:    clrlwi r5, r6, 24
755; CHECK-PWR8-NEXT:    clrldi r22, r24, 56
756; CHECK-PWR8-NEXT:    rldicl r21, r26, 56, 56
757; CHECK-PWR8-NEXT:    xor r10, r0, r4
758; CHECK-PWR8-NEXT:    xor r9, r9, r7
759; CHECK-PWR8-NEXT:    rldicl r20, r24, 56, 56
760; CHECK-PWR8-NEXT:    rldicl r19, r26, 48, 56
761; CHECK-PWR8-NEXT:    sub r3, r3, r5
762; CHECK-PWR8-NEXT:    sub r4, r10, r4
763; CHECK-PWR8-NEXT:    sub r7, r9, r7
764; CHECK-PWR8-NEXT:    clrlwi r9, r23, 24
765; CHECK-PWR8-NEXT:    rldicl r18, r24, 48, 56
766; CHECK-PWR8-NEXT:    clrlwi r10, r22, 24
767; CHECK-PWR8-NEXT:    clrlwi r11, r21, 24
768; CHECK-PWR8-NEXT:    clrlwi r12, r20, 24
769; CHECK-PWR8-NEXT:    mtvsrd v1, r4
770; CHECK-PWR8-NEXT:    std r14, -144(r1) # 8-byte Folded Spill
771; CHECK-PWR8-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
772; CHECK-PWR8-NEXT:    rldicl r17, r26, 40, 56
773; CHECK-PWR8-NEXT:    rldicl r16, r24, 40, 56
774; CHECK-PWR8-NEXT:    sub r9, r9, r10
775; CHECK-PWR8-NEXT:    sub r10, r11, r12
776; CHECK-PWR8-NEXT:    mtvsrd v3, r7
777; CHECK-PWR8-NEXT:    srawi r4, r3, 31
778; CHECK-PWR8-NEXT:    clrlwi r11, r19, 24
779; CHECK-PWR8-NEXT:    clrlwi r12, r18, 24
780; CHECK-PWR8-NEXT:    vmrghb v4, v5, v4
781; CHECK-PWR8-NEXT:    std r31, -8(r1) # 8-byte Folded Spill
782; CHECK-PWR8-NEXT:    xor r3, r3, r4
783; CHECK-PWR8-NEXT:    sub r7, r11, r12
784; CHECK-PWR8-NEXT:    clrlwi r11, r17, 24
785; CHECK-PWR8-NEXT:    clrlwi r12, r16, 24
786; CHECK-PWR8-NEXT:    vmrghb v0, v1, v0
787; CHECK-PWR8-NEXT:    std r2, -152(r1) # 8-byte Folded Spill
788; CHECK-PWR8-NEXT:    rldicl r15, r26, 32, 56
789; CHECK-PWR8-NEXT:    rldicl r14, r24, 32, 56
790; CHECK-PWR8-NEXT:    sub r3, r3, r4
791; CHECK-PWR8-NEXT:    sub r11, r11, r12
792; CHECK-PWR8-NEXT:    srawi r4, r9, 31
793; CHECK-PWR8-NEXT:    srawi r12, r10, 31
794; CHECK-PWR8-NEXT:    clrlwi r0, r15, 24
795; CHECK-PWR8-NEXT:    clrlwi r30, r14, 24
796; CHECK-PWR8-NEXT:    mtvsrd v5, r3
797; CHECK-PWR8-NEXT:    ld r27, -40(r1) # 8-byte Folded Reload
798; CHECK-PWR8-NEXT:    xor r9, r9, r4
799; CHECK-PWR8-NEXT:    xor r10, r10, r12
800; CHECK-PWR8-NEXT:    sub r3, r0, r30
801; CHECK-PWR8-NEXT:    ld r25, -56(r1) # 8-byte Folded Reload
802; CHECK-PWR8-NEXT:    ld r23, -72(r1) # 8-byte Folded Reload
803; CHECK-PWR8-NEXT:    ld r22, -80(r1) # 8-byte Folded Reload
804; CHECK-PWR8-NEXT:    srawi r28, r11, 31
805; CHECK-PWR8-NEXT:    sub r4, r9, r4
806; CHECK-PWR8-NEXT:    sub r10, r10, r12
807; CHECK-PWR8-NEXT:    vmrghb v3, v5, v3
808; CHECK-PWR8-NEXT:    ld r21, -88(r1) # 8-byte Folded Reload
809; CHECK-PWR8-NEXT:    ld r20, -96(r1) # 8-byte Folded Reload
810; CHECK-PWR8-NEXT:    srawi r29, r7, 31
811; CHECK-PWR8-NEXT:    srawi r9, r3, 31
812; CHECK-PWR8-NEXT:    mtvsrd v5, r4
813; CHECK-PWR8-NEXT:    xor r4, r11, r28
814; CHECK-PWR8-NEXT:    ld r19, -104(r1) # 8-byte Folded Reload
815; CHECK-PWR8-NEXT:    ld r18, -112(r1) # 8-byte Folded Reload
816; CHECK-PWR8-NEXT:    mtvsrd v1, r10
817; CHECK-PWR8-NEXT:    ld r10, -160(r1) # 8-byte Folded Reload
818; CHECK-PWR8-NEXT:    rldicl r31, r26, 24, 56
819; CHECK-PWR8-NEXT:    rldicl r2, r24, 24, 56
820; CHECK-PWR8-NEXT:    xor r7, r7, r29
821; CHECK-PWR8-NEXT:    xor r3, r3, r9
822; CHECK-PWR8-NEXT:    rldicl r8, r24, 16, 56
823; CHECK-PWR8-NEXT:    rldicl r6, r26, 8, 56
824; CHECK-PWR8-NEXT:    sub r4, r4, r28
825; CHECK-PWR8-NEXT:    clrlwi r0, r31, 24
826; CHECK-PWR8-NEXT:    clrlwi r30, r2, 24
827; CHECK-PWR8-NEXT:    sub r7, r7, r29
828; CHECK-PWR8-NEXT:    rldicl r5, r24, 8, 56
829; CHECK-PWR8-NEXT:    clrlwi r10, r10, 24
830; CHECK-PWR8-NEXT:    clrlwi r8, r8, 24
831; CHECK-PWR8-NEXT:    sub r3, r3, r9
832; CHECK-PWR8-NEXT:    mtvsrd v7, r4
833; CHECK-PWR8-NEXT:    clrlwi r4, r6, 24
834; CHECK-PWR8-NEXT:    clrlwi r5, r5, 24
835; CHECK-PWR8-NEXT:    sub r0, r0, r30
836; CHECK-PWR8-NEXT:    mtvsrd v6, r7
837; CHECK-PWR8-NEXT:    sub r7, r10, r8
838; CHECK-PWR8-NEXT:    ld r2, -152(r1) # 8-byte Folded Reload
839; CHECK-PWR8-NEXT:    ld r31, -8(r1) # 8-byte Folded Reload
840; CHECK-PWR8-NEXT:    mtvsrd v8, r3
841; CHECK-PWR8-NEXT:    sub r3, r4, r5
842; CHECK-PWR8-NEXT:    srawi r12, r0, 31
843; CHECK-PWR8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
844; CHECK-PWR8-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
845; CHECK-PWR8-NEXT:    ld r28, -32(r1) # 8-byte Folded Reload
846; CHECK-PWR8-NEXT:    srawi r6, r7, 31
847; CHECK-PWR8-NEXT:    srawi r5, r3, 31
848; CHECK-PWR8-NEXT:    xor r8, r0, r12
849; CHECK-PWR8-NEXT:    vmrghb v5, v1, v5
850; CHECK-PWR8-NEXT:    ld r26, -48(r1) # 8-byte Folded Reload
851; CHECK-PWR8-NEXT:    ld r24, -64(r1) # 8-byte Folded Reload
852; CHECK-PWR8-NEXT:    xor r4, r7, r6
853; CHECK-PWR8-NEXT:    xor r3, r3, r5
854; CHECK-PWR8-NEXT:    sub r8, r8, r12
855; CHECK-PWR8-NEXT:    vmrghb v6, v7, v6
856; CHECK-PWR8-NEXT:    ld r17, -120(r1) # 8-byte Folded Reload
857; CHECK-PWR8-NEXT:    ld r16, -128(r1) # 8-byte Folded Reload
858; CHECK-PWR8-NEXT:    sub r4, r4, r6
859; CHECK-PWR8-NEXT:    sub r3, r3, r5
860; CHECK-PWR8-NEXT:    mtvsrd v9, r8
861; CHECK-PWR8-NEXT:    ld r15, -136(r1) # 8-byte Folded Reload
862; CHECK-PWR8-NEXT:    ld r14, -144(r1) # 8-byte Folded Reload
863; CHECK-PWR8-NEXT:    mtvsrd v1, r4
864; CHECK-PWR8-NEXT:    mtvsrd v7, r3
865; CHECK-PWR8-NEXT:    vmrghb v8, v9, v8
866; CHECK-PWR8-NEXT:    vmrghb v1, v7, v1
867; CHECK-PWR8-NEXT:    vmrglh v2, v4, v2
868; CHECK-PWR8-NEXT:    vmrglh v3, v3, v0
869; CHECK-PWR8-NEXT:    vmrglh v4, v6, v5
870; CHECK-PWR8-NEXT:    vmrglh v5, v1, v8
871; CHECK-PWR8-NEXT:    xxmrglw vs0, v3, v2
872; CHECK-PWR8-NEXT:    xxmrglw vs1, v5, v4
873; CHECK-PWR8-NEXT:    xxmrgld v2, vs0, vs1
874; CHECK-PWR8-NEXT:    blr
875;
876; CHECK-PWR7-LABEL: sub_absv_8_ext:
877; CHECK-PWR7:       # %bb.0: # %entry
878; CHECK-PWR7-NEXT:    stdu r1, -416(r1)
879; CHECK-PWR7-NEXT:    .cfi_def_cfa_offset 416
880; CHECK-PWR7-NEXT:    .cfi_offset r23, -72
881; CHECK-PWR7-NEXT:    .cfi_offset r24, -64
882; CHECK-PWR7-NEXT:    .cfi_offset r25, -56
883; CHECK-PWR7-NEXT:    .cfi_offset r26, -48
884; CHECK-PWR7-NEXT:    .cfi_offset r27, -40
885; CHECK-PWR7-NEXT:    .cfi_offset r28, -32
886; CHECK-PWR7-NEXT:    .cfi_offset r29, -24
887; CHECK-PWR7-NEXT:    .cfi_offset r30, -16
888; CHECK-PWR7-NEXT:    addi r3, r1, 304
889; CHECK-PWR7-NEXT:    std r23, 344(r1) # 8-byte Folded Spill
890; CHECK-PWR7-NEXT:    addi r4, r1, 320
891; CHECK-PWR7-NEXT:    std r24, 352(r1) # 8-byte Folded Spill
892; CHECK-PWR7-NEXT:    std r25, 360(r1) # 8-byte Folded Spill
893; CHECK-PWR7-NEXT:    std r26, 368(r1) # 8-byte Folded Spill
894; CHECK-PWR7-NEXT:    std r27, 376(r1) # 8-byte Folded Spill
895; CHECK-PWR7-NEXT:    std r28, 384(r1) # 8-byte Folded Spill
896; CHECK-PWR7-NEXT:    std r29, 392(r1) # 8-byte Folded Spill
897; CHECK-PWR7-NEXT:    std r30, 400(r1) # 8-byte Folded Spill
898; CHECK-PWR7-NEXT:    stxvw4x v2, 0, r3
899; CHECK-PWR7-NEXT:    lbz r3, 304(r1)
900; CHECK-PWR7-NEXT:    stxvw4x v3, 0, r4
901; CHECK-PWR7-NEXT:    lbz r9, 307(r1)
902; CHECK-PWR7-NEXT:    lbz r10, 323(r1)
903; CHECK-PWR7-NEXT:    lbz r11, 308(r1)
904; CHECK-PWR7-NEXT:    lbz r12, 324(r1)
905; CHECK-PWR7-NEXT:    lbz r0, 309(r1)
906; CHECK-PWR7-NEXT:    lbz r30, 325(r1)
907; CHECK-PWR7-NEXT:    sub r9, r9, r10
908; CHECK-PWR7-NEXT:    lbz r29, 310(r1)
909; CHECK-PWR7-NEXT:    lbz r28, 326(r1)
910; CHECK-PWR7-NEXT:    sub r11, r11, r12
911; CHECK-PWR7-NEXT:    lbz r27, 311(r1)
912; CHECK-PWR7-NEXT:    lbz r26, 327(r1)
913; CHECK-PWR7-NEXT:    sub r0, r0, r30
914; CHECK-PWR7-NEXT:    lbz r25, 312(r1)
915; CHECK-PWR7-NEXT:    lbz r24, 328(r1)
916; CHECK-PWR7-NEXT:    sub r29, r29, r28
917; CHECK-PWR7-NEXT:    lbz r10, 315(r1)
918; CHECK-PWR7-NEXT:    lbz r12, 331(r1)
919; CHECK-PWR7-NEXT:    sub r27, r27, r26
920; CHECK-PWR7-NEXT:    lbz r30, 316(r1)
921; CHECK-PWR7-NEXT:    lbz r28, 332(r1)
922; CHECK-PWR7-NEXT:    sub r25, r25, r24
923; CHECK-PWR7-NEXT:    lbz r4, 320(r1)
924; CHECK-PWR7-NEXT:    lbz r5, 305(r1)
925; CHECK-PWR7-NEXT:    sub r10, r10, r12
926; CHECK-PWR7-NEXT:    lbz r6, 321(r1)
927; CHECK-PWR7-NEXT:    lbz r26, 317(r1)
928; CHECK-PWR7-NEXT:    sub r30, r30, r28
929; CHECK-PWR7-NEXT:    lbz r24, 333(r1)
930; CHECK-PWR7-NEXT:    lbz r12, 319(r1)
931; CHECK-PWR7-NEXT:    sub r3, r3, r4
932; CHECK-PWR7-NEXT:    lbz r28, 335(r1)
933; CHECK-PWR7-NEXT:    lbz r7, 306(r1)
934; CHECK-PWR7-NEXT:    sub r5, r5, r6
935; CHECK-PWR7-NEXT:    lbz r8, 322(r1)
936; CHECK-PWR7-NEXT:    sub r26, r26, r24
937; CHECK-PWR7-NEXT:    srawi r24, r5, 31
938; CHECK-PWR7-NEXT:    lbz r23, 313(r1)
939; CHECK-PWR7-NEXT:    sub r12, r12, r28
940; CHECK-PWR7-NEXT:    srawi r28, r3, 31
941; CHECK-PWR7-NEXT:    xor r5, r5, r24
942; CHECK-PWR7-NEXT:    lbz r4, 329(r1)
943; CHECK-PWR7-NEXT:    sub r7, r7, r8
944; CHECK-PWR7-NEXT:    xor r3, r3, r28
945; CHECK-PWR7-NEXT:    lbz r6, 314(r1)
946; CHECK-PWR7-NEXT:    lbz r8, 330(r1)
947; CHECK-PWR7-NEXT:    sub r3, r3, r28
948; CHECK-PWR7-NEXT:    srawi r28, r7, 31
949; CHECK-PWR7-NEXT:    sub r5, r5, r24
950; CHECK-PWR7-NEXT:    srawi r24, r9, 31
951; CHECK-PWR7-NEXT:    xor r7, r7, r28
952; CHECK-PWR7-NEXT:    xor r9, r9, r24
953; CHECK-PWR7-NEXT:    sub r7, r7, r28
954; CHECK-PWR7-NEXT:    srawi r28, r11, 31
955; CHECK-PWR7-NEXT:    sub r9, r9, r24
956; CHECK-PWR7-NEXT:    srawi r24, r0, 31
957; CHECK-PWR7-NEXT:    xor r11, r11, r28
958; CHECK-PWR7-NEXT:    xor r0, r0, r24
959; CHECK-PWR7-NEXT:    sub r11, r11, r28
960; CHECK-PWR7-NEXT:    srawi r28, r29, 31
961; CHECK-PWR7-NEXT:    sub r0, r0, r24
962; CHECK-PWR7-NEXT:    srawi r24, r27, 31
963; CHECK-PWR7-NEXT:    sub r4, r23, r4
964; CHECK-PWR7-NEXT:    xor r29, r29, r28
965; CHECK-PWR7-NEXT:    lbz r23, 318(r1)
966; CHECK-PWR7-NEXT:    xor r27, r27, r24
967; CHECK-PWR7-NEXT:    sub r29, r29, r28
968; CHECK-PWR7-NEXT:    srawi r28, r25, 31
969; CHECK-PWR7-NEXT:    sub r27, r27, r24
970; CHECK-PWR7-NEXT:    srawi r24, r4, 31
971; CHECK-PWR7-NEXT:    sub r6, r6, r8
972; CHECK-PWR7-NEXT:    xor r25, r25, r28
973; CHECK-PWR7-NEXT:    lbz r8, 334(r1)
974; CHECK-PWR7-NEXT:    xor r4, r4, r24
975; CHECK-PWR7-NEXT:    sub r28, r25, r28
976; CHECK-PWR7-NEXT:    srawi r25, r6, 31
977; CHECK-PWR7-NEXT:    sub r4, r4, r24
978; CHECK-PWR7-NEXT:    srawi r24, r10, 31
979; CHECK-PWR7-NEXT:    xor r6, r6, r25
980; CHECK-PWR7-NEXT:    xor r10, r10, r24
981; CHECK-PWR7-NEXT:    sub r6, r6, r25
982; CHECK-PWR7-NEXT:    srawi r25, r30, 31
983; CHECK-PWR7-NEXT:    sub r10, r10, r24
984; CHECK-PWR7-NEXT:    srawi r24, r26, 31
985; CHECK-PWR7-NEXT:    sub r8, r23, r8
986; CHECK-PWR7-NEXT:    xor r30, r30, r25
987; CHECK-PWR7-NEXT:    ld r23, 344(r1) # 8-byte Folded Reload
988; CHECK-PWR7-NEXT:    xor r26, r26, r24
989; CHECK-PWR7-NEXT:    sub r30, r30, r25
990; CHECK-PWR7-NEXT:    srawi r25, r12, 31
991; CHECK-PWR7-NEXT:    sub r26, r26, r24
992; CHECK-PWR7-NEXT:    srawi r24, r8, 31
993; CHECK-PWR7-NEXT:    xor r12, r12, r25
994; CHECK-PWR7-NEXT:    xor r8, r8, r24
995; CHECK-PWR7-NEXT:    sub r12, r12, r25
996; CHECK-PWR7-NEXT:    addi r25, r1, 272
997; CHECK-PWR7-NEXT:    sub r8, r8, r24
998; CHECK-PWR7-NEXT:    stb r12, 288(r1)
999; CHECK-PWR7-NEXT:    addi r12, r1, 288
1000; CHECK-PWR7-NEXT:    stb r8, 272(r1)
1001; CHECK-PWR7-NEXT:    stb r26, 256(r1)
1002; CHECK-PWR7-NEXT:    stb r30, 240(r1)
1003; CHECK-PWR7-NEXT:    stb r10, 224(r1)
1004; CHECK-PWR7-NEXT:    stb r6, 208(r1)
1005; CHECK-PWR7-NEXT:    stb r4, 192(r1)
1006; CHECK-PWR7-NEXT:    stb r28, 176(r1)
1007; CHECK-PWR7-NEXT:    stb r27, 160(r1)
1008; CHECK-PWR7-NEXT:    stb r29, 144(r1)
1009; CHECK-PWR7-NEXT:    stb r0, 128(r1)
1010; CHECK-PWR7-NEXT:    stb r11, 112(r1)
1011; CHECK-PWR7-NEXT:    stb r9, 96(r1)
1012; CHECK-PWR7-NEXT:    stb r7, 80(r1)
1013; CHECK-PWR7-NEXT:    stb r5, 64(r1)
1014; CHECK-PWR7-NEXT:    stb r3, 48(r1)
1015; CHECK-PWR7-NEXT:    addi r8, r1, 256
1016; CHECK-PWR7-NEXT:    addi r26, r1, 240
1017; CHECK-PWR7-NEXT:    lxvw4x v2, 0, r12
1018; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r25
1019; CHECK-PWR7-NEXT:    addi r10, r1, 224
1020; CHECK-PWR7-NEXT:    addi r30, r1, 208
1021; CHECK-PWR7-NEXT:    addi r3, r1, 192
1022; CHECK-PWR7-NEXT:    addi r4, r1, 176
1023; CHECK-PWR7-NEXT:    addi r5, r1, 160
1024; CHECK-PWR7-NEXT:    addi r6, r1, 144
1025; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r8
1026; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r26
1027; CHECK-PWR7-NEXT:    addi r7, r1, 128
1028; CHECK-PWR7-NEXT:    addi r8, r1, 112
1029; CHECK-PWR7-NEXT:    lxvw4x v0, 0, r10
1030; CHECK-PWR7-NEXT:    lxvw4x v1, 0, r30
1031; CHECK-PWR7-NEXT:    vmrghb v2, v3, v2
1032; CHECK-PWR7-NEXT:    addi r9, r1, 96
1033; CHECK-PWR7-NEXT:    lxvw4x v6, 0, r3
1034; CHECK-PWR7-NEXT:    lxvw4x v7, 0, r4
1035; CHECK-PWR7-NEXT:    addi r3, r1, 80
1036; CHECK-PWR7-NEXT:    addi r4, r1, 64
1037; CHECK-PWR7-NEXT:    lxvw4x v3, 0, r5
1038; CHECK-PWR7-NEXT:    lxvw4x v8, 0, r6
1039; CHECK-PWR7-NEXT:    addi r5, r1, 48
1040; CHECK-PWR7-NEXT:    vmrghb v4, v5, v4
1041; CHECK-PWR7-NEXT:    lxvw4x v5, 0, r7
1042; CHECK-PWR7-NEXT:    lxvw4x v9, 0, r8
1043; CHECK-PWR7-NEXT:    vmrghb v0, v1, v0
1044; CHECK-PWR7-NEXT:    lxvw4x v1, 0, r9
1045; CHECK-PWR7-NEXT:    lxvw4x v10, 0, r3
1046; CHECK-PWR7-NEXT:    vmrghb v6, v7, v6
1047; CHECK-PWR7-NEXT:    lxvw4x v7, 0, r4
1048; CHECK-PWR7-NEXT:    vmrghb v3, v8, v3
1049; CHECK-PWR7-NEXT:    lxvw4x v8, 0, r5
1050; CHECK-PWR7-NEXT:    vmrghb v5, v9, v5
1051; CHECK-PWR7-NEXT:    ld r30, 400(r1) # 8-byte Folded Reload
1052; CHECK-PWR7-NEXT:    ld r29, 392(r1) # 8-byte Folded Reload
1053; CHECK-PWR7-NEXT:    vmrghb v1, v10, v1
1054; CHECK-PWR7-NEXT:    ld r28, 384(r1) # 8-byte Folded Reload
1055; CHECK-PWR7-NEXT:    ld r27, 376(r1) # 8-byte Folded Reload
1056; CHECK-PWR7-NEXT:    vmrghb v7, v8, v7
1057; CHECK-PWR7-NEXT:    ld r26, 368(r1) # 8-byte Folded Reload
1058; CHECK-PWR7-NEXT:    ld r25, 360(r1) # 8-byte Folded Reload
1059; CHECK-PWR7-NEXT:    vmrghh v2, v4, v2
1060; CHECK-PWR7-NEXT:    ld r24, 352(r1) # 8-byte Folded Reload
1061; CHECK-PWR7-NEXT:    vmrghh v4, v6, v0
1062; CHECK-PWR7-NEXT:    vmrghh v3, v5, v3
1063; CHECK-PWR7-NEXT:    vmrghh v5, v7, v1
1064; CHECK-PWR7-NEXT:    xxmrghw vs0, v4, v2
1065; CHECK-PWR7-NEXT:    xxmrghw vs1, v5, v3
1066; CHECK-PWR7-NEXT:    xxmrghd v2, vs1, vs0
1067; CHECK-PWR7-NEXT:    addi r1, r1, 416
1068; CHECK-PWR7-NEXT:    blr
1069entry:
1070  %vecext = extractelement <16 x i8> %a, i32 0
1071  %conv = zext i8 %vecext to i32
1072  %vecext1 = extractelement <16 x i8> %b, i32 0
1073  %conv2 = zext i8 %vecext1 to i32
1074  %sub = sub nsw i32 %conv, %conv2
1075  %ispos = icmp sgt i32 %sub, -1
1076  %neg = sub nsw i32 0, %sub
1077  %0 = select i1 %ispos, i32 %sub, i32 %neg
1078  %conv3 = trunc i32 %0 to i8
1079  %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0
1080  %vecext4 = extractelement <16 x i8> %a, i32 1
1081  %conv5 = zext i8 %vecext4 to i32
1082  %vecext6 = extractelement <16 x i8> %b, i32 1
1083  %conv7 = zext i8 %vecext6 to i32
1084  %sub8 = sub nsw i32 %conv5, %conv7
1085  %ispos171 = icmp sgt i32 %sub8, -1
1086  %neg172 = sub nsw i32 0, %sub8
1087  %1 = select i1 %ispos171, i32 %sub8, i32 %neg172
1088  %conv10 = trunc i32 %1 to i8
1089  %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1
1090  %vecext12 = extractelement <16 x i8> %a, i32 2
1091  %conv13 = zext i8 %vecext12 to i32
1092  %vecext14 = extractelement <16 x i8> %b, i32 2
1093  %conv15 = zext i8 %vecext14 to i32
1094  %sub16 = sub nsw i32 %conv13, %conv15
1095  %ispos173 = icmp sgt i32 %sub16, -1
1096  %neg174 = sub nsw i32 0, %sub16
1097  %2 = select i1 %ispos173, i32 %sub16, i32 %neg174
1098  %conv18 = trunc i32 %2 to i8
1099  %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2
1100  %vecext20 = extractelement <16 x i8> %a, i32 3
1101  %conv21 = zext i8 %vecext20 to i32
1102  %vecext22 = extractelement <16 x i8> %b, i32 3
1103  %conv23 = zext i8 %vecext22 to i32
1104  %sub24 = sub nsw i32 %conv21, %conv23
1105  %ispos175 = icmp sgt i32 %sub24, -1
1106  %neg176 = sub nsw i32 0, %sub24
1107  %3 = select i1 %ispos175, i32 %sub24, i32 %neg176
1108  %conv26 = trunc i32 %3 to i8
1109  %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3
1110  %vecext28 = extractelement <16 x i8> %a, i32 4
1111  %conv29 = zext i8 %vecext28 to i32
1112  %vecext30 = extractelement <16 x i8> %b, i32 4
1113  %conv31 = zext i8 %vecext30 to i32
1114  %sub32 = sub nsw i32 %conv29, %conv31
1115  %ispos177 = icmp sgt i32 %sub32, -1
1116  %neg178 = sub nsw i32 0, %sub32
1117  %4 = select i1 %ispos177, i32 %sub32, i32 %neg178
1118  %conv34 = trunc i32 %4 to i8
1119  %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4
1120  %vecext36 = extractelement <16 x i8> %a, i32 5
1121  %conv37 = zext i8 %vecext36 to i32
1122  %vecext38 = extractelement <16 x i8> %b, i32 5
1123  %conv39 = zext i8 %vecext38 to i32
1124  %sub40 = sub nsw i32 %conv37, %conv39
1125  %ispos179 = icmp sgt i32 %sub40, -1
1126  %neg180 = sub nsw i32 0, %sub40
1127  %5 = select i1 %ispos179, i32 %sub40, i32 %neg180
1128  %conv42 = trunc i32 %5 to i8
1129  %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5
1130  %vecext44 = extractelement <16 x i8> %a, i32 6
1131  %conv45 = zext i8 %vecext44 to i32
1132  %vecext46 = extractelement <16 x i8> %b, i32 6
1133  %conv47 = zext i8 %vecext46 to i32
1134  %sub48 = sub nsw i32 %conv45, %conv47
1135  %ispos181 = icmp sgt i32 %sub48, -1
1136  %neg182 = sub nsw i32 0, %sub48
1137  %6 = select i1 %ispos181, i32 %sub48, i32 %neg182
1138  %conv50 = trunc i32 %6 to i8
1139  %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6
1140  %vecext52 = extractelement <16 x i8> %a, i32 7
1141  %conv53 = zext i8 %vecext52 to i32
1142  %vecext54 = extractelement <16 x i8> %b, i32 7
1143  %conv55 = zext i8 %vecext54 to i32
1144  %sub56 = sub nsw i32 %conv53, %conv55
1145  %ispos183 = icmp sgt i32 %sub56, -1
1146  %neg184 = sub nsw i32 0, %sub56
1147  %7 = select i1 %ispos183, i32 %sub56, i32 %neg184
1148  %conv58 = trunc i32 %7 to i8
1149  %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7
1150  %vecext60 = extractelement <16 x i8> %a, i32 8
1151  %conv61 = zext i8 %vecext60 to i32
1152  %vecext62 = extractelement <16 x i8> %b, i32 8
1153  %conv63 = zext i8 %vecext62 to i32
1154  %sub64 = sub nsw i32 %conv61, %conv63
1155  %ispos185 = icmp sgt i32 %sub64, -1
1156  %neg186 = sub nsw i32 0, %sub64
1157  %8 = select i1 %ispos185, i32 %sub64, i32 %neg186
1158  %conv66 = trunc i32 %8 to i8
1159  %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8
1160  %vecext68 = extractelement <16 x i8> %a, i32 9
1161  %conv69 = zext i8 %vecext68 to i32
1162  %vecext70 = extractelement <16 x i8> %b, i32 9
1163  %conv71 = zext i8 %vecext70 to i32
1164  %sub72 = sub nsw i32 %conv69, %conv71
1165  %ispos187 = icmp sgt i32 %sub72, -1
1166  %neg188 = sub nsw i32 0, %sub72
1167  %9 = select i1 %ispos187, i32 %sub72, i32 %neg188
1168  %conv74 = trunc i32 %9 to i8
1169  %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9
1170  %vecext76 = extractelement <16 x i8> %a, i32 10
1171  %conv77 = zext i8 %vecext76 to i32
1172  %vecext78 = extractelement <16 x i8> %b, i32 10
1173  %conv79 = zext i8 %vecext78 to i32
1174  %sub80 = sub nsw i32 %conv77, %conv79
1175  %ispos189 = icmp sgt i32 %sub80, -1
1176  %neg190 = sub nsw i32 0, %sub80
1177  %10 = select i1 %ispos189, i32 %sub80, i32 %neg190
1178  %conv82 = trunc i32 %10 to i8
1179  %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10
1180  %vecext84 = extractelement <16 x i8> %a, i32 11
1181  %conv85 = zext i8 %vecext84 to i32
1182  %vecext86 = extractelement <16 x i8> %b, i32 11
1183  %conv87 = zext i8 %vecext86 to i32
1184  %sub88 = sub nsw i32 %conv85, %conv87
1185  %ispos191 = icmp sgt i32 %sub88, -1
1186  %neg192 = sub nsw i32 0, %sub88
1187  %11 = select i1 %ispos191, i32 %sub88, i32 %neg192
1188  %conv90 = trunc i32 %11 to i8
1189  %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11
1190  %vecext92 = extractelement <16 x i8> %a, i32 12
1191  %conv93 = zext i8 %vecext92 to i32
1192  %vecext94 = extractelement <16 x i8> %b, i32 12
1193  %conv95 = zext i8 %vecext94 to i32
1194  %sub96 = sub nsw i32 %conv93, %conv95
1195  %ispos193 = icmp sgt i32 %sub96, -1
1196  %neg194 = sub nsw i32 0, %sub96
1197  %12 = select i1 %ispos193, i32 %sub96, i32 %neg194
1198  %conv98 = trunc i32 %12 to i8
1199  %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12
1200  %vecext100 = extractelement <16 x i8> %a, i32 13
1201  %conv101 = zext i8 %vecext100 to i32
1202  %vecext102 = extractelement <16 x i8> %b, i32 13
1203  %conv103 = zext i8 %vecext102 to i32
1204  %sub104 = sub nsw i32 %conv101, %conv103
1205  %ispos195 = icmp sgt i32 %sub104, -1
1206  %neg196 = sub nsw i32 0, %sub104
1207  %13 = select i1 %ispos195, i32 %sub104, i32 %neg196
1208  %conv106 = trunc i32 %13 to i8
1209  %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13
1210  %vecext108 = extractelement <16 x i8> %a, i32 14
1211  %conv109 = zext i8 %vecext108 to i32
1212  %vecext110 = extractelement <16 x i8> %b, i32 14
1213  %conv111 = zext i8 %vecext110 to i32
1214  %sub112 = sub nsw i32 %conv109, %conv111
1215  %ispos197 = icmp sgt i32 %sub112, -1
1216  %neg198 = sub nsw i32 0, %sub112
1217  %14 = select i1 %ispos197, i32 %sub112, i32 %neg198
1218  %conv114 = trunc i32 %14 to i8
1219  %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14
1220  %vecext116 = extractelement <16 x i8> %a, i32 15
1221  %conv117 = zext i8 %vecext116 to i32
1222  %vecext118 = extractelement <16 x i8> %b, i32 15
1223  %conv119 = zext i8 %vecext118 to i32
1224  %sub120 = sub nsw i32 %conv117, %conv119
1225  %ispos199 = icmp sgt i32 %sub120, -1
1226  %neg200 = sub nsw i32 0, %sub120
1227  %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
1228  %conv122 = trunc i32 %15 to i8
1229  %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
1230  ret <16 x i8> %vecins123
1231}
1232
1233define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
1234; CHECK-PWR9-LABEL: sub_absv_vec_32:
1235; CHECK-PWR9:       # %bb.0: # %entry
1236; CHECK-PWR9-NEXT:    xvnegsp v3, v3
1237; CHECK-PWR9-NEXT:    xvnegsp v2, v2
1238; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
1239; CHECK-PWR9-NEXT:    blr
1240;
1241; CHECK-PWR78-LABEL: sub_absv_vec_32:
1242; CHECK-PWR78:       # %bb.0: # %entry
1243; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
1244; CHECK-PWR78-NEXT:    vsubuwm v2, v2, v3
1245; CHECK-PWR78-NEXT:    vsubuwm v3, v4, v2
1246; CHECK-PWR78-NEXT:    vmaxsw v2, v2, v3
1247; CHECK-PWR78-NEXT:    blr
1248entry:
1249  %sub = sub <4 x i32> %a, %b
1250  %sub.i = sub <4 x i32> zeroinitializer, %sub
1251  %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
1252  ret <4 x i32> %0
1253}
1254
1255define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
1256; CHECK-PWR9-LABEL: sub_absv_vec_16:
1257; CHECK-PWR9:       # %bb.0: # %entry
1258; CHECK-PWR9-NEXT:    vsubuhm v2, v2, v3
1259; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
1260; CHECK-PWR9-NEXT:    vsubuhm v3, v3, v2
1261; CHECK-PWR9-NEXT:    vmaxsh v2, v2, v3
1262; CHECK-PWR9-NEXT:    blr
1263;
1264; CHECK-PWR78-LABEL: sub_absv_vec_16:
1265; CHECK-PWR78:       # %bb.0: # %entry
1266; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
1267; CHECK-PWR78-NEXT:    vsubuhm v2, v2, v3
1268; CHECK-PWR78-NEXT:    vsubuhm v3, v4, v2
1269; CHECK-PWR78-NEXT:    vmaxsh v2, v2, v3
1270; CHECK-PWR78-NEXT:    blr
1271entry:
1272  %sub = sub <8 x i16> %a, %b
1273  %sub.i = sub <8 x i16> zeroinitializer, %sub
1274  %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
1275  ret <8 x i16> %0
1276}
1277
1278define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
1279; CHECK-PWR9-LABEL: sub_absv_vec_8:
1280; CHECK-PWR9:       # %bb.0: # %entry
1281; CHECK-PWR9-NEXT:    vsububm v2, v2, v3
1282; CHECK-PWR9-NEXT:    xxlxor v3, v3, v3
1283; CHECK-PWR9-NEXT:    vsububm v3, v3, v2
1284; CHECK-PWR9-NEXT:    vmaxsb v2, v2, v3
1285; CHECK-PWR9-NEXT:    blr
1286;
1287; CHECK-PWR78-LABEL: sub_absv_vec_8:
1288; CHECK-PWR78:       # %bb.0: # %entry
1289; CHECK-PWR78-NEXT:    xxlxor v4, v4, v4
1290; CHECK-PWR78-NEXT:    vsububm v2, v2, v3
1291; CHECK-PWR78-NEXT:    vsububm v3, v4, v2
1292; CHECK-PWR78-NEXT:    vmaxsb v2, v2, v3
1293; CHECK-PWR78-NEXT:    blr
1294entry:
1295  %sub = sub <16 x i8> %a, %b
1296  %sub.i = sub <16 x i8> zeroinitializer, %sub
1297  %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
1298  ret <16 x i8> %0
1299}
1300
1301define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1302; CHECK-PWR9-LE-LABEL: zext_sub_absd32:
1303; CHECK-PWR9-LE:       # %bb.0:
1304; CHECK-PWR9-LE-NEXT:    xxlxor v4, v4, v4
1305; CHECK-PWR9-LE-NEXT:    vmrglh v2, v4, v2
1306; CHECK-PWR9-LE-NEXT:    vmrglh v3, v4, v3
1307; CHECK-PWR9-LE-NEXT:    vabsduw v2, v2, v3
1308; CHECK-PWR9-LE-NEXT:    blr
1309;
1310; CHECK-PWR9-BE-LABEL: zext_sub_absd32:
1311; CHECK-PWR9-BE:       # %bb.0:
1312; CHECK-PWR9-BE-NEXT:    xxlxor v4, v4, v4
1313; CHECK-PWR9-BE-NEXT:    vmrghh v2, v4, v2
1314; CHECK-PWR9-BE-NEXT:    vmrghh v3, v4, v3
1315; CHECK-PWR9-BE-NEXT:    vabsduw v2, v2, v3
1316; CHECK-PWR9-BE-NEXT:    blr
1317;
1318; CHECK-PWR8-LABEL: zext_sub_absd32:
1319; CHECK-PWR8:       # %bb.0:
1320; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
1321; CHECK-PWR8-NEXT:    vmrglh v2, v4, v2
1322; CHECK-PWR8-NEXT:    vmrglh v3, v4, v3
1323; CHECK-PWR8-NEXT:    vsubuwm v2, v2, v3
1324; CHECK-PWR8-NEXT:    vsubuwm v3, v4, v2
1325; CHECK-PWR8-NEXT:    vmaxsw v2, v2, v3
1326; CHECK-PWR8-NEXT:    blr
1327;
1328; CHECK-PWR7-LABEL: zext_sub_absd32:
1329; CHECK-PWR7:       # %bb.0:
1330; CHECK-PWR7-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
1331; CHECK-PWR7-NEXT:    xxlxor v5, v5, v5
1332; CHECK-PWR7-NEXT:    addi r3, r3, .LCPI13_0@toc@l
1333; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
1334; CHECK-PWR7-NEXT:    vperm v2, v5, v2, v4
1335; CHECK-PWR7-NEXT:    vperm v3, v5, v3, v4
1336; CHECK-PWR7-NEXT:    vsubuwm v2, v2, v3
1337; CHECK-PWR7-NEXT:    vsubuwm v3, v5, v2
1338; CHECK-PWR7-NEXT:    vmaxsw v2, v2, v3
1339; CHECK-PWR7-NEXT:    blr
1340    %3 = zext <4 x i16> %0 to <4 x i32>
1341    %4 = zext <4 x i16> %1 to <4 x i32>
1342    %5 = sub <4 x i32> %3, %4
1343    %6 = sub <4 x i32> zeroinitializer, %5
1344    %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1345    ret <4 x i32> %7
1346}
1347
1348define <8 x i16> @zext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1349; CHECK-PWR9-LE-LABEL: zext_sub_absd16:
1350; CHECK-PWR9-LE:       # %bb.0:
1351; CHECK-PWR9-LE-NEXT:    xxlxor v4, v4, v4
1352; CHECK-PWR9-LE-NEXT:    vmrglb v2, v4, v2
1353; CHECK-PWR9-LE-NEXT:    vmrglb v3, v4, v3
1354; CHECK-PWR9-LE-NEXT:    vabsduh v2, v2, v3
1355; CHECK-PWR9-LE-NEXT:    blr
1356;
1357; CHECK-PWR9-BE-LABEL: zext_sub_absd16:
1358; CHECK-PWR9-BE:       # %bb.0:
1359; CHECK-PWR9-BE-NEXT:    xxlxor v4, v4, v4
1360; CHECK-PWR9-BE-NEXT:    vmrghb v2, v4, v2
1361; CHECK-PWR9-BE-NEXT:    vmrghb v3, v4, v3
1362; CHECK-PWR9-BE-NEXT:    vabsduh v2, v2, v3
1363; CHECK-PWR9-BE-NEXT:    blr
1364;
1365; CHECK-PWR8-LABEL: zext_sub_absd16:
1366; CHECK-PWR8:       # %bb.0:
1367; CHECK-PWR8-NEXT:    xxlxor v4, v4, v4
1368; CHECK-PWR8-NEXT:    vmrglb v2, v4, v2
1369; CHECK-PWR8-NEXT:    vmrglb v3, v4, v3
1370; CHECK-PWR8-NEXT:    vsubuhm v2, v2, v3
1371; CHECK-PWR8-NEXT:    vsubuhm v3, v4, v2
1372; CHECK-PWR8-NEXT:    vmaxsh v2, v2, v3
1373; CHECK-PWR8-NEXT:    blr
1374;
1375; CHECK-PWR7-LABEL: zext_sub_absd16:
1376; CHECK-PWR7:       # %bb.0:
1377; CHECK-PWR7-NEXT:    addis r3, r2, .LCPI14_0@toc@ha
1378; CHECK-PWR7-NEXT:    xxlxor v5, v5, v5
1379; CHECK-PWR7-NEXT:    addi r3, r3, .LCPI14_0@toc@l
1380; CHECK-PWR7-NEXT:    lxvw4x v4, 0, r3
1381; CHECK-PWR7-NEXT:    vperm v2, v5, v2, v4
1382; CHECK-PWR7-NEXT:    vperm v3, v5, v3, v4
1383; CHECK-PWR7-NEXT:    vsubuhm v2, v2, v3
1384; CHECK-PWR7-NEXT:    vsubuhm v3, v5, v2
1385; CHECK-PWR7-NEXT:    vmaxsh v2, v2, v3
1386; CHECK-PWR7-NEXT:    blr
1387    %3 = zext <8 x i8> %0 to <8 x i16>
1388    %4 = zext <8 x i8> %1 to <8 x i16>
1389    %5 = sub <8 x i16> %3, %4
1390    %6 = sub <8 x i16> zeroinitializer, %5
1391    %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1392    ret <8 x i16> %7
1393}
1394
1395define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1396; CHECK-PWR9-LABEL: zext_sub_absd8:
1397; CHECK-PWR9:       # %bb.0:
1398; CHECK-PWR9-NEXT:    xxspltib vs0, 15
1399; CHECK-PWR9-NEXT:    xxland v2, v2, vs0
1400; CHECK-PWR9-NEXT:    xxland v3, v3, vs0
1401; CHECK-PWR9-NEXT:    vabsdub v2, v2, v3
1402; CHECK-PWR9-NEXT:    blr
1403;
1404; CHECK-PWR78-LABEL: zext_sub_absd8:
1405; CHECK-PWR78:       # %bb.0:
1406; CHECK-PWR78-NEXT:    vspltisb v4, 15
1407; CHECK-PWR78-NEXT:    xxland v2, v2, v4
1408; CHECK-PWR78-NEXT:    xxland v3, v3, v4
1409; CHECK-PWR78-NEXT:    vsububm v2, v2, v3
1410; CHECK-PWR78-NEXT:    xxlxor v3, v3, v3
1411; CHECK-PWR78-NEXT:    vsububm v3, v3, v2
1412; CHECK-PWR78-NEXT:    vmaxsb v2, v2, v3
1413; CHECK-PWR78-NEXT:    blr
1414    %3 = zext <16 x i4> %0 to <16 x i8>
1415    %4 = zext <16 x i4> %1 to <16 x i8>
1416    %5 = sub <16 x i8> %3, %4
1417    %6 = sub <16 x i8> zeroinitializer, %5
1418    %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1419    ret <16 x i8> %7
1420}
1421
1422; To verify vabsdu* exploitation for ucmp + sub + select sequence
1423
1424define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {
1425; CHECK-PWR9-LABEL: absd_int32_ugt:
1426; CHECK-PWR9:       # %bb.0:
1427; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
1428; CHECK-PWR9-NEXT:    blr
1429;
1430; CHECK-PWR78-LABEL: absd_int32_ugt:
1431; CHECK-PWR78:       # %bb.0:
1432; CHECK-PWR78-NEXT:    vcmpgtuw v4, v2, v3
1433; CHECK-PWR78-NEXT:    vsubuwm v5, v2, v3
1434; CHECK-PWR78-NEXT:    vsubuwm v2, v3, v2
1435; CHECK-PWR78-NEXT:    xxsel v2, v2, v5, v4
1436; CHECK-PWR78-NEXT:    blr
1437  %3 = icmp ugt <4 x i32> %0, %1
1438  %4 = sub <4 x i32> %0, %1
1439  %5 = sub <4 x i32> %1, %0
1440  %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1441  ret <4 x i32> %6
1442}
1443
1444define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {
1445; CHECK-PWR9-LABEL: absd_int32_uge:
1446; CHECK-PWR9:       # %bb.0:
1447; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
1448; CHECK-PWR9-NEXT:    blr
1449;
1450; CHECK-PWR78-LABEL: absd_int32_uge:
1451; CHECK-PWR78:       # %bb.0:
1452; CHECK-PWR78-NEXT:    vcmpgtuw v4, v3, v2
1453; CHECK-PWR78-NEXT:    xxlnor vs0, v4, v4
1454; CHECK-PWR78-NEXT:    vsubuwm v4, v2, v3
1455; CHECK-PWR78-NEXT:    vsubuwm v2, v3, v2
1456; CHECK-PWR78-NEXT:    xxsel v2, v2, v4, vs0
1457; CHECK-PWR78-NEXT:    blr
1458  %3 = icmp uge <4 x i32> %0, %1
1459  %4 = sub <4 x i32> %0, %1
1460  %5 = sub <4 x i32> %1, %0
1461  %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1462  ret <4 x i32> %6
1463}
1464
1465define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {
1466; CHECK-PWR9-LABEL: absd_int32_ult:
1467; CHECK-PWR9:       # %bb.0:
1468; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
1469; CHECK-PWR9-NEXT:    blr
1470;
1471; CHECK-PWR78-LABEL: absd_int32_ult:
1472; CHECK-PWR78:       # %bb.0:
1473; CHECK-PWR78-NEXT:    vcmpgtuw v4, v3, v2
1474; CHECK-PWR78-NEXT:    vsubuwm v5, v2, v3
1475; CHECK-PWR78-NEXT:    vsubuwm v2, v3, v2
1476; CHECK-PWR78-NEXT:    xxsel v2, v5, v2, v4
1477; CHECK-PWR78-NEXT:    blr
1478  %3 = icmp ult <4 x i32> %0, %1
1479  %4 = sub <4 x i32> %0, %1
1480  %5 = sub <4 x i32> %1, %0
1481  %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1482  ret <4 x i32> %6
1483}
1484
1485define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {
1486; CHECK-PWR9-LABEL: absd_int32_ule:
1487; CHECK-PWR9:       # %bb.0:
1488; CHECK-PWR9-NEXT:    vabsduw v2, v2, v3
1489; CHECK-PWR9-NEXT:    blr
1490;
1491; CHECK-PWR78-LABEL: absd_int32_ule:
1492; CHECK-PWR78:       # %bb.0:
1493; CHECK-PWR78-NEXT:    vcmpgtuw v4, v2, v3
1494; CHECK-PWR78-NEXT:    xxlnor vs0, v4, v4
1495; CHECK-PWR78-NEXT:    vsubuwm v4, v2, v3
1496; CHECK-PWR78-NEXT:    vsubuwm v2, v3, v2
1497; CHECK-PWR78-NEXT:    xxsel v2, v4, v2, vs0
1498; CHECK-PWR78-NEXT:    blr
1499  %3 = icmp ule <4 x i32> %0, %1
1500  %4 = sub <4 x i32> %0, %1
1501  %5 = sub <4 x i32> %1, %0
1502  %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1503  ret <4 x i32> %6
1504}
1505
1506define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {
1507; CHECK-PWR9-LABEL: absd_int16_ugt:
1508; CHECK-PWR9:       # %bb.0:
1509; CHECK-PWR9-NEXT:    vabsduh v2, v2, v3
1510; CHECK-PWR9-NEXT:    blr
1511;
1512; CHECK-PWR78-LABEL: absd_int16_ugt:
1513; CHECK-PWR78:       # %bb.0:
1514; CHECK-PWR78-NEXT:    vcmpgtuh v4, v2, v3
1515; CHECK-PWR78-NEXT:    vsubuhm v5, v2, v3
1516; CHECK-PWR78-NEXT:    vsubuhm v2, v3, v2
1517; CHECK-PWR78-NEXT:    xxsel v2, v2, v5, v4
1518; CHECK-PWR78-NEXT:    blr
1519  %3 = icmp ugt <8 x i16> %0, %1
1520  %4 = sub <8 x i16> %0, %1
1521  %5 = sub <8 x i16> %1, %0
1522  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1523  ret <8 x i16> %6
1524}
1525
1526define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {
1527; CHECK-PWR9-LABEL: absd_int16_uge:
1528; CHECK-PWR9:       # %bb.0:
1529; CHECK-PWR9-NEXT:    vabsduh v2, v2, v3
1530; CHECK-PWR9-NEXT:    blr
1531;
1532; CHECK-PWR78-LABEL: absd_int16_uge:
1533; CHECK-PWR78:       # %bb.0:
1534; CHECK-PWR78-NEXT:    vcmpgtuh v4, v3, v2
1535; CHECK-PWR78-NEXT:    vsubuhm v5, v2, v3
1536; CHECK-PWR78-NEXT:    vsubuhm v2, v3, v2
1537; CHECK-PWR78-NEXT:    xxlnor v4, v4, v4
1538; CHECK-PWR78-NEXT:    xxsel v2, v2, v5, v4
1539; CHECK-PWR78-NEXT:    blr
1540  %3 = icmp uge <8 x i16> %0, %1
1541  %4 = sub <8 x i16> %0, %1
1542  %5 = sub <8 x i16> %1, %0
1543  %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1544  ret <8 x i16> %6
1545}
1546
1547define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {
1548; CHECK-PWR9-LABEL: absd_int16_ult:
1549; CHECK-PWR9:       # %bb.0:
1550; CHECK-PWR9-NEXT:    vabsduh v2, v2, v3
1551; CHECK-PWR9-NEXT:    blr
1552;
1553; CHECK-PWR78-LABEL: absd_int16_ult:
1554; CHECK-PWR78:       # %bb.0:
1555; CHECK-PWR78-NEXT:    vcmpgtuh v4, v3, v2
1556; CHECK-PWR78-NEXT:    vsubuhm v5, v2, v3
1557; CHECK-PWR78-NEXT:    vsubuhm v2, v3, v2
1558; CHECK-PWR78-NEXT:    xxsel v2, v5, v2, v4
1559; CHECK-PWR78-NEXT:    blr
1560  %3 = icmp ult <8 x i16> %0, %1
1561  %4 = sub <8 x i16> %0, %1
1562  %5 = sub <8 x i16> %1, %0
1563  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1564  ret <8 x i16> %6
1565}
1566
1567define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {
1568; CHECK-PWR9-LABEL: absd_int16_ule:
1569; CHECK-PWR9:       # %bb.0:
1570; CHECK-PWR9-NEXT:    vabsduh v2, v2, v3
1571; CHECK-PWR9-NEXT:    blr
1572;
1573; CHECK-PWR78-LABEL: absd_int16_ule:
1574; CHECK-PWR78:       # %bb.0:
1575; CHECK-PWR78-NEXT:    vcmpgtuh v4, v2, v3
1576; CHECK-PWR78-NEXT:    vsubuhm v5, v2, v3
1577; CHECK-PWR78-NEXT:    vsubuhm v2, v3, v2
1578; CHECK-PWR78-NEXT:    xxlnor v4, v4, v4
1579; CHECK-PWR78-NEXT:    xxsel v2, v5, v2, v4
1580; CHECK-PWR78-NEXT:    blr
1581  %3 = icmp ule <8 x i16> %0, %1
1582  %4 = sub <8 x i16> %0, %1
1583  %5 = sub <8 x i16> %1, %0
1584  %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1585  ret <8 x i16> %6
1586}
1587
1588define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {
1589; CHECK-PWR9-LABEL: absd_int8_ugt:
1590; CHECK-PWR9:       # %bb.0:
1591; CHECK-PWR9-NEXT:    vabsdub v2, v2, v3
1592; CHECK-PWR9-NEXT:    blr
1593;
1594; CHECK-PWR78-LABEL: absd_int8_ugt:
1595; CHECK-PWR78:       # %bb.0:
1596; CHECK-PWR78-NEXT:    vcmpgtub v4, v2, v3
1597; CHECK-PWR78-NEXT:    vsububm v5, v2, v3
1598; CHECK-PWR78-NEXT:    vsububm v2, v3, v2
1599; CHECK-PWR78-NEXT:    xxsel v2, v2, v5, v4
1600; CHECK-PWR78-NEXT:    blr
1601  %3 = icmp ugt <16 x i8> %0, %1
1602  %4 = sub <16 x i8> %0, %1
1603  %5 = sub <16 x i8> %1, %0
1604  %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1605  ret <16 x i8> %6
1606}
1607
1608define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {
1609; CHECK-PWR9-LABEL: absd_int8_uge:
1610; CHECK-PWR9:       # %bb.0:
1611; CHECK-PWR9-NEXT:    vabsdub v2, v2, v3
1612; CHECK-PWR9-NEXT:    blr
1613;
1614; CHECK-PWR78-LABEL: absd_int8_uge:
1615; CHECK-PWR78:       # %bb.0:
1616; CHECK-PWR78-NEXT:    vcmpgtub v4, v3, v2
1617; CHECK-PWR78-NEXT:    vsububm v5, v2, v3
1618; CHECK-PWR78-NEXT:    vsububm v2, v3, v2
1619; CHECK-PWR78-NEXT:    xxlnor v4, v4, v4
1620; CHECK-PWR78-NEXT:    xxsel v2, v2, v5, v4
1621; CHECK-PWR78-NEXT:    blr
1622  %3 = icmp uge <16 x i8> %0, %1
1623  %4 = sub <16 x i8> %0, %1
1624  %5 = sub <16 x i8> %1, %0
1625  %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1626  ret <16 x i8> %6
1627}
1628
1629define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {
1630; CHECK-PWR9-LABEL: absd_int8_ult:
1631; CHECK-PWR9:       # %bb.0:
1632; CHECK-PWR9-NEXT:    vabsdub v2, v2, v3
1633; CHECK-PWR9-NEXT:    blr
1634;
1635; CHECK-PWR78-LABEL: absd_int8_ult:
1636; CHECK-PWR78:       # %bb.0:
1637; CHECK-PWR78-NEXT:    vcmpgtub v4, v3, v2
1638; CHECK-PWR78-NEXT:    vsububm v5, v2, v3
1639; CHECK-PWR78-NEXT:    vsububm v2, v3, v2
1640; CHECK-PWR78-NEXT:    xxsel v2, v5, v2, v4
1641; CHECK-PWR78-NEXT:    blr
1642  %3 = icmp ult <16 x i8> %0, %1
1643  %4 = sub <16 x i8> %0, %1
1644  %5 = sub <16 x i8> %1, %0
1645  %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1646  ret <16 x i8> %6
1647}
1648
1649define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {
1650; CHECK-PWR9-LABEL: absd_int8_ule:
1651; CHECK-PWR9:       # %bb.0:
1652; CHECK-PWR9-NEXT:    vabsdub v2, v2, v3
1653; CHECK-PWR9-NEXT:    blr
1654;
1655; CHECK-PWR78-LABEL: absd_int8_ule:
1656; CHECK-PWR78:       # %bb.0:
1657; CHECK-PWR78-NEXT:    vcmpgtub v4, v2, v3
1658; CHECK-PWR78-NEXT:    vsububm v5, v2, v3
1659; CHECK-PWR78-NEXT:    vsububm v2, v3, v2
1660; CHECK-PWR78-NEXT:    xxlnor v4, v4, v4
1661; CHECK-PWR78-NEXT:    xxsel v2, v5, v2, v4
1662; CHECK-PWR78-NEXT:    blr
1663  %3 = icmp ule <16 x i8> %0, %1
1664  %4 = sub <16 x i8> %0, %1
1665  %5 = sub <16 x i8> %1, %0
1666  %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1667  ret <16 x i8> %6
1668}
1669
1670; some cases we are unable to optimize
1671; check whether goes beyond the scope
1672define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {
1673; CHECK-LABEL: absd_int32_ugt_opp:
1674; CHECK:       # %bb.0:
1675; CHECK-NEXT:    vcmpgtuw v4, v2, v3
1676; CHECK-NEXT:    vsubuwm v5, v2, v3
1677; CHECK-NEXT:    vsubuwm v2, v3, v2
1678; CHECK-NEXT:    xxsel v2, v5, v2, v4
1679; CHECK-NEXT:    blr
1680  %3 = icmp ugt <4 x i32> %0, %1
1681  %4 = sub <4 x i32> %0, %1
1682  %5 = sub <4 x i32> %1, %0
1683  %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1684  ret <4 x i32> %6
1685}
1686
1687define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {
1688; CHECK-PWR9-LABEL: absd_int64_ugt:
1689; CHECK-PWR9:       # %bb.0:
1690; CHECK-PWR9-NEXT:    vcmpgtud v4, v2, v3
1691; CHECK-PWR9-NEXT:    vsubudm v5, v2, v3
1692; CHECK-PWR9-NEXT:    vsubudm v2, v3, v2
1693; CHECK-PWR9-NEXT:    xxsel v2, v2, v5, v4
1694; CHECK-PWR9-NEXT:    blr
1695;
1696; CHECK-PWR8-LABEL: absd_int64_ugt:
1697; CHECK-PWR8:       # %bb.0:
1698; CHECK-PWR8-NEXT:    vcmpgtud v4, v2, v3
1699; CHECK-PWR8-NEXT:    vsubudm v5, v2, v3
1700; CHECK-PWR8-NEXT:    vsubudm v2, v3, v2
1701; CHECK-PWR8-NEXT:    xxsel v2, v2, v5, v4
1702; CHECK-PWR8-NEXT:    blr
1703;
1704; CHECK-PWR7-LABEL: absd_int64_ugt:
1705; CHECK-PWR7:       # %bb.0:
1706; CHECK-PWR7-NEXT:    addi r3, r1, -64
1707; CHECK-PWR7-NEXT:    addi r4, r1, -80
1708; CHECK-PWR7-NEXT:    li r5, 0
1709; CHECK-PWR7-NEXT:    li r6, -1
1710; CHECK-PWR7-NEXT:    stxvd2x v3, 0, r3
1711; CHECK-PWR7-NEXT:    stxvd2x v2, 0, r4
1712; CHECK-PWR7-NEXT:    ld r3, -56(r1)
1713; CHECK-PWR7-NEXT:    ld r4, -72(r1)
1714; CHECK-PWR7-NEXT:    ld r8, -80(r1)
1715; CHECK-PWR7-NEXT:    cmpld r4, r3
1716; CHECK-PWR7-NEXT:    sub r9, r4, r3
1717; CHECK-PWR7-NEXT:    iselgt r7, r6, r5
1718; CHECK-PWR7-NEXT:    sub r3, r3, r4
1719; CHECK-PWR7-NEXT:    std r7, -8(r1)
1720; CHECK-PWR7-NEXT:    ld r7, -64(r1)
1721; CHECK-PWR7-NEXT:    cmpld r8, r7
1722; CHECK-PWR7-NEXT:    iselgt r4, r6, r5
1723; CHECK-PWR7-NEXT:    addi r5, r1, -16
1724; CHECK-PWR7-NEXT:    std r4, -16(r1)
1725; CHECK-PWR7-NEXT:    sub r4, r8, r7
1726; CHECK-PWR7-NEXT:    lxvd2x v2, 0, r5
1727; CHECK-PWR7-NEXT:    std r9, -40(r1)
1728; CHECK-PWR7-NEXT:    addi r5, r1, -48
1729; CHECK-PWR7-NEXT:    std r4, -48(r1)
1730; CHECK-PWR7-NEXT:    sub r4, r7, r8
1731; CHECK-PWR7-NEXT:    lxvd2x v3, 0, r5
1732; CHECK-PWR7-NEXT:    std r3, -24(r1)
1733; CHECK-PWR7-NEXT:    addi r3, r1, -32
1734; CHECK-PWR7-NEXT:    std r4, -32(r1)
1735; CHECK-PWR7-NEXT:    lxvd2x v4, 0, r3
1736; CHECK-PWR7-NEXT:    xxsel v2, v4, v3, v2
1737; CHECK-PWR7-NEXT:    blr
1738  %3 = icmp ugt <2 x i64> %0, %1
1739  %4 = sub <2 x i64> %0, %1
1740  %5 = sub <2 x i64> %1, %0
1741  %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %5
1742  ret <2 x i64> %6
1743}
1744
1745declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
1746
1747declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
1748
1749declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)
1750
1751