1; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 2; RUN: -verify-machineinstrs < %s | FileCheck %s 3; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \ 4; RUN: -verify-machineinstrs < %s | FileCheck %s 5; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 7; RUN: llc -O0 -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \ 8; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE 9 10; The following testcases take one halfword element from the second vector and 11; inserts it at various locations in the first vector 12define <8 x i16> @shuffle_vector_halfword_0_8(<8 x i16> %a, <8 x i16> %b) { 13entry: 14; CHECK-LABEL: shuffle_vector_halfword_0_8 15; CHECK: vsldoi 3, 3, 3, 8 16; CHECK: vinserth 2, 3, 14 17; CHECK-BE-LABEL: shuffle_vector_halfword_0_8 18; CHECK-BE: vsldoi 3, 3, 3, 10 19; CHECK-BE: vinserth 2, 3, 0 20 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 21 ret <8 x i16> %vecins 22} 23 24define <8 x i16> @shuffle_vector_halfword_1_15(<8 x i16> %a, <8 x i16> %b) { 25entry: 26; CHECK-LABEL: shuffle_vector_halfword_1_15 27; CHECK: vsldoi 3, 3, 3, 10 28; CHECK: vinserth 2, 3, 12 29; CHECK-BE-LABEL: shuffle_vector_halfword_1_15 30; CHECK-BE: vsldoi 3, 3, 3, 8 31; CHECK-BE: vinserth 2, 3, 2 32 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 15, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 33 ret <8 x i16> %vecins 34} 35 36define <8 x i16> @shuffle_vector_halfword_2_9(<8 x i16> %a, <8 x i16> %b) { 37entry: 38; CHECK-LABEL: shuffle_vector_halfword_2_9 39; CHECK: vsldoi 3, 3, 3, 6 40; CHECK: vinserth 2, 3, 10 41; CHECK-BE-LABEL: shuffle_vector_halfword_2_9 42; CHECK-BE: vsldoi 3, 3, 3, 12 43; CHECK-BE: vinserth 2, 3, 4 44 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 9, i32 3, i32 4, i32 5, i32 6, i32 7> 45 ret <8 x i16> %vecins 46} 47 48define <8 x i16> @shuffle_vector_halfword_3_13(<8 x i16> %a, <8 x i16> %b) { 49entry: 50; CHECK-LABEL: shuffle_vector_halfword_3_13 51; CHECK: vsldoi 3, 3, 3, 14 52; CHECK: vinserth 2, 3, 8 53; CHECK-BE-LABEL: shuffle_vector_halfword_3_13 54; CHECK-BE: vsldoi 3, 3, 3, 4 55; CHECK-BE: vinserth 2, 3, 6 56 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 13, i32 4, i32 5, i32 6, i32 7> 57 ret <8 x i16> %vecins 58} 59 60define <8 x i16> @shuffle_vector_halfword_4_10(<8 x i16> %a, <8 x i16> %b) { 61entry: 62; CHECK-LABEL: shuffle_vector_halfword_4_10 63; CHECK: vsldoi 3, 3, 3, 4 64; CHECK: vinserth 2, 3, 6 65; CHECK-BE-LABEL: shuffle_vector_halfword_4_10 66; CHECK-BE: vsldoi 3, 3, 3, 14 67; CHECK-BE: vinserth 2, 3, 8 68 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 10, i32 5, i32 6, i32 7> 69 ret <8 x i16> %vecins 70} 71 72define <8 x i16> @shuffle_vector_halfword_5_14(<8 x i16> %a, <8 x i16> %b) { 73entry: 74; CHECK-LABEL: shuffle_vector_halfword_5_14 75; CHECK: vsldoi 3, 3, 3, 12 76; CHECK: vinserth 2, 3, 4 77; CHECK-BE-LABEL: shuffle_vector_halfword_5_14 78; CHECK-BE: vsldoi 3, 3, 3, 6 79; CHECK-BE: vinserth 2, 3, 10 80 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 14, i32 6, i32 7> 81 ret <8 x i16> %vecins 82} 83 84define <8 x i16> @shuffle_vector_halfword_6_11(<8 x i16> %a, <8 x i16> %b) { 85entry: 86; CHECK-LABEL: shuffle_vector_halfword_6_11 87; CHECK: vsldoi 3, 3, 3, 2 88; CHECK: vinserth 2, 3, 2 89; CHECK-BE-LABEL: shuffle_vector_halfword_6_11 90; CHECK-BE: vinserth 2, 3, 12 91 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 11, i32 7> 92 ret <8 x i16> %vecins 93} 94 95define <8 x i16> @shuffle_vector_halfword_7_12(<8 x i16> %a, <8 x i16> %b) { 96entry: 97; CHECK-LABEL: shuffle_vector_halfword_7_12 98; CHECK: vinserth 2, 3, 0 99; CHECK-BE-LABEL: shuffle_vector_halfword_7_12 100; CHECK-BE: vsldoi 3, 3, 3, 2 101; CHECK-BE: vinserth 2, 3, 14 102 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 12> 103 ret <8 x i16> %vecins 104} 105 106define <8 x i16> @shuffle_vector_halfword_8_1(<8 x i16> %a, <8 x i16> %b) { 107entry: 108; CHECK-LABEL: shuffle_vector_halfword_8_1 109; CHECK: vsldoi 2, 2, 2, 6 110; CHECK: vinserth 3, 2, 14 111; CHECK: vmr 2, 3 112; CHECK-BE-LABEL: shuffle_vector_halfword_8_1 113; CHECK-BE: vsldoi 2, 2, 2, 12 114; CHECK-BE: vinserth 3, 2, 0 115; CHECK-BE: vmr 2, 3 116 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 117 ret <8 x i16> %vecins 118} 119 120; The following testcases take one halfword element from the first vector and 121; inserts it at various locations in the second vector 122define <8 x i16> @shuffle_vector_halfword_9_7(<8 x i16> %a, <8 x i16> %b) { 123entry: 124; CHECK-LABEL: shuffle_vector_halfword_9_7 125; CHECK: vsldoi 2, 2, 2, 10 126; CHECK: vinserth 3, 2, 12 127; CHECK: vmr 2, 3 128; CHECK-BE-LABEL: shuffle_vector_halfword_9_7 129; CHECK-BE: vsldoi 2, 2, 2, 8 130; CHECK-BE: vinserth 3, 2, 2 131; CHECK-BE: vmr 2, 3 132 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 133 ret <8 x i16> %vecins 134} 135 136define <8 x i16> @shuffle_vector_halfword_10_4(<8 x i16> %a, <8 x i16> %b) { 137entry: 138; CHECK-LABEL: shuffle_vector_halfword_10_4 139; CHECK: vinserth 3, 2, 10 140; CHECK: vmr 2, 3 141; CHECK-BE-LABEL: shuffle_vector_halfword_10_4 142; CHECK-BE: vsldoi 2, 2, 2, 2 143; CHECK-BE: vinserth 3, 2, 4 144; CHECK-BE: vmr 2, 3 145 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 4, i32 11, i32 12, i32 13, i32 14, i32 15> 146 ret <8 x i16> %vecins 147} 148 149define <8 x i16> @shuffle_vector_halfword_11_2(<8 x i16> %a, <8 x i16> %b) { 150entry: 151; CHECK-LABEL: shuffle_vector_halfword_11_2 152; CHECK: vsldoi 2, 2, 2, 4 153; CHECK: vinserth 3, 2, 8 154; CHECK: vmr 2, 3 155; CHECK-BE-LABEL: shuffle_vector_halfword_11_2 156; CHECK-BE: vsldoi 2, 2, 2, 14 157; CHECK-BE: vinserth 3, 2, 6 158; CHECK-BE: vmr 2, 3 159 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 2, i32 12, i32 13, i32 14, i32 15> 160 ret <8 x i16> %vecins 161} 162 163define <8 x i16> @shuffle_vector_halfword_12_6(<8 x i16> %a, <8 x i16> %b) { 164entry: 165; CHECK-LABEL: shuffle_vector_halfword_12_6 166; CHECK: vsldoi 2, 2, 2, 12 167; CHECK: vinserth 3, 2, 6 168; CHECK: vmr 2, 3 169; CHECK-BE-LABEL: shuffle_vector_halfword_12_6 170; CHECK-BE: vsldoi 2, 2, 2, 6 171; CHECK-BE: vinserth 3, 2, 8 172; CHECK-BE: vmr 2, 3 173 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 6, i32 13, i32 14, i32 15> 174 ret <8 x i16> %vecins 175} 176 177define <8 x i16> @shuffle_vector_halfword_13_3(<8 x i16> %a, <8 x i16> %b) { 178entry: 179; CHECK-LABEL: shuffle_vector_halfword_13_3 180; CHECK: vsldoi 2, 2, 2, 2 181; CHECK: vinserth 3, 2, 4 182; CHECK: vmr 2, 3 183; CHECK-BE-LABEL: shuffle_vector_halfword_13_3 184; CHECK-BE: vinserth 3, 2, 10 185; CHECK-BE: vmr 2, 3 186 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 3, i32 14, i32 15> 187 ret <8 x i16> %vecins 188} 189 190define <8 x i16> @shuffle_vector_halfword_14_5(<8 x i16> %a, <8 x i16> %b) { 191entry: 192; CHECK-LABEL: shuffle_vector_halfword_14_5 193; CHECK: vsldoi 2, 2, 2, 14 194; CHECK: vinserth 3, 2, 2 195; CHECK: vmr 2, 3 196; CHECK-BE-LABEL: shuffle_vector_halfword_14_5 197; CHECK-BE: vsldoi 2, 2, 2, 4 198; CHECK-BE: vinserth 3, 2, 12 199; CHECK-BE: vmr 2, 3 200 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 5, i32 15> 201 ret <8 x i16> %vecins 202} 203 204define <8 x i16> @shuffle_vector_halfword_15_0(<8 x i16> %a, <8 x i16> %b) { 205entry: 206; CHECK-LABEL: shuffle_vector_halfword_15_0 207; CHECK: vsldoi 2, 2, 2, 8 208; CHECK: vinserth 3, 2, 0 209; CHECK: vmr 2, 3 210; CHECK-BE-LABEL: shuffle_vector_halfword_15_0 211; CHECK-BE: vsldoi 2, 2, 2, 10 212; CHECK-BE: vinserth 3, 2, 14 213; CHECK-BE: vmr 2, 3 214 %vecins = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0> 215 ret <8 x i16> %vecins 216} 217 218; The following testcases use the same vector in both arguments of the 219; shufflevector. If halfword element 3 in BE mode(or 4 in LE mode) is the one 220; we're attempting to insert, then we can use the vector insert instruction 221define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) { 222entry: 223; CHECK-LABEL: shuffle_vector_halfword_0_4 224; CHECK: vinserth 2, 2, 14 225; CHECK-BE-LABEL: shuffle_vector_halfword_0_4 226; CHECK-BE-NOT: vinserth 227 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 228 ret <8 x i16> %vecins 229} 230 231define <8 x i16> @shuffle_vector_halfword_1_3(<8 x i16> %a) { 232entry: 233; CHECK-LABEL: shuffle_vector_halfword_1_3 234; CHECK-NOT: vinserth 235; CHECK-BE-LABEL: shuffle_vector_halfword_1_3 236; CHECK-BE: vinserth 2, 2, 2 237 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 3, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 238 ret <8 x i16> %vecins 239} 240 241define <8 x i16> @shuffle_vector_halfword_2_3(<8 x i16> %a) { 242entry: 243; CHECK-LABEL: shuffle_vector_halfword_2_3 244; CHECK-NOT: vinserth 245; CHECK-BE-LABEL: shuffle_vector_halfword_2_3 246; CHECK-BE: vinserth 2, 2, 4 247 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 3, i32 3, i32 4, i32 5, i32 6, i32 7> 248 ret <8 x i16> %vecins 249} 250 251define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { 252entry: 253; CHECK-LABEL: shuffle_vector_halfword_3_4 254; CHECK: vinserth 2, 2, 8 255; CHECK-BE-LABEL: shuffle_vector_halfword_3_4 256; CHECK-BE-NOT: vinserth 257 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 4, i32 4, i32 5, i32 6, i32 7> 258 ret <8 x i16> %vecins 259} 260 261define <8 x i16> @shuffle_vector_halfword_4_3(<8 x i16> %a) { 262entry: 263; CHECK-LABEL: shuffle_vector_halfword_4_3 264; CHECK-NOT: vinserth 265; CHECK-BE-LABEL: shuffle_vector_halfword_4_3 266; CHECK-BE: vinserth 2, 2, 8 267 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 5, i32 6, i32 7> 268 ret <8 x i16> %vecins 269} 270 271define <8 x i16> @shuffle_vector_halfword_5_3(<8 x i16> %a) { 272entry: 273; CHECK-LABEL: shuffle_vector_halfword_5_3 274; CHECK-NOT: vinserth 275; CHECK-BE-LABEL: shuffle_vector_halfword_5_3 276; CHECK-BE: vinserth 2, 2, 10 277 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 3, i32 6, i32 7> 278 ret <8 x i16> %vecins 279} 280 281define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { 282entry: 283; CHECK-LABEL: shuffle_vector_halfword_6_4 284; CHECK: vinserth 2, 2, 2 285; CHECK-BE-LABEL: shuffle_vector_halfword_6_4 286; CHECK-BE-NOT: vinserth 287 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 4, i32 7> 288 ret <8 x i16> %vecins 289} 290 291define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { 292entry: 293; CHECK-LABEL: shuffle_vector_halfword_7_4 294; CHECK: vinserth 2, 2, 0 295; CHECK-BE-LABEL: shuffle_vector_halfword_7_4 296; CHECK-BE-NOT: vinserth 297 %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 4> 298 ret <8 x i16> %vecins 299} 300 301; The following testcases take one byte element from the second vector and 302; inserts it at various locations in the first vector 303define <16 x i8> @shuffle_vector_byte_0_16(<16 x i8> %a, <16 x i8> %b) { 304entry: 305; CHECK-LABEL: shuffle_vector_byte_0_16 306; CHECK: vsldoi 3, 3, 3, 8 307; CHECK: vinsertb 2, 3, 15 308; CHECK-BE-LABEL: shuffle_vector_byte_0_16 309; CHECK-BE: vsldoi 3, 3, 3, 9 310; CHECK-BE: vinsertb 2, 3, 0 311 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 312 ret <16 x i8> %vecins 313} 314 315define <16 x i8> @shuffle_vector_byte_1_25(<16 x i8> %a, <16 x i8> %b) { 316entry: 317; CHECK-LABEL: shuffle_vector_byte_1_25 318; CHECK: vsldoi 3, 3, 3, 15 319; CHECK: vinsertb 2, 3, 14 320; CHECK-BE-LABEL: shuffle_vector_byte_1_25 321; CHECK-BE: vsldoi 3, 3, 3, 2 322; CHECK-BE: vinsertb 2, 3, 1 323 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 25, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 324 ret <16 x i8> %vecins 325} 326 327define <16 x i8> @shuffle_vector_byte_2_18(<16 x i8> %a, <16 x i8> %b) { 328entry: 329; CHECK-LABEL: shuffle_vector_byte_2_18 330; CHECK: vsldoi 3, 3, 3, 6 331; CHECK: vinsertb 2, 3, 13 332; CHECK-BE-LABEL: shuffle_vector_byte_2_18 333; CHECK-BE: vsldoi 3, 3, 3, 11 334; CHECK-BE: vinsertb 2, 3, 2 335 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 18, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 336 ret <16 x i8> %vecins 337} 338 339define <16 x i8> @shuffle_vector_byte_3_27(<16 x i8> %a, <16 x i8> %b) { 340entry: 341; CHECK-LABEL: shuffle_vector_byte_3_27 342; CHECK: vsldoi 3, 3, 3, 13 343; CHECK: vinsertb 2, 3, 12 344; CHECK-BE-LABEL: shuffle_vector_byte_3_27 345; CHECK-BE: vsldoi 3, 3, 3, 4 346; CHECK-BE: vinsertb 2, 3, 3 347 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 27, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 348 ret <16 x i8> %vecins 349} 350 351define <16 x i8> @shuffle_vector_byte_4_20(<16 x i8> %a, <16 x i8> %b) { 352entry: 353; CHECK-LABEL: shuffle_vector_byte_4_20 354; CHECK: vsldoi 3, 3, 3, 4 355; CHECK: vinsertb 2, 3, 11 356; CHECK-BE-LABEL: shuffle_vector_byte_4_20 357; CHECK-BE: vsldoi 3, 3, 3, 13 358; CHECK-BE: vinsertb 2, 3, 4 359 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 20, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 360 ret <16 x i8> %vecins 361} 362 363define <16 x i8> @shuffle_vector_byte_5_29(<16 x i8> %a, <16 x i8> %b) { 364entry: 365; CHECK-LABEL: shuffle_vector_byte_5_29 366; CHECK: vsldoi 3, 3, 3, 11 367; CHECK: vinsertb 2, 3, 10 368; CHECK-BE-LABEL: shuffle_vector_byte_5_29 369; CHECK-BE: vsldoi 3, 3, 3, 6 370; CHECK-BE: vinsertb 2, 3, 5 371 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 29, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 372 ret <16 x i8> %vecins 373} 374 375define <16 x i8> @shuffle_vector_byte_6_22(<16 x i8> %a, <16 x i8> %b) { 376entry: 377; CHECK-LABEL: shuffle_vector_byte_6_22 378; CHECK: vsldoi 3, 3, 3, 2 379; CHECK: vinsertb 2, 3, 9 380; CHECK-BE-LABEL: shuffle_vector_byte_6_22 381; CHECK-BE: vsldoi 3, 3, 3, 15 382; CHECK-BE: vinsertb 2, 3, 6 383 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 384 ret <16 x i8> %vecins 385} 386 387define <16 x i8> @shuffle_vector_byte_7_31(<16 x i8> %a, <16 x i8> %b) { 388entry: 389; CHECK-LABEL: shuffle_vector_byte_7_31 390; CHECK: vsldoi 3, 3, 3, 9 391; CHECK: vinsertb 2, 3, 8 392; CHECK-BE-LABEL: shuffle_vector_byte_7_31 393; CHECK-BE: vsldoi 3, 3, 3, 8 394; CHECK-BE: vinsertb 2, 3, 7 395 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 31, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 396 ret <16 x i8> %vecins 397} 398 399define <16 x i8> @shuffle_vector_byte_8_24(<16 x i8> %a, <16 x i8> %b) { 400entry: 401; CHECK-LABEL: shuffle_vector_byte_8_24 402; CHECK: vinsertb 2, 3, 7 403; CHECK-BE-LABEL: shuffle_vector_byte_8_24 404; CHECK-BE: vsldoi 3, 3, 3, 1 405; CHECK-BE: vinsertb 2, 3, 8 406 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 407 ret <16 x i8> %vecins 408} 409 410define <16 x i8> @shuffle_vector_byte_9_17(<16 x i8> %a, <16 x i8> %b) { 411entry: 412; CHECK-LABEL: shuffle_vector_byte_9_17 413; CHECK: vsldoi 3, 3, 3, 7 414; CHECK: vinsertb 2, 3, 6 415; CHECK-BE-LABEL: shuffle_vector_byte_9_17 416; CHECK-BE: vsldoi 3, 3, 3, 10 417; CHECK-BE: vinsertb 2, 3, 9 418 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 419 ret <16 x i8> %vecins 420} 421 422define <16 x i8> @shuffle_vector_byte_10_26(<16 x i8> %a, <16 x i8> %b) { 423entry: 424; CHECK-LABEL: shuffle_vector_byte_10_26 425; CHECK: vsldoi 3, 3, 3, 14 426; CHECK: vinsertb 2, 3, 5 427; CHECK-BE-LABEL: shuffle_vector_byte_10_26 428; CHECK-BE: vsldoi 3, 3, 3, 3 429; CHECK-BE: vinsertb 2, 3, 10 430 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 26, i32 11, i32 12, i32 13, i32 14, i32 15> 431 ret <16 x i8> %vecins 432} 433 434define <16 x i8> @shuffle_vector_byte_11_19(<16 x i8> %a, <16 x i8> %b) { 435entry: 436; CHECK-LABEL: shuffle_vector_byte_11_19 437; CHECK: vsldoi 3, 3, 3, 5 438; CHECK: vinsertb 2, 3, 4 439; CHECK-BE-LABEL: shuffle_vector_byte_11_19 440; CHECK-BE: vsldoi 3, 3, 3, 12 441; CHECK-BE: vinsertb 2, 3, 11 442 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 19, i32 12, i32 13, i32 14, i32 15> 443 ret <16 x i8> %vecins 444} 445 446define <16 x i8> @shuffle_vector_byte_12_28(<16 x i8> %a, <16 x i8> %b) { 447entry: 448; CHECK-LABEL: shuffle_vector_byte_12_28 449; CHECK: vsldoi 3, 3, 3, 12 450; CHECK: vinsertb 2, 3, 3 451; CHECK-BE-LABEL: shuffle_vector_byte_12_28 452; CHECK-BE: vsldoi 3, 3, 3, 5 453; CHECK-BE: vinsertb 2, 3, 12 454 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 28, i32 13, i32 14, i32 15> 455 ret <16 x i8> %vecins 456} 457 458define <16 x i8> @shuffle_vector_byte_13_21(<16 x i8> %a, <16 x i8> %b) { 459entry: 460; CHECK-LABEL: shuffle_vector_byte_13_21 461; CHECK: vsldoi 3, 3, 3, 3 462; CHECK: vinsertb 2, 3, 2 463; CHECK-BE-LABEL: shuffle_vector_byte_13_21 464; CHECK-BE: vsldoi 3, 3, 3, 14 465; CHECK-BE: vinsertb 2, 3, 13 466 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 21, i32 14, i32 15> 467 ret <16 x i8> %vecins 468} 469 470define <16 x i8> @shuffle_vector_byte_14_30(<16 x i8> %a, <16 x i8> %b) { 471entry: 472; CHECK-LABEL: shuffle_vector_byte_14_30 473; CHECK: vsldoi 3, 3, 3, 10 474; CHECK: vinsertb 2, 3, 1 475; CHECK-BE-LABEL: shuffle_vector_byte_14_30 476; CHECK-BE: vsldoi 3, 3, 3, 7 477; CHECK-BE: vinsertb 2, 3, 14 478 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 30, i32 15> 479 ret <16 x i8> %vecins 480} 481 482define <16 x i8> @shuffle_vector_byte_15_23(<16 x i8> %a, <16 x i8> %b) { 483entry: 484; CHECK-LABEL: shuffle_vector_byte_15_23 485; CHECK: vsldoi 3, 3, 3, 1 486; CHECK: vinsertb 2, 3, 0 487; CHECK-BE-LABEL: shuffle_vector_byte_15_23 488; CHECK-BE: vinsertb 2, 3, 15 489 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 23> 490 ret <16 x i8> %vecins 491} 492 493; The following testcases take one byte element from the first vector and 494; inserts it at various locations in the second vector 495define <16 x i8> @shuffle_vector_byte_16_8(<16 x i8> %a, <16 x i8> %b) { 496entry: 497; CHECK-LABEL: shuffle_vector_byte_16_8 498; CHECK: vinsertb 3, 2, 15 499; CHECK: vmr 2, 3 500; CHECK-BE-LABEL: shuffle_vector_byte_16_8 501; CHECK-BE: vsldoi 2, 2, 2, 1 502; CHECK-BE: vinsertb 3, 2, 0 503; CHECK-BE: vmr 2, 3 504 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 505 ret <16 x i8> %vecins 506} 507 508define <16 x i8> @shuffle_vector_byte_17_1(<16 x i8> %a, <16 x i8> %b) { 509entry: 510; CHECK-LABEL: shuffle_vector_byte_17_1 511; CHECK: vsldoi 2, 2, 2, 7 512; CHECK: vinsertb 3, 2, 14 513; CHECK: vmr 2, 3 514; CHECK-BE-LABEL: shuffle_vector_byte_17_1 515; CHECK-BE: vsldoi 2, 2, 2, 10 516; CHECK-BE: vinsertb 3, 2, 1 517; CHECK-BE: vmr 2, 3 518 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 1, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 519 ret <16 x i8> %vecins 520} 521 522define <16 x i8> @shuffle_vector_byte_18_10(<16 x i8> %a, <16 x i8> %b) { 523entry: 524; CHECK-LABEL: shuffle_vector_byte_18_10 525; CHECK: vsldoi 2, 2, 2, 14 526; CHECK: vinsertb 3, 2, 13 527; CHECK: vmr 2, 3 528; CHECK-BE-LABEL: shuffle_vector_byte_18_10 529; CHECK-BE: vsldoi 2, 2, 2, 3 530; CHECK-BE: vinsertb 3, 2, 2 531; CHECK-BE: vmr 2, 3 532 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 10, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 533 ret <16 x i8> %vecins 534} 535 536define <16 x i8> @shuffle_vector_byte_19_3(<16 x i8> %a, <16 x i8> %b) { 537entry: 538; CHECK-LABEL: shuffle_vector_byte_19_3 539; CHECK: vsldoi 2, 2, 2, 5 540; CHECK: vinsertb 3, 2, 12 541; CHECK: vmr 2, 3 542; CHECK-BE-LABEL: shuffle_vector_byte_19_3 543; CHECK-BE: vsldoi 2, 2, 2, 12 544; CHECK-BE: vinsertb 3, 2, 3 545; CHECK-BE: vmr 2, 3 546 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 3, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 547 ret <16 x i8> %vecins 548} 549 550define <16 x i8> @shuffle_vector_byte_20_12(<16 x i8> %a, <16 x i8> %b) { 551entry: 552; CHECK-LABEL: shuffle_vector_byte_20_12 553; CHECK: vsldoi 2, 2, 2, 12 554; CHECK: vinsertb 3, 2, 11 555; CHECK: vmr 2, 3 556; CHECK-BE-LABEL: shuffle_vector_byte_20_12 557; CHECK-BE: vsldoi 2, 2, 2, 5 558; CHECK-BE: vinsertb 3, 2, 4 559; CHECK-BE: vmr 2, 3 560 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 12, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 561 ret <16 x i8> %vecins 562} 563 564define <16 x i8> @shuffle_vector_byte_21_5(<16 x i8> %a, <16 x i8> %b) { 565entry: 566; CHECK-LABEL: shuffle_vector_byte_21_5 567; CHECK: vsldoi 2, 2, 2, 3 568; CHECK: vinsertb 3, 2, 10 569; CHECK: vmr 2, 3 570; CHECK-BE-LABEL: shuffle_vector_byte_21_5 571; CHECK-BE: vsldoi 2, 2, 2, 14 572; CHECK-BE: vinsertb 3, 2, 5 573; CHECK-BE: vmr 2, 3 574 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 575 ret <16 x i8> %vecins 576} 577 578define <16 x i8> @shuffle_vector_byte_22_14(<16 x i8> %a, <16 x i8> %b) { 579entry: 580; CHECK-LABEL: shuffle_vector_byte_22_14 581; CHECK: vsldoi 2, 2, 2, 10 582; CHECK: vinsertb 3, 2, 9 583; CHECK: vmr 2, 3 584; CHECK-BE-LABEL: shuffle_vector_byte_22_14 585; CHECK-BE: vsldoi 2, 2, 2, 7 586; CHECK-BE: vinsertb 3, 2, 6 587; CHECK-BE: vmr 2, 3 588 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 14, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 589 ret <16 x i8> %vecins 590} 591 592define <16 x i8> @shuffle_vector_byte_23_7(<16 x i8> %a, <16 x i8> %b) { 593entry: 594; CHECK-LABEL: shuffle_vector_byte_23_7 595; CHECK: vsldoi 2, 2, 2, 1 596; CHECK: vinsertb 3, 2, 8 597; CHECK: vmr 2, 3 598; CHECK-BE-LABEL: shuffle_vector_byte_23_7 599; CHECK-BE: vinsertb 3, 2, 7 600; CHECK-BE: vmr 2, 3 601 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 602 ret <16 x i8> %vecins 603} 604 605define <16 x i8> @shuffle_vector_byte_24_0(<16 x i8> %a, <16 x i8> %b) { 606entry: 607; CHECK-LABEL: shuffle_vector_byte_24_0 608; CHECK: vsldoi 2, 2, 2, 8 609; CHECK: vinsertb 3, 2, 7 610; CHECK: vmr 2, 3 611; CHECK-BE-LABEL: shuffle_vector_byte_24_0 612; CHECK-BE: vsldoi 2, 2, 2, 9 613; CHECK-BE: vinsertb 3, 2, 8 614; CHECK-BE: vmr 2, 3 615 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 0, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 616 ret <16 x i8> %vecins 617} 618 619define <16 x i8> @shuffle_vector_byte_25_9(<16 x i8> %a, <16 x i8> %b) { 620entry: 621; CHECK-LABEL: shuffle_vector_byte_25_9 622; CHECK: vsldoi 2, 2, 2, 15 623; CHECK: vinsertb 3, 2, 6 624; CHECK: vmr 2, 3 625; CHECK-BE-LABEL: shuffle_vector_byte_25_9 626; CHECK-BE: vsldoi 2, 2, 2, 2 627; CHECK-BE: vinsertb 3, 2, 9 628; CHECK-BE: vmr 2, 3 629 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 9, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> 630 ret <16 x i8> %vecins 631} 632 633define <16 x i8> @shuffle_vector_byte_26_2(<16 x i8> %a, <16 x i8> %b) { 634entry: 635; CHECK-LABEL: shuffle_vector_byte_26_2 636; CHECK: vsldoi 2, 2, 2, 6 637; CHECK: vinsertb 3, 2, 5 638; CHECK: vmr 2, 3 639; CHECK-BE-LABEL: shuffle_vector_byte_26_2 640; CHECK-BE: vsldoi 2, 2, 2, 11 641; CHECK-BE: vinsertb 3, 2, 10 642; CHECK-BE: vmr 2, 3 643 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 2, i32 27, i32 28, i32 29, i32 30, i32 31> 644 ret <16 x i8> %vecins 645} 646 647define <16 x i8> @shuffle_vector_byte_27_11(<16 x i8> %a, <16 x i8> %b) { 648entry: 649; CHECK-LABEL: shuffle_vector_byte_27_11 650; CHECK: vsldoi 2, 2, 2, 13 651; CHECK: vinsertb 3, 2, 4 652; CHECK: vmr 2, 3 653; CHECK-BE-LABEL: shuffle_vector_byte_27_11 654; CHECK-BE: vsldoi 2, 2, 2, 4 655; CHECK-BE: vinsertb 3, 2, 11 656; CHECK-BE: vmr 2, 3 657 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 11, i32 28, i32 29, i32 30, i32 31> 658 ret <16 x i8> %vecins 659} 660 661define <16 x i8> @shuffle_vector_byte_28_4(<16 x i8> %a, <16 x i8> %b) { 662entry: 663; CHECK-LABEL: shuffle_vector_byte_28_4 664; CHECK: vsldoi 2, 2, 2, 4 665; CHECK: vinsertb 3, 2, 3 666; CHECK: vmr 2, 3 667; CHECK-BE-LABEL: shuffle_vector_byte_28_4 668; CHECK-BE: vsldoi 2, 2, 2, 13 669; CHECK-BE: vinsertb 3, 2, 12 670; CHECK-BE: vmr 2, 3 671 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 4, i32 29, i32 30, i32 31> 672 ret <16 x i8> %vecins 673} 674 675define <16 x i8> @shuffle_vector_byte_29_13(<16 x i8> %a, <16 x i8> %b) { 676entry: 677; CHECK-LABEL: shuffle_vector_byte_29_13 678; CHECK: vsldoi 2, 2, 2, 11 679; CHECK: vinsertb 3, 2, 2 680; CHECK: vmr 2, 3 681; CHECK-BE-LABEL: shuffle_vector_byte_29_13 682; CHECK-BE: vsldoi 2, 2, 2, 6 683; CHECK-BE: vinsertb 3, 2, 13 684; CHECK-BE: vmr 2, 3 685 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 13, i32 30, i32 31> 686 ret <16 x i8> %vecins 687} 688 689define <16 x i8> @shuffle_vector_byte_30_6(<16 x i8> %a, <16 x i8> %b) { 690entry: 691; CHECK-LABEL: shuffle_vector_byte_30_6 692; CHECK: vsldoi 2, 2, 2, 2 693; CHECK: vinsertb 3, 2, 1 694; CHECK: vmr 2, 3 695; CHECK-BE-LABEL: shuffle_vector_byte_30_6 696; CHECK-BE: vsldoi 2, 2, 2, 15 697; CHECK-BE: vinsertb 3, 2, 14 698; CHECK-BE: vmr 2, 3 699 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 6, i32 31> 700 ret <16 x i8> %vecins 701} 702 703define <16 x i8> @shuffle_vector_byte_31_15(<16 x i8> %a, <16 x i8> %b) { 704entry: 705; CHECK-LABEL: shuffle_vector_byte_31_15 706; CHECK: vsldoi 2, 2, 2, 9 707; CHECK: vinsertb 3, 2, 0 708; CHECK: vmr 2, 3 709; CHECK-BE-LABEL: shuffle_vector_byte_31_15 710; CHECK-BE: vsldoi 2, 2, 2, 8 711; CHECK-BE: vinsertb 3, 2, 15 712; CHECK-BE: vmr 2, 3 713 %vecins = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 15> 714 ret <16 x i8> %vecins 715} 716 717; The following testcases use the same vector in both arguments of the 718; shufflevector. If byte element 7 in BE mode(or 8 in LE mode) is the one 719; we're attempting to insert, then we can use the vector insert instruction 720define <16 x i8> @shuffle_vector_byte_0_7(<16 x i8> %a) { 721entry: 722; CHECK-LABEL: shuffle_vector_byte_0_7 723; CHECK-NOT: vinsertb 724; CHECK-BE-LABEL: shuffle_vector_byte_0_7 725; CHECK-BE: vinsertb 2, 2, 0 726 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 7, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 727 ret <16 x i8> %vecins 728} 729 730define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { 731entry: 732; CHECK-LABEL: shuffle_vector_byte_1_8 733; CHECK: vinsertb 2, 2, 14 734; CHECK-BE-LABEL: shuffle_vector_byte_1_8 735; CHECK-BE-NOT: vinsertb 736 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 8, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 737 ret <16 x i8> %vecins 738} 739 740define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { 741entry: 742; CHECK-LABEL: shuffle_vector_byte_2_8 743; CHECK: vinsertb 2, 2, 13 744; CHECK-BE-LABEL: shuffle_vector_byte_2_8 745; CHECK-BE-NOT: vinsertb 746 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 747 ret <16 x i8> %vecins 748} 749 750define <16 x i8> @shuffle_vector_byte_3_7(<16 x i8> %a) { 751entry: 752; CHECK-LABEL: shuffle_vector_byte_3_7 753; CHECK-NOT: vinsertb 754; CHECK-BE-LABEL: shuffle_vector_byte_3_7 755; CHECK-BE: vinsertb 2, 2, 3 756 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 757 ret <16 x i8> %vecins 758} 759 760define <16 x i8> @shuffle_vector_byte_4_7(<16 x i8> %a) { 761entry: 762; CHECK-LABEL: shuffle_vector_byte_4_7 763; CHECK-NOT: vinsertb 764; CHECK-BE-LABEL: shuffle_vector_byte_4_7 765; CHECK-BE: vinsertb 2, 2, 4 766 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 7, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 767 ret <16 x i8> %vecins 768} 769 770define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { 771entry: 772; CHECK-LABEL: shuffle_vector_byte_5_8 773; CHECK: vinsertb 2, 2, 10 774; CHECK-BE-LABEL: shuffle_vector_byte_5_8 775; CHECK-BE-NOT: vinsertb 776 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 777 ret <16 x i8> %vecins 778} 779 780define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { 781entry: 782; CHECK-LABEL: shuffle_vector_byte_6_8 783; CHECK: vinsertb 2, 2, 9 784; CHECK-BE-LABEL: shuffle_vector_byte_6_8 785; CHECK-BE-NOT: vinsertb 786 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 787 ret <16 x i8> %vecins 788} 789 790define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { 791entry: 792; CHECK-LABEL: shuffle_vector_byte_7_8 793; CHECK: vinsertb 2, 2, 8 794; CHECK-BE-LABEL: shuffle_vector_byte_7_8 795; CHECK-BE-NOT: vinsertb 796 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 8, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 797 ret <16 x i8> %vecins 798} 799 800define <16 x i8> @shuffle_vector_byte_8_7(<16 x i8> %a) { 801entry: 802; CHECK-LABEL: shuffle_vector_byte_8_7 803; CHECK-NOT: vinsertb 804; CHECK-BE-LABEL: shuffle_vector_byte_8_7 805; CHECK-BE: vinsertb 2, 2, 8 806 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 7, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 807 ret <16 x i8> %vecins 808} 809 810define <16 x i8> @shuffle_vector_byte_9_7(<16 x i8> %a) { 811entry: 812; CHECK-LABEL: shuffle_vector_byte_9_7 813; CHECK-NOT: vinsertb 814; CHECK-BE-LABEL: shuffle_vector_byte_9_7 815; CHECK-BE: vinsertb 2, 2, 9 816 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 7, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 817 ret <16 x i8> %vecins 818} 819 820define <16 x i8> @shuffle_vector_byte_10_7(<16 x i8> %a) { 821entry: 822; CHECK-LABEL: shuffle_vector_byte_10_7 823; CHECK-NOT: vinsertb 824; CHECK-BE-LABEL: shuffle_vector_byte_10_7 825; CHECK-BE: vinsertb 2, 2, 10 826 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 7, i32 11, i32 12, i32 13, i32 14, i32 15> 827 ret <16 x i8> %vecins 828} 829 830define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { 831entry: 832; CHECK-LABEL: shuffle_vector_byte_11_8 833; CHECK: vinsertb 2, 2, 4 834; CHECK-BE-LABEL: shuffle_vector_byte_11_8 835; CHECK-BE-NOT: vinsertb 836 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 8, i32 12, i32 13, i32 14, i32 15> 837 ret <16 x i8> %vecins 838} 839 840define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { 841entry: 842; CHECK-LABEL: shuffle_vector_byte_12_8 843; CHECK: vinsertb 2, 2, 3 844; CHECK-BE-LABEL: shuffle_vector_byte_12_8 845; CHECK-BE-NOT: vinsertb 846 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 13, i32 14, i32 15> 847 ret <16 x i8> %vecins 848} 849 850define <16 x i8> @shuffle_vector_byte_13_7(<16 x i8> %a) { 851entry: 852; CHECK-LABEL: shuffle_vector_byte_13_7 853; CHECK-NOT: vinsertb 854; CHECK-BE-LABEL: shuffle_vector_byte_13_7 855; CHECK-BE: vinsertb 2, 2, 13 856 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 7, i32 14, i32 15> 857 ret <16 x i8> %vecins 858} 859 860define <16 x i8> @shuffle_vector_byte_14_7(<16 x i8> %a) { 861entry: 862; CHECK-LABEL: shuffle_vector_byte_14_7 863; CHECK-NOT: vinsertb 864; CHECK-BE-LABEL: shuffle_vector_byte_14_7 865; CHECK-BE: vinsertb 2, 2, 14 866 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 7, i32 15> 867 ret <16 x i8> %vecins 868} 869 870define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { 871entry: 872; CHECK-LABEL: shuffle_vector_byte_15_8 873; CHECK: vinsertb 2, 2, 0 874; CHECK-BE-LABEL: shuffle_vector_byte_15_8 875; CHECK-BE-NOT: vinsertb 876 %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 8> 877 ret <16 x i8> %vecins 878} 879