1; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s 2; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE 3 4; The build[csilf] functions simply test the scalar_to_vector handling with 5; direct moves. This corresponds to the "insertelement" instruction. Subsequent 6; to this, there will be a splat corresponding to the shufflevector. 7 8@d = common global double 0.000000e+00, align 8 9 10; Function Attrs: nounwind 11define <16 x i8> @buildc(i8 zeroext %a) { 12entry: 13 %a.addr = alloca i8, align 1 14 store i8 %a, i8* %a.addr, align 1 15 %0 = load i8, i8* %a.addr, align 1 16 %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0 17 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer 18 ret <16 x i8> %splat.splat 19; CHECK: sldi [[REG1:[0-9]+]], 3, 56 20; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] 21; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 22; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] 23} 24 25; Function Attrs: nounwind 26define <8 x i16> @builds(i16 zeroext %a) { 27entry: 28 %a.addr = alloca i16, align 2 29 store i16 %a, i16* %a.addr, align 2 30 %0 = load i16, i16* %a.addr, align 2 31 %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0 32 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer 33 ret <8 x i16> %splat.splat 34; CHECK: sldi [[REG1:[0-9]+]], 3, 48 35; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] 36; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 37; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] 38} 39 40; Function Attrs: nounwind 41define <4 x i32> @buildi(i32 zeroext %a) { 42entry: 43 %a.addr = alloca i32, align 4 44 store i32 %a, i32* %a.addr, align 4 45 %0 = load i32, i32* %a.addr, align 4 46 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 47 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 48 ret <4 x i32> %splat.splat 49; CHECK: mtvsrwz [[REG1:[0-9]+]], 3 50; CHECK: xxspltw 34, [[REG1]] 51; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3 52; CHECK-LE: xxspltw 34, [[REG1]] 53} 54 55; Function Attrs: nounwind 56define <2 x i64> @buildl(i64 %a) { 57entry: 58 %a.addr = alloca i64, align 8 59 store i64 %a, i64* %a.addr, align 8 60 %0 = load i64, i64* %a.addr, align 8 61 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 62 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 63 ret <2 x i64> %splat.splat 64; CHECK: mtvsrd {{[0-9]+}}, 3 65; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 66; CHECK-LE: xxspltd 34, [[REG1]], 0 67} 68 69; Function Attrs: nounwind 70define <4 x float> @buildf(float %a) { 71entry: 72 %a.addr = alloca float, align 4 73 store float %a, float* %a.addr, align 4 74 %0 = load float, float* %a.addr, align 4 75 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 76 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 77 ret <4 x float> %splat.splat 78; CHECK: xscvdpspn [[REG1:[0-9]+]], 1 79; CHECK: xxspltw 34, [[REG1]] 80; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1 81; CHECK-LE: xxspltw 34, [[REG1]] 82} 83 84; The optimization to remove stack operations from PPCDAGToDAGISel::Select 85; should still trigger for v2f64, producing an lxvdsx. 86; Function Attrs: nounwind 87define <2 x double> @buildd() #0 { 88entry: 89 %0 = load double, double* @d, align 8 90 %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 91 %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer 92 ret <2 x double> %splat.splat 93; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l 94; CHECK: lxvdsx 34, 0, [[REG1]] 95; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l 96; CHECK-LE: lxvdsx 34, 0, [[REG1]] 97} 98 99; Function Attrs: nounwind 100define signext i8 @getsc0(<16 x i8> %vsc) { 101entry: 102 %vsc.addr = alloca <16 x i8>, align 16 103 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 104 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 105 %vecext = extractelement <16 x i8> %0, i32 0 106 ret i8 %vecext 107; CHECK-LABEL: @getsc0 108; CHECK: mfvsrd 3, 34 109; CHECK: rldicl 3, 3, 8, 56 110; CHECK: extsb 3, 3 111; CHECK-LE-LABEL: @getsc0 112; CHECK-LE: mfvsrd 3, 113; CHECK-LE: clrldi 3, 3, 56 114; CHECK-LE: extsb 3, 3 115} 116 117; Function Attrs: nounwind 118define signext i8 @getsc1(<16 x i8> %vsc) { 119entry: 120 %vsc.addr = alloca <16 x i8>, align 16 121 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 122 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 123 %vecext = extractelement <16 x i8> %0, i32 1 124 ret i8 %vecext 125; CHECK-LABEL: @getsc1 126; CHECK: mfvsrd 3, 34 127; CHECK: rldicl 3, 3, 16, 56 128; CHECK: extsb 3, 3 129; CHECK-LE-LABEL: @getsc1 130; CHECK-LE: mfvsrd 3, 131; CHECK-LE: rldicl 3, 3, 56, 56 132; CHECK-LE: extsb 3, 3 133} 134 135; Function Attrs: nounwind 136define signext i8 @getsc2(<16 x i8> %vsc) { 137entry: 138 %vsc.addr = alloca <16 x i8>, align 16 139 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 140 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 141 %vecext = extractelement <16 x i8> %0, i32 2 142 ret i8 %vecext 143; CHECK-LABEL: @getsc2 144; CHECK: mfvsrd 3, 34 145; CHECK: rldicl 3, 3, 24, 56 146; CHECK: extsb 3, 3 147; CHECK-LE-LABEL: @getsc2 148; CHECK-LE: mfvsrd 3, 149; CHECK-LE: rldicl 3, 3, 48, 56 150; CHECK-LE: extsb 3, 3 151} 152 153; Function Attrs: nounwind 154define signext i8 @getsc3(<16 x i8> %vsc) { 155entry: 156 %vsc.addr = alloca <16 x i8>, align 16 157 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 158 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 159 %vecext = extractelement <16 x i8> %0, i32 3 160 ret i8 %vecext 161; CHECK-LABEL: @getsc3 162; CHECK: mfvsrd 3, 34 163; CHECK: rldicl 3, 3, 32, 56 164; CHECK: extsb 3, 3 165; CHECK-LE-LABEL: @getsc3 166; CHECK-LE: mfvsrd 3, 167; CHECK-LE: rldicl 3, 3, 40, 56 168; CHECK-LE: extsb 3, 3 169} 170 171; Function Attrs: nounwind 172define signext i8 @getsc4(<16 x i8> %vsc) { 173entry: 174 %vsc.addr = alloca <16 x i8>, align 16 175 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 176 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 177 %vecext = extractelement <16 x i8> %0, i32 4 178 ret i8 %vecext 179; CHECK-LABEL: @getsc4 180; CHECK: mfvsrd 3, 34 181; CHECK: rldicl 3, 3, 40, 56 182; CHECK: extsb 3, 3 183; CHECK-LE-LABEL: @getsc4 184; CHECK-LE: mfvsrd 3, 185; CHECK-LE: rldicl 3, 3, 32, 56 186; CHECK-LE: extsb 3, 3 187} 188 189; Function Attrs: nounwind 190define signext i8 @getsc5(<16 x i8> %vsc) { 191entry: 192 %vsc.addr = alloca <16 x i8>, align 16 193 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 194 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 195 %vecext = extractelement <16 x i8> %0, i32 5 196 ret i8 %vecext 197; CHECK-LABEL: @getsc5 198; CHECK: mfvsrd 3, 34 199; CHECK: rldicl 3, 3, 48, 56 200; CHECK: extsb 3, 3 201; CHECK-LE-LABEL: @getsc5 202; CHECK-LE: mfvsrd 3, 203; CHECK-LE: rldicl 3, 3, 24, 56 204; CHECK-LE: extsb 3, 3 205} 206 207; Function Attrs: nounwind 208define signext i8 @getsc6(<16 x i8> %vsc) { 209entry: 210 %vsc.addr = alloca <16 x i8>, align 16 211 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 212 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 213 %vecext = extractelement <16 x i8> %0, i32 6 214 ret i8 %vecext 215; CHECK-LABEL: @getsc6 216; CHECK: mfvsrd 3, 34 217; CHECK: rldicl 3, 3, 56, 56 218; CHECK: extsb 3, 3 219; CHECK-LE-LABEL: @getsc6 220; CHECK-LE: mfvsrd 3, 221; CHECK-LE: rldicl 3, 3, 16, 56 222; CHECK-LE: extsb 3, 3 223} 224 225; Function Attrs: nounwind 226define signext i8 @getsc7(<16 x i8> %vsc) { 227entry: 228 %vsc.addr = alloca <16 x i8>, align 16 229 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 230 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 231 %vecext = extractelement <16 x i8> %0, i32 7 232 ret i8 %vecext 233; CHECK-LABEL: @getsc7 234; CHECK: mfvsrd 3, 34 235; CHECK: clrldi 3, 3, 56 236; CHECK: extsb 3, 3 237; CHECK-LE-LABEL: @getsc7 238; CHECK-LE: mfvsrd 3, 239; CHECK-LE: rldicl 3, 3, 8, 56 240; CHECK-LE: extsb 3, 3 241} 242 243; Function Attrs: nounwind 244define signext i8 @getsc8(<16 x i8> %vsc) { 245entry: 246 %vsc.addr = alloca <16 x i8>, align 16 247 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 248 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 249 %vecext = extractelement <16 x i8> %0, i32 8 250 ret i8 %vecext 251; CHECK-LABEL: @getsc8 252; CHECK: mfvsrd 3, 253; CHECK: rldicl 3, 3, 8, 56 254; CHECK: extsb 3, 3 255; CHECK-LE-LABEL: @getsc8 256; CHECK-LE: mfvsrd 3, 34 257; CHECK-LE: clrldi 3, 3, 56 258; CHECK-LE: extsb 3, 3 259} 260 261; Function Attrs: nounwind 262define signext i8 @getsc9(<16 x i8> %vsc) { 263entry: 264 %vsc.addr = alloca <16 x i8>, align 16 265 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 266 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 267 %vecext = extractelement <16 x i8> %0, i32 9 268 ret i8 %vecext 269; CHECK-LABEL: @getsc9 270; CHECK: mfvsrd 3, 271; CHECK: rldicl 3, 3, 16, 56 272; CHECK: extsb 3, 3 273; CHECK-LE-LABEL: @getsc9 274; CHECK-LE: mfvsrd 3, 34 275; CHECK-LE: rldicl 3, 3, 56, 56 276; CHECK-LE: extsb 3, 3 277} 278 279; Function Attrs: nounwind 280define signext i8 @getsc10(<16 x i8> %vsc) { 281entry: 282 %vsc.addr = alloca <16 x i8>, align 16 283 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 284 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 285 %vecext = extractelement <16 x i8> %0, i32 10 286 ret i8 %vecext 287; CHECK-LABEL: @getsc10 288; CHECK: mfvsrd 3, 289; CHECK: rldicl 3, 3, 24, 56 290; CHECK: extsb 3, 3 291; CHECK-LE-LABEL: @getsc10 292; CHECK-LE: mfvsrd 3, 34 293; CHECK-LE: rldicl 3, 3, 48, 56 294; CHECK-LE: extsb 3, 3 295} 296 297; Function Attrs: nounwind 298define signext i8 @getsc11(<16 x i8> %vsc) { 299entry: 300 %vsc.addr = alloca <16 x i8>, align 16 301 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 302 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 303 %vecext = extractelement <16 x i8> %0, i32 11 304 ret i8 %vecext 305; CHECK-LABEL: @getsc11 306; CHECK: mfvsrd 3, 307; CHECK: rldicl 3, 3, 32, 56 308; CHECK: extsb 3, 3 309; CHECK-LE-LABEL: @getsc11 310; CHECK-LE: mfvsrd 3, 34 311; CHECK-LE: rldicl 3, 3, 40, 56 312; CHECK-LE: extsb 3, 3 313} 314 315; Function Attrs: nounwind 316define signext i8 @getsc12(<16 x i8> %vsc) { 317entry: 318 %vsc.addr = alloca <16 x i8>, align 16 319 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 320 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 321 %vecext = extractelement <16 x i8> %0, i32 12 322 ret i8 %vecext 323; CHECK-LABEL: @getsc12 324; CHECK: mfvsrd 3, 325; CHECK: rldicl 3, 3, 40, 56 326; CHECK: extsb 3, 3 327; CHECK-LE-LABEL: @getsc12 328; CHECK-LE: mfvsrd 3, 34 329; CHECK-LE: rldicl 3, 3, 32, 56 330; CHECK-LE: extsb 3, 3 331} 332 333; Function Attrs: nounwind 334define signext i8 @getsc13(<16 x i8> %vsc) { 335entry: 336 %vsc.addr = alloca <16 x i8>, align 16 337 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 338 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 339 %vecext = extractelement <16 x i8> %0, i32 13 340 ret i8 %vecext 341; CHECK-LABEL: @getsc13 342; CHECK: mfvsrd 3, 343; CHECK: rldicl 3, 3, 48, 56 344; CHECK: extsb 3, 3 345; CHECK-LE-LABEL: @getsc13 346; CHECK-LE: mfvsrd 3, 34 347; CHECK-LE: rldicl 3, 3, 24, 56 348; CHECK-LE: extsb 3, 3 349} 350 351; Function Attrs: nounwind 352define signext i8 @getsc14(<16 x i8> %vsc) { 353entry: 354 %vsc.addr = alloca <16 x i8>, align 16 355 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 356 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 357 %vecext = extractelement <16 x i8> %0, i32 14 358 ret i8 %vecext 359; CHECK-LABEL: @getsc14 360; CHECK: mfvsrd 3, 361; CHECK: rldicl 3, 3, 56, 56 362; CHECK: extsb 3, 3 363; CHECK-LE-LABEL: @getsc14 364; CHECK-LE: mfvsrd 3, 34 365; CHECK-LE: rldicl 3, 3, 16, 56 366; CHECK-LE: extsb 3, 3 367} 368 369; Function Attrs: nounwind 370define signext i8 @getsc15(<16 x i8> %vsc) { 371entry: 372 %vsc.addr = alloca <16 x i8>, align 16 373 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 374 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 375 %vecext = extractelement <16 x i8> %0, i32 15 376 ret i8 %vecext 377; CHECK-LABEL: @getsc15 378; CHECK: mfvsrd 3, 379; CHECK: extsb 3, 3 380; CHECK-LE-LABEL: @getsc15 381; CHECK-LE: mfvsrd 3, 34 382; CHECK-LE: rldicl 3, 3, 8, 56 383; CHECK-LE: extsb 3, 3 384} 385 386; Function Attrs: nounwind 387define zeroext i8 @getuc0(<16 x i8> %vuc) { 388entry: 389 %vuc.addr = alloca <16 x i8>, align 16 390 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 391 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 392 %vecext = extractelement <16 x i8> %0, i32 0 393 ret i8 %vecext 394; CHECK-LABEL: @getuc0 395; CHECK: mfvsrd 3, 34 396; CHECK: rldicl 3, 3, 8, 56 397; CHECK: clrldi 3, 3, 56 398; CHECK-LE-LABEL: @getuc0 399; CHECK-LE: mfvsrd 3, 400; CHECK-LE: clrldi 3, 3, 56 401} 402 403; Function Attrs: nounwind 404define zeroext i8 @getuc1(<16 x i8> %vuc) { 405entry: 406 %vuc.addr = alloca <16 x i8>, align 16 407 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 408 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 409 %vecext = extractelement <16 x i8> %0, i32 1 410 ret i8 %vecext 411; CHECK-LABEL: @getuc1 412; CHECK: mfvsrd 3, 34 413; CHECK: rldicl 3, 3, 16, 56 414; CHECK: clrldi 3, 3, 56 415; CHECK-LE-LABEL: @getuc1 416; CHECK-LE: mfvsrd 3, 417; CHECK-LE: rldicl 3, 3, 56, 56 418; CHECK-LE: clrldi 3, 3, 56 419} 420 421; Function Attrs: nounwind 422define zeroext i8 @getuc2(<16 x i8> %vuc) { 423entry: 424 %vuc.addr = alloca <16 x i8>, align 16 425 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 426 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 427 %vecext = extractelement <16 x i8> %0, i32 2 428 ret i8 %vecext 429; CHECK-LABEL: @getuc2 430; CHECK: mfvsrd 3, 34 431; CHECK: rldicl 3, 3, 24, 56 432; CHECK: clrldi 3, 3, 56 433; CHECK-LE-LABEL: @getuc2 434; CHECK-LE: mfvsrd 3, 435; CHECK-LE: rldicl 3, 3, 48, 56 436; CHECK-LE: clrldi 3, 3, 56 437} 438 439; Function Attrs: nounwind 440define zeroext i8 @getuc3(<16 x i8> %vuc) { 441entry: 442 %vuc.addr = alloca <16 x i8>, align 16 443 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 444 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 445 %vecext = extractelement <16 x i8> %0, i32 3 446 ret i8 %vecext 447; CHECK-LABEL: @getuc3 448; CHECK: mfvsrd 3, 34 449; CHECK: rldicl 3, 3, 32, 56 450; CHECK: clrldi 3, 3, 56 451; CHECK-LE-LABEL: @getuc3 452; CHECK-LE: mfvsrd 3, 453; CHECK-LE: rldicl 3, 3, 40, 56 454; CHECK-LE: clrldi 3, 3, 56 455} 456 457; Function Attrs: nounwind 458define zeroext i8 @getuc4(<16 x i8> %vuc) { 459entry: 460 %vuc.addr = alloca <16 x i8>, align 16 461 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 462 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 463 %vecext = extractelement <16 x i8> %0, i32 4 464 ret i8 %vecext 465; CHECK-LABEL: @getuc4 466; CHECK: mfvsrd 3, 34 467; CHECK: rldicl 3, 3, 40, 56 468; CHECK: clrldi 3, 3, 56 469; CHECK-LE-LABEL: @getuc4 470; CHECK-LE: mfvsrd 3, 471; CHECK-LE: rldicl 3, 3, 32, 56 472; CHECK-LE: clrldi 3, 3, 56 473} 474 475; Function Attrs: nounwind 476define zeroext i8 @getuc5(<16 x i8> %vuc) { 477entry: 478 %vuc.addr = alloca <16 x i8>, align 16 479 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 480 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 481 %vecext = extractelement <16 x i8> %0, i32 5 482 ret i8 %vecext 483; CHECK-LABEL: @getuc5 484; CHECK: mfvsrd 3, 34 485; CHECK: rldicl 3, 3, 48, 56 486; CHECK: clrldi 3, 3, 56 487; CHECK-LE-LABEL: @getuc5 488; CHECK-LE: mfvsrd 3, 489; CHECK-LE: rldicl 3, 3, 24, 56 490; CHECK-LE: clrldi 3, 3, 56 491} 492 493; Function Attrs: nounwind 494define zeroext i8 @getuc6(<16 x i8> %vuc) { 495entry: 496 %vuc.addr = alloca <16 x i8>, align 16 497 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 498 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 499 %vecext = extractelement <16 x i8> %0, i32 6 500 ret i8 %vecext 501; CHECK-LABEL: @getuc6 502; CHECK: mfvsrd 3, 34 503; CHECK: rldicl 3, 3, 56, 56 504; CHECK: clrldi 3, 3, 56 505; CHECK-LE-LABEL: @getuc6 506; CHECK-LE: mfvsrd 3, 507; CHECK-LE: rldicl 3, 3, 16, 56 508; CHECK-LE: clrldi 3, 3, 56 509} 510 511; Function Attrs: nounwind 512define zeroext i8 @getuc7(<16 x i8> %vuc) { 513entry: 514 %vuc.addr = alloca <16 x i8>, align 16 515 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 516 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 517 %vecext = extractelement <16 x i8> %0, i32 7 518 ret i8 %vecext 519; CHECK-LABEL: @getuc7 520; CHECK: mfvsrd 3, 34 521; CHECK: clrldi 3, 3, 56 522; CHECK-LE-LABEL: @getuc7 523; CHECK-LE: mfvsrd 3, 524; CHECK-LE: rldicl 3, 3, 8, 56 525; CHECK-LE: clrldi 3, 3, 56 526} 527 528; Function Attrs: nounwind 529define zeroext i8 @getuc8(<16 x i8> %vuc) { 530entry: 531 %vuc.addr = alloca <16 x i8>, align 16 532 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 533 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 534 %vecext = extractelement <16 x i8> %0, i32 8 535 ret i8 %vecext 536; CHECK-LABEL: @getuc8 537; CHECK: mfvsrd 3, 538; CHECK: rldicl 3, 3, 8, 56 539; CHECK: clrldi 3, 3, 56 540; CHECK-LE-LABEL: @getuc8 541; CHECK-LE: mfvsrd 3, 34 542; CHECK-LE: clrldi 3, 3, 56 543} 544 545; Function Attrs: nounwind 546define zeroext i8 @getuc9(<16 x i8> %vuc) { 547entry: 548 %vuc.addr = alloca <16 x i8>, align 16 549 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 550 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 551 %vecext = extractelement <16 x i8> %0, i32 9 552 ret i8 %vecext 553; CHECK-LABEL: @getuc9 554; CHECK: mfvsrd 3, 555; CHECK: rldicl 3, 3, 16, 56 556; CHECK: clrldi 3, 3, 56 557; CHECK-LE-LABEL: @getuc9 558; CHECK-LE: mfvsrd 3, 34 559; CHECK-LE: rldicl 3, 3, 56, 56 560; CHECK-LE: clrldi 3, 3, 56 561} 562 563; Function Attrs: nounwind 564define zeroext i8 @getuc10(<16 x i8> %vuc) { 565entry: 566 %vuc.addr = alloca <16 x i8>, align 16 567 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 568 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 569 %vecext = extractelement <16 x i8> %0, i32 10 570 ret i8 %vecext 571; CHECK-LABEL: @getuc10 572; CHECK: mfvsrd 3, 573; CHECK: rldicl 3, 3, 24, 56 574; CHECK: clrldi 3, 3, 56 575; CHECK-LE-LABEL: @getuc10 576; CHECK-LE: mfvsrd 3, 34 577; CHECK-LE: rldicl 3, 3, 48, 56 578; CHECK-LE: clrldi 3, 3, 56 579} 580 581; Function Attrs: nounwind 582define zeroext i8 @getuc11(<16 x i8> %vuc) { 583entry: 584 %vuc.addr = alloca <16 x i8>, align 16 585 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 586 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 587 %vecext = extractelement <16 x i8> %0, i32 11 588 ret i8 %vecext 589; CHECK-LABEL: @getuc11 590; CHECK: mfvsrd 3, 591; CHECK: rldicl 3, 3, 32, 56 592; CHECK: clrldi 3, 3, 56 593; CHECK-LE-LABEL: @getuc11 594; CHECK-LE: mfvsrd 3, 34 595; CHECK-LE: rldicl 3, 3, 40, 56 596; CHECK-LE: clrldi 3, 3, 56 597} 598 599; Function Attrs: nounwind 600define zeroext i8 @getuc12(<16 x i8> %vuc) { 601entry: 602 %vuc.addr = alloca <16 x i8>, align 16 603 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 604 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 605 %vecext = extractelement <16 x i8> %0, i32 12 606 ret i8 %vecext 607; CHECK-LABEL: @getuc12 608; CHECK: mfvsrd 3, 609; CHECK: rldicl 3, 3, 40, 56 610; CHECK: clrldi 3, 3, 56 611; CHECK-LE-LABEL: @getuc12 612; CHECK-LE: mfvsrd 3, 34 613; CHECK-LE: rldicl 3, 3, 32, 56 614; CHECK-LE: clrldi 3, 3, 56 615} 616 617; Function Attrs: nounwind 618define zeroext i8 @getuc13(<16 x i8> %vuc) { 619entry: 620 %vuc.addr = alloca <16 x i8>, align 16 621 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 622 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 623 %vecext = extractelement <16 x i8> %0, i32 13 624 ret i8 %vecext 625; CHECK-LABEL: @getuc13 626; CHECK: mfvsrd 3, 627; CHECK: rldicl 3, 3, 48, 56 628; CHECK: clrldi 3, 3, 56 629; CHECK-LE-LABEL: @getuc13 630; CHECK-LE: mfvsrd 3, 34 631; CHECK-LE: rldicl 3, 3, 24, 56 632; CHECK-LE: clrldi 3, 3, 56 633} 634 635; Function Attrs: nounwind 636define zeroext i8 @getuc14(<16 x i8> %vuc) { 637entry: 638 %vuc.addr = alloca <16 x i8>, align 16 639 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 640 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 641 %vecext = extractelement <16 x i8> %0, i32 14 642 ret i8 %vecext 643; CHECK-LABEL: @getuc14 644; CHECK: mfvsrd 3, 645; CHECK: rldicl 3, 3, 56, 56 646; CHECK: clrldi 3, 3, 56 647; CHECK-LE-LABEL: @getuc14 648; CHECK-LE: mfvsrd 3, 34 649; CHECK-LE: rldicl 3, 3, 16, 56 650; CHECK-LE: clrldi 3, 3, 56 651} 652 653; Function Attrs: nounwind 654define zeroext i8 @getuc15(<16 x i8> %vuc) { 655entry: 656 %vuc.addr = alloca <16 x i8>, align 16 657 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 658 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 659 %vecext = extractelement <16 x i8> %0, i32 15 660 ret i8 %vecext 661; CHECK-LABEL: @getuc15 662; CHECK: mfvsrd 3, 663; CHECK: clrldi 3, 3, 56 664; CHECK-LE-LABEL: @getuc15 665; CHECK-LE: mfvsrd 3, 34 666; CHECK-LE: rldicl 3, 3, 8, 56 667; CHECK-LE: clrldi 3, 3, 56 668} 669 670; Function Attrs: nounwind 671define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { 672entry: 673 %vsc.addr = alloca <16 x i8>, align 16 674 %i.addr = alloca i32, align 4 675 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 676 store i32 %i, i32* %i.addr, align 4 677 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 678 %1 = load i32, i32* %i.addr, align 4 679 %vecext = extractelement <16 x i8> %0, i32 %1 680 ret i8 %vecext 681; CHECK-LABEL: @getvelsc 682; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 683; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] 684; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 685; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 686; CHECK-DAG: li [[IMM7:[0-9]+]], 7 687; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] 688; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 689; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 690; CHECK-DAG: extsb 3, 3 691; CHECK-LE-LABEL: @getvelsc 692; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 693; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] 694; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] 695; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 696; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 697; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 698; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] 699; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 700; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 701; CHECK-DAG-LE: extsb 3, 3 702} 703 704; Function Attrs: nounwind 705define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) { 706entry: 707 %vuc.addr = alloca <16 x i8>, align 16 708 %i.addr = alloca i32, align 4 709 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 710 store i32 %i, i32* %i.addr, align 4 711 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 712 %1 = load i32, i32* %i.addr, align 4 713 %vecext = extractelement <16 x i8> %0, i32 %1 714 ret i8 %vecext 715; CHECK-LABEL: @getveluc 716; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 717; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] 718; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 719; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 720; CHECK-DAG: li [[IMM7:[0-9]+]], 7 721; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] 722; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 723; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 724; CHECK-DAG: clrldi 3, 3, 56 725; CHECK-LE-LABEL: @getveluc 726; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 727; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] 728; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] 729; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 730; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 731; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 732; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] 733; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 734; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 735; CHECK-DAG-LE: clrldi 3, 3, 56 736} 737 738; Function Attrs: nounwind 739define signext i16 @getss0(<8 x i16> %vss) { 740entry: 741 %vss.addr = alloca <8 x i16>, align 16 742 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 743 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 744 %vecext = extractelement <8 x i16> %0, i32 0 745 ret i16 %vecext 746; CHECK-LABEL: @getss0 747; CHECK: mfvsrd 3, 34 748; CHECK: rldicl 3, 3, 16, 48 749; CHECK: extsh 3, 3 750; CHECK-LE-LABEL: @getss0 751; CHECK-LE: mfvsrd 3, 752; CHECK-LE: clrldi 3, 3, 48 753; CHECK-LE: extsh 3, 3 754} 755 756; Function Attrs: nounwind 757define signext i16 @getss1(<8 x i16> %vss) { 758entry: 759 %vss.addr = alloca <8 x i16>, align 16 760 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 761 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 762 %vecext = extractelement <8 x i16> %0, i32 1 763 ret i16 %vecext 764; CHECK-LABEL: @getss1 765; CHECK: mfvsrd 3, 34 766; CHECK: rldicl 3, 3, 32, 48 767; CHECK: extsh 3, 3 768; CHECK-LE-LABEL: @getss1 769; CHECK-LE: mfvsrd 3, 770; CHECK-LE: rldicl 3, 3, 48, 48 771; CHECK-LE: extsh 3, 3 772} 773 774; Function Attrs: nounwind 775define signext i16 @getss2(<8 x i16> %vss) { 776entry: 777 %vss.addr = alloca <8 x i16>, align 16 778 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 779 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 780 %vecext = extractelement <8 x i16> %0, i32 2 781 ret i16 %vecext 782; CHECK-LABEL: @getss2 783; CHECK: mfvsrd 3, 34 784; CHECK: rldicl 3, 3, 48, 48 785; CHECK: extsh 3, 3 786; CHECK-LE-LABEL: @getss2 787; CHECK-LE: mfvsrd 3, 788; CHECK-LE: rldicl 3, 3, 32, 48 789; CHECK-LE: extsh 3, 3 790} 791 792; Function Attrs: nounwind 793define signext i16 @getss3(<8 x i16> %vss) { 794entry: 795 %vss.addr = alloca <8 x i16>, align 16 796 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 797 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 798 %vecext = extractelement <8 x i16> %0, i32 3 799 ret i16 %vecext 800; CHECK-LABEL: @getss3 801; CHECK: mfvsrd 3, 34 802; CHECK: clrldi 3, 3, 48 803; CHECK: extsh 3, 3 804; CHECK-LE-LABEL: @getss3 805; CHECK-LE: mfvsrd 3, 806; CHECK-LE: rldicl 3, 3, 16, 48 807; CHECK-LE: extsh 3, 3 808} 809 810; Function Attrs: nounwind 811define signext i16 @getss4(<8 x i16> %vss) { 812entry: 813 %vss.addr = alloca <8 x i16>, align 16 814 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 815 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 816 %vecext = extractelement <8 x i16> %0, i32 4 817 ret i16 %vecext 818; CHECK-LABEL: @getss4 819; CHECK: mfvsrd 3, 820; CHECK: rldicl 3, 3, 16, 48 821; CHECK: extsh 3, 3 822; CHECK-LE-LABEL: @getss4 823; CHECK-LE: mfvsrd 3, 34 824; CHECK-LE: clrldi 3, 3, 48 825; CHECK-LE: extsh 3, 3 826} 827 828; Function Attrs: nounwind 829define signext i16 @getss5(<8 x i16> %vss) { 830entry: 831 %vss.addr = alloca <8 x i16>, align 16 832 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 833 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 834 %vecext = extractelement <8 x i16> %0, i32 5 835 ret i16 %vecext 836; CHECK-LABEL: @getss5 837; CHECK: mfvsrd 3, 838; CHECK: rldicl 3, 3, 32, 48 839; CHECK: extsh 3, 3 840; CHECK-LE-LABEL: @getss5 841; CHECK-LE: mfvsrd 3, 34 842; CHECK-LE: rldicl 3, 3, 48, 48 843; CHECK-LE: extsh 3, 3 844} 845 846; Function Attrs: nounwind 847define signext i16 @getss6(<8 x i16> %vss) { 848entry: 849 %vss.addr = alloca <8 x i16>, align 16 850 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 851 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 852 %vecext = extractelement <8 x i16> %0, i32 6 853 ret i16 %vecext 854; CHECK-LABEL: @getss6 855; CHECK: mfvsrd 3, 856; CHECK: rldicl 3, 3, 48, 48 857; CHECK: extsh 3, 3 858; CHECK-LE-LABEL: @getss6 859; CHECK-LE: mfvsrd 3, 34 860; CHECK-LE: rldicl 3, 3, 32, 48 861; CHECK-LE: extsh 3, 3 862} 863 864; Function Attrs: nounwind 865define signext i16 @getss7(<8 x i16> %vss) { 866entry: 867 %vss.addr = alloca <8 x i16>, align 16 868 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 869 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 870 %vecext = extractelement <8 x i16> %0, i32 7 871 ret i16 %vecext 872; CHECK-LABEL: @getss7 873; CHECK: mfvsrd 3, 874; CHECK: extsh 3, 3 875; CHECK-LE-LABEL: @getss7 876; CHECK-LE: mfvsrd 3, 34 877; CHECK-LE: rldicl 3, 3, 16, 48 878; CHECK-LE: extsh 3, 3 879} 880 881; Function Attrs: nounwind 882define zeroext i16 @getus0(<8 x i16> %vus) { 883entry: 884 %vus.addr = alloca <8 x i16>, align 16 885 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 886 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 887 %vecext = extractelement <8 x i16> %0, i32 0 888 ret i16 %vecext 889; CHECK-LABEL: @getus0 890; CHECK: mfvsrd 3, 34 891; CHECK: rldicl 3, 3, 16, 48 892; CHECK: clrldi 3, 3, 48 893; CHECK-LE-LABEL: @getus0 894; CHECK-LE: mfvsrd 3, 895; CHECK-LE: clrldi 3, 3, 48 896} 897 898; Function Attrs: nounwind 899define zeroext i16 @getus1(<8 x i16> %vus) { 900entry: 901 %vus.addr = alloca <8 x i16>, align 16 902 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 903 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 904 %vecext = extractelement <8 x i16> %0, i32 1 905 ret i16 %vecext 906; CHECK-LABEL: @getus1 907; CHECK: mfvsrd 3, 34 908; CHECK: rldicl 3, 3, 32, 48 909; CHECK: clrldi 3, 3, 48 910; CHECK-LE-LABEL: @getus1 911; CHECK-LE: mfvsrd 3, 912; CHECK-LE: rldicl 3, 3, 48, 48 913; CHECK-LE: clrldi 3, 3, 48 914} 915 916; Function Attrs: nounwind 917define zeroext i16 @getus2(<8 x i16> %vus) { 918entry: 919 %vus.addr = alloca <8 x i16>, align 16 920 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 921 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 922 %vecext = extractelement <8 x i16> %0, i32 2 923 ret i16 %vecext 924; CHECK-LABEL: @getus2 925; CHECK: mfvsrd 3, 34 926; CHECK: rldicl 3, 3, 48, 48 927; CHECK: clrldi 3, 3, 48 928; CHECK-LE-LABEL: @getus2 929; CHECK-LE: mfvsrd 3, 930; CHECK-LE: rldicl 3, 3, 32, 48 931; CHECK-LE: clrldi 3, 3, 48 932} 933 934; Function Attrs: nounwind 935define zeroext i16 @getus3(<8 x i16> %vus) { 936entry: 937 %vus.addr = alloca <8 x i16>, align 16 938 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 939 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 940 %vecext = extractelement <8 x i16> %0, i32 3 941 ret i16 %vecext 942; CHECK-LABEL: @getus3 943; CHECK: mfvsrd 3, 34 944; CHECK: clrldi 3, 3, 48 945; CHECK-LE-LABEL: @getus3 946; CHECK-LE: mfvsrd 3, 947; CHECK-LE: rldicl 3, 3, 16, 48 948; CHECK-LE: clrldi 3, 3, 48 949} 950 951; Function Attrs: nounwind 952define zeroext i16 @getus4(<8 x i16> %vus) { 953entry: 954 %vus.addr = alloca <8 x i16>, align 16 955 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 956 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 957 %vecext = extractelement <8 x i16> %0, i32 4 958 ret i16 %vecext 959; CHECK-LABEL: @getus4 960; CHECK: mfvsrd 3, 961; CHECK: rldicl 3, 3, 16, 48 962; CHECK: clrldi 3, 3, 48 963; CHECK-LE-LABEL: @getus4 964; CHECK-LE: mfvsrd 3, 34 965; CHECK-LE: clrldi 3, 3, 48 966} 967 968; Function Attrs: nounwind 969define zeroext i16 @getus5(<8 x i16> %vus) { 970entry: 971 %vus.addr = alloca <8 x i16>, align 16 972 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 973 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 974 %vecext = extractelement <8 x i16> %0, i32 5 975 ret i16 %vecext 976; CHECK-LABEL: @getus5 977; CHECK: mfvsrd 3, 978; CHECK: rldicl 3, 3, 32, 48 979; CHECK: clrldi 3, 3, 48 980; CHECK-LE-LABEL: @getus5 981; CHECK-LE: mfvsrd 3, 34 982; CHECK-LE: rldicl 3, 3, 48, 48 983; CHECK-LE: clrldi 3, 3, 48 984} 985 986; Function Attrs: nounwind 987define zeroext i16 @getus6(<8 x i16> %vus) { 988entry: 989 %vus.addr = alloca <8 x i16>, align 16 990 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 991 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 992 %vecext = extractelement <8 x i16> %0, i32 6 993 ret i16 %vecext 994; CHECK-LABEL: @getus6 995; CHECK: mfvsrd 3, 996; CHECK: rldicl 3, 3, 48, 48 997; CHECK: clrldi 3, 3, 48 998; CHECK-LE-LABEL: @getus6 999; CHECK-LE: mfvsrd 3, 34 1000; CHECK-LE: rldicl 3, 3, 32, 48 1001; CHECK-LE: clrldi 3, 3, 48 1002} 1003 1004; Function Attrs: nounwind 1005define zeroext i16 @getus7(<8 x i16> %vus) { 1006entry: 1007 %vus.addr = alloca <8 x i16>, align 16 1008 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 1009 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 1010 %vecext = extractelement <8 x i16> %0, i32 7 1011 ret i16 %vecext 1012; CHECK-LABEL: @getus7 1013; CHECK: mfvsrd 3, 1014; CHECK: clrldi 3, 3, 48 1015; CHECK-LE-LABEL: @getus7 1016; CHECK-LE: mfvsrd 3, 34 1017; CHECK-LE: rldicl 3, 3, 16, 48 1018; CHECK-LE: clrldi 3, 3, 48 1019} 1020 1021; Function Attrs: nounwind 1022define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { 1023entry: 1024 %vss.addr = alloca <8 x i16>, align 16 1025 %i.addr = alloca i32, align 4 1026 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 1027 store i32 %i, i32* %i.addr, align 4 1028 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 1029 %1 = load i32, i32* %i.addr, align 4 1030 %vecext = extractelement <8 x i16> %0, i32 %1 1031 ret i16 %vecext 1032; CHECK-LABEL: @getvelss 1033; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 1034; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 1035; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1036; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1037; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 1038; CHECK-DAG: li [[IMM3:[0-9]+]], 3 1039; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] 1040; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 1041; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 1042; CHECK-DAG: extsh 3, 3 1043; CHECK-LE-LABEL: @getvelss 1044; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 1045; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] 1046; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 1047; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1048; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1049; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 1050; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 1051; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] 1052; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 1053; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 1054; CHECK-DAG-LE: extsh 3, 3 1055} 1056 1057; Function Attrs: nounwind 1058define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) { 1059entry: 1060 %vus.addr = alloca <8 x i16>, align 16 1061 %i.addr = alloca i32, align 4 1062 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 1063 store i32 %i, i32* %i.addr, align 4 1064 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 1065 %1 = load i32, i32* %i.addr, align 4 1066 %vecext = extractelement <8 x i16> %0, i32 %1 1067 ret i16 %vecext 1068; CHECK-LABEL: @getvelus 1069; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 1070; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 1071; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1072; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1073; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 1074; CHECK-DAG: li [[IMM3:[0-9]+]], 3 1075; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] 1076; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 1077; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 1078; CHECK-DAG: clrldi 3, 3, 48 1079; CHECK-LE-LABEL: @getvelus 1080; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 1081; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] 1082; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 1083; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1084; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1085; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 1086; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 1087; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] 1088; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 1089; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 1090; CHECK-DAG-LE: clrldi 3, 3, 48 1091} 1092 1093; Function Attrs: nounwind 1094define signext i32 @getsi0(<4 x i32> %vsi) { 1095entry: 1096 %vsi.addr = alloca <4 x i32>, align 16 1097 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1098 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1099 %vecext = extractelement <4 x i32> %0, i32 0 1100 ret i32 %vecext 1101; CHECK-LABEL: @getsi0 1102; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1103; CHECK: mfvsrwz 3, [[SHL]] 1104; CHECK: extsw 3, 3 1105; CHECK-LE-LABEL: @getsi0 1106; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1107; CHECK-LE: mfvsrwz 3, [[SHL]] 1108; CHECK-LE: extsw 3, 3 1109} 1110 1111; Function Attrs: nounwind 1112define signext i32 @getsi1(<4 x i32> %vsi) { 1113entry: 1114 %vsi.addr = alloca <4 x i32>, align 16 1115 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1116 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1117 %vecext = extractelement <4 x i32> %0, i32 1 1118 ret i32 %vecext 1119; CHECK-LABEL: @getsi1 1120; CHECK: mfvsrwz 3, 34 1121; CHECK: extsw 3, 3 1122; CHECK-LE-LABEL: @getsi1 1123; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1124; CHECK-LE: mfvsrwz 3, [[SHL]] 1125; CHECK-LE: extsw 3, 3 1126} 1127 1128; Function Attrs: nounwind 1129define signext i32 @getsi2(<4 x i32> %vsi) { 1130entry: 1131 %vsi.addr = alloca <4 x i32>, align 16 1132 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1133 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1134 %vecext = extractelement <4 x i32> %0, i32 2 1135 ret i32 %vecext 1136; CHECK-LABEL: @getsi2 1137; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1138; CHECK: mfvsrwz 3, [[SHL]] 1139; CHECK: extsw 3, 3 1140; CHECK-LE-LABEL: @getsi2 1141; CHECK-LE: mfvsrwz 3, 34 1142; CHECK-LE: extsw 3, 3 1143} 1144 1145; Function Attrs: nounwind 1146define signext i32 @getsi3(<4 x i32> %vsi) { 1147entry: 1148 %vsi.addr = alloca <4 x i32>, align 16 1149 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1150 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1151 %vecext = extractelement <4 x i32> %0, i32 3 1152 ret i32 %vecext 1153; CHECK-LABEL: @getsi3 1154; CHECK: xxswapd [[SHL:[0-9]+]], 34 1155; CHECK: mfvsrwz 3, [[SHL]] 1156; CHECK: extsw 3, 3 1157; CHECK-LE-LABEL: @getsi3 1158; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1159; CHECK-LE: mfvsrwz 3, [[SHL]] 1160; CHECK-LE: extsw 3, 3 1161} 1162 1163; Function Attrs: nounwind 1164define zeroext i32 @getui0(<4 x i32> %vui) { 1165entry: 1166 %vui.addr = alloca <4 x i32>, align 16 1167 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1168 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1169 %vecext = extractelement <4 x i32> %0, i32 0 1170 ret i32 %vecext 1171; CHECK-LABEL: @getui0 1172; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1173; CHECK: mfvsrwz 3, [[SHL]] 1174; CHECK: clrldi 3, 3, 32 1175; CHECK-LE-LABEL: @getui0 1176; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1177; CHECK-LE: mfvsrwz 3, [[SHL]] 1178; CHECK-LE: clrldi 3, 3, 32 1179} 1180 1181; Function Attrs: nounwind 1182define zeroext i32 @getui1(<4 x i32> %vui) { 1183entry: 1184 %vui.addr = alloca <4 x i32>, align 16 1185 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1186 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1187 %vecext = extractelement <4 x i32> %0, i32 1 1188 ret i32 %vecext 1189; CHECK-LABEL: @getui1 1190; CHECK: mfvsrwz 3, 34 1191; CHECK: clrldi 3, 3, 32 1192; CHECK-LE-LABEL: @getui1 1193; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1194; CHECK-LE: mfvsrwz 3, [[SHL]] 1195; CHECK-LE: clrldi 3, 3, 32 1196} 1197 1198; Function Attrs: nounwind 1199define zeroext i32 @getui2(<4 x i32> %vui) { 1200entry: 1201 %vui.addr = alloca <4 x i32>, align 16 1202 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1203 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1204 %vecext = extractelement <4 x i32> %0, i32 2 1205 ret i32 %vecext 1206; CHECK-LABEL: @getui2 1207; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1208; CHECK: mfvsrwz 3, [[SHL]] 1209; CHECK: clrldi 3, 3, 32 1210; CHECK-LE-LABEL: @getui2 1211; CHECK-LE: mfvsrwz 3, 34 1212; CHECK-LE: clrldi 3, 3, 32 1213} 1214 1215; Function Attrs: nounwind 1216define zeroext i32 @getui3(<4 x i32> %vui) { 1217entry: 1218 %vui.addr = alloca <4 x i32>, align 16 1219 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1220 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1221 %vecext = extractelement <4 x i32> %0, i32 3 1222 ret i32 %vecext 1223; CHECK-LABEL: @getui3 1224; CHECK: xxswapd [[SHL:[0-9]+]], 34 1225; CHECK: mfvsrwz 3, [[SHL]] 1226; CHECK: clrldi 3, 3, 32 1227; CHECK-LE-LABEL: @getui3 1228; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1229; CHECK-LE: mfvsrwz 3, [[SHL]] 1230; CHECK-LE: clrldi 3, 3, 32 1231} 1232 1233; Function Attrs: nounwind 1234define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) { 1235entry: 1236 %vsi.addr = alloca <4 x i32>, align 16 1237 %i.addr = alloca i32, align 4 1238 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1239 store i32 %i, i32* %i.addr, align 4 1240 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1241 %1 = load i32, i32* %i.addr, align 4 1242 %vecext = extractelement <4 x i32> %0, i32 %1 1243 ret i32 %vecext 1244; CHECK-LABEL: @getvelsi 1245; CHECK-LE-LABEL: @getvelsi 1246; FIXME: add check patterns when variable element extraction is implemented 1247} 1248 1249; Function Attrs: nounwind 1250define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) { 1251entry: 1252 %vui.addr = alloca <4 x i32>, align 16 1253 %i.addr = alloca i32, align 4 1254 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1255 store i32 %i, i32* %i.addr, align 4 1256 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1257 %1 = load i32, i32* %i.addr, align 4 1258 %vecext = extractelement <4 x i32> %0, i32 %1 1259 ret i32 %vecext 1260; CHECK-LABEL: @getvelui 1261; CHECK-LE-LABEL: @getvelui 1262; FIXME: add check patterns when variable element extraction is implemented 1263} 1264 1265; Function Attrs: nounwind 1266define i64 @getsl0(<2 x i64> %vsl) { 1267entry: 1268 %vsl.addr = alloca <2 x i64>, align 16 1269 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1270 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1271 %vecext = extractelement <2 x i64> %0, i32 0 1272 ret i64 %vecext 1273; CHECK-LABEL: @getsl0 1274; CHECK: mfvsrd 3, 34 1275; CHECK-LE-LABEL: @getsl0 1276; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 1277; CHECK-LE: mfvsrd 3, [[SWP]] 1278} 1279 1280; Function Attrs: nounwind 1281define i64 @getsl1(<2 x i64> %vsl) { 1282entry: 1283 %vsl.addr = alloca <2 x i64>, align 16 1284 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1285 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1286 %vecext = extractelement <2 x i64> %0, i32 1 1287 ret i64 %vecext 1288; CHECK-LABEL: @getsl1 1289; CHECK: xxswapd [[SWP:[0-9]+]], 34 1290; CHECK: mfvsrd 3, [[SWP]] 1291; CHECK-LE-LABEL: @getsl1 1292; CHECK-LE: mfvsrd 3, 34 1293} 1294 1295; Function Attrs: nounwind 1296define i64 @getul0(<2 x i64> %vul) { 1297entry: 1298 %vul.addr = alloca <2 x i64>, align 16 1299 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1300 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1301 %vecext = extractelement <2 x i64> %0, i32 0 1302 ret i64 %vecext 1303; CHECK-LABEL: @getul0 1304; CHECK: mfvsrd 3, 34 1305; CHECK-LE-LABEL: @getul0 1306; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 1307; CHECK-LE: mfvsrd 3, [[SWP]] 1308} 1309 1310; Function Attrs: nounwind 1311define i64 @getul1(<2 x i64> %vul) { 1312entry: 1313 %vul.addr = alloca <2 x i64>, align 16 1314 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1315 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1316 %vecext = extractelement <2 x i64> %0, i32 1 1317 ret i64 %vecext 1318; CHECK-LABEL: @getul1 1319; CHECK: xxswapd [[SWP:[0-9]+]], 34 1320; CHECK: mfvsrd 3, [[SWP]] 1321; CHECK-LE-LABEL: @getul1 1322; CHECK-LE: mfvsrd 3, 34 1323} 1324 1325; Function Attrs: nounwind 1326define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) { 1327entry: 1328 %vsl.addr = alloca <2 x i64>, align 16 1329 %i.addr = alloca i32, align 4 1330 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1331 store i32 %i, i32* %i.addr, align 4 1332 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1333 %1 = load i32, i32* %i.addr, align 4 1334 %vecext = extractelement <2 x i64> %0, i32 %1 1335 ret i64 %vecext 1336; CHECK-LABEL: @getvelsl 1337; CHECK-LE-LABEL: @getvelsl 1338; FIXME: add check patterns when variable element extraction is implemented 1339} 1340 1341; Function Attrs: nounwind 1342define i64 @getvelul(<2 x i64> %vul, i32 signext %i) { 1343entry: 1344 %vul.addr = alloca <2 x i64>, align 16 1345 %i.addr = alloca i32, align 4 1346 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1347 store i32 %i, i32* %i.addr, align 4 1348 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1349 %1 = load i32, i32* %i.addr, align 4 1350 %vecext = extractelement <2 x i64> %0, i32 %1 1351 ret i64 %vecext 1352; CHECK-LABEL: @getvelul 1353; CHECK-LE-LABEL: @getvelul 1354; FIXME: add check patterns when variable element extraction is implemented 1355} 1356 1357; Function Attrs: nounwind 1358define float @getf0(<4 x float> %vf) { 1359entry: 1360 %vf.addr = alloca <4 x float>, align 16 1361 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1362 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1363 %vecext = extractelement <4 x float> %0, i32 0 1364 ret float %vecext 1365; CHECK-LABEL: @getf0 1366; CHECK: xscvspdpn 1, 34 1367; CHECK-LE-LABEL: @getf0 1368; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1369; CHECK-LE: xscvspdpn 1, [[SHL]] 1370} 1371 1372; Function Attrs: nounwind 1373define float @getf1(<4 x float> %vf) { 1374entry: 1375 %vf.addr = alloca <4 x float>, align 16 1376 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1377 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1378 %vecext = extractelement <4 x float> %0, i32 1 1379 ret float %vecext 1380; CHECK-LABEL: @getf1 1381; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1382; CHECK: xscvspdpn 1, [[SHL]] 1383; CHECK-LE-LABEL: @getf1 1384; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1385; CHECK-LE: xscvspdpn 1, [[SHL]] 1386} 1387 1388; Function Attrs: nounwind 1389define float @getf2(<4 x float> %vf) { 1390entry: 1391 %vf.addr = alloca <4 x float>, align 16 1392 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1393 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1394 %vecext = extractelement <4 x float> %0, i32 2 1395 ret float %vecext 1396; CHECK-LABEL: @getf2 1397; CHECK: xxswapd [[SHL:[0-9]+]], 34 1398; CHECK: xscvspdpn 1, [[SHL]] 1399; CHECK-LE-LABEL: @getf2 1400; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1401; CHECK-LE: xscvspdpn 1, [[SHL]] 1402} 1403 1404; Function Attrs: nounwind 1405define float @getf3(<4 x float> %vf) { 1406entry: 1407 %vf.addr = alloca <4 x float>, align 16 1408 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1409 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1410 %vecext = extractelement <4 x float> %0, i32 3 1411 ret float %vecext 1412; CHECK-LABEL: @getf3 1413; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1414; CHECK: xscvspdpn 1, [[SHL]] 1415; CHECK-LE-LABEL: @getf3 1416; CHECK-LE: xscvspdpn 1, 34 1417} 1418 1419; Function Attrs: nounwind 1420define float @getvelf(<4 x float> %vf, i32 signext %i) { 1421entry: 1422 %vf.addr = alloca <4 x float>, align 16 1423 %i.addr = alloca i32, align 4 1424 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1425 store i32 %i, i32* %i.addr, align 4 1426 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1427 %1 = load i32, i32* %i.addr, align 4 1428 %vecext = extractelement <4 x float> %0, i32 %1 1429 ret float %vecext 1430; CHECK-LABEL: @getvelf 1431; CHECK-LE-LABEL: @getvelf 1432; FIXME: add check patterns when variable element extraction is implemented 1433} 1434 1435; Function Attrs: nounwind 1436define double @getd0(<2 x double> %vd) { 1437entry: 1438 %vd.addr = alloca <2 x double>, align 16 1439 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1440 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1441 %vecext = extractelement <2 x double> %0, i32 0 1442 ret double %vecext 1443; CHECK-LABEL: @getd0 1444; CHECK: xxlor 1, 34, 34 1445; CHECK-LE-LABEL: @getd0 1446; CHECK-LE: xxswapd 1, 34 1447} 1448 1449; Function Attrs: nounwind 1450define double @getd1(<2 x double> %vd) { 1451entry: 1452 %vd.addr = alloca <2 x double>, align 16 1453 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1454 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1455 %vecext = extractelement <2 x double> %0, i32 1 1456 ret double %vecext 1457; CHECK-LABEL: @getd1 1458; CHECK: xxswapd 1, 34 1459; CHECK-LE-LABEL: @getd1 1460; CHECK-LE: xxlor 1, 34, 34 1461} 1462 1463; Function Attrs: nounwind 1464define double @getveld(<2 x double> %vd, i32 signext %i) { 1465entry: 1466 %vd.addr = alloca <2 x double>, align 16 1467 %i.addr = alloca i32, align 4 1468 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1469 store i32 %i, i32* %i.addr, align 4 1470 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1471 %1 = load i32, i32* %i.addr, align 4 1472 %vecext = extractelement <2 x double> %0, i32 %1 1473 ret double %vecext 1474; CHECK-LABEL: @getveld 1475; CHECK-LE-LABEL: @getveld 1476; FIXME: add check patterns when variable element extraction is implemented 1477} 1478