1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN:   FileCheck %s
5
6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
7; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
8; RUN:   FileCheck %s
9
10; These test cases demonstrate that the vector shift quadword instructions
11; introduced within Power10 are correctly exploited.
12
13define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) {
14; CHECK-LABEL: test_vec_vslq:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    vslq v2, v2, v3
17; CHECK-NEXT:    blr
18entry:
19  %rem = urem <1 x i128> %b, <i128 128>
20  %shl = shl <1 x i128> %a, %rem
21  ret <1 x i128> %shl
22}
23
24define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) {
25; CHECK-LABEL: test_vec_vsrq:
26; CHECK:       # %bb.0: # %entry
27; CHECK-NEXT:    vsrq v2, v2, v3
28; CHECK-NEXT:    blr
29entry:
30  %rem = urem <1 x i128> %b, <i128 128>
31  %shr = lshr <1 x i128> %a, %rem
32  ret <1 x i128> %shr
33}
34
35define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) {
36; CHECK-LABEL: test_vec_vsraq:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    vsraq v2, v2, v3
39; CHECK-NEXT:    blr
40entry:
41  %rem = urem <1 x i128> %b, <i128 128>
42  %shr = ashr <1 x i128> %a, %rem
43  ret <1 x i128> %shr
44}
45
46define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) {
47; CHECK-LABEL: test_vec_vslq2:
48; CHECK:       # %bb.0: # %entry
49; CHECK-NEXT:    vslq v2, v2, v3
50; CHECK-NEXT:    blr
51entry:
52  %shl = shl <1 x i128> %a, %b
53  ret <1 x i128> %shl
54}
55
56define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) {
57; CHECK-LABEL: test_vec_vsrq2:
58; CHECK:       # %bb.0: # %entry
59; CHECK-NEXT:    vsrq v2, v2, v3
60; CHECK-NEXT:    blr
61entry:
62  %shr = lshr <1 x i128> %a, %b
63  ret <1 x i128> %shr
64}
65
66define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) {
67; CHECK-LABEL: test_vec_vsraq2:
68; CHECK:       # %bb.0: # %entry
69; CHECK-NEXT:    vsraq v2, v2, v3
70; CHECK-NEXT:    blr
71entry:
72  %shr = ashr <1 x i128> %a, %b
73  ret <1 x i128> %shr
74}
75