1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN:   FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN:   FileCheck %s
8
9; This test case aims to test the vector modulo instructions on Power10.
10; The vector modulo instructions operate on signed and unsigned words
11; and doublewords.
12
13define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {
14; CHECK-LABEL: test_vmodud:
15; CHECK:       # %bb.0: # %entry
16; CHECK-NEXT:    vmodud v2, v2, v3
17; CHECK-NEXT:    blr
18entry:
19  %rem = urem <2 x i64> %a, %b
20  ret <2 x i64> %rem
21}
22
23define <2 x i64> @test_vmodsd(<2 x i64> %a, <2 x i64> %b) {
24; CHECK-LABEL: test_vmodsd:
25; CHECK:       # %bb.0: # %entry
26; CHECK-NEXT:    vmodsd v2, v2, v3
27; CHECK-NEXT:    blr
28entry:
29  %rem = srem <2 x i64> %a, %b
30  ret <2 x i64> %rem
31}
32
33define <4 x i32> @test_vmoduw(<4 x i32> %a, <4 x i32> %b) {
34; CHECK-LABEL: test_vmoduw:
35; CHECK:       # %bb.0: # %entry
36; CHECK-NEXT:    vmoduw v2, v2, v3
37; CHECK-NEXT:    blr
38entry:
39  %rem = urem <4 x i32> %a, %b
40  ret <4 x i32> %rem
41}
42
43define <4 x i32> @test_vmodsw(<4 x i32> %a, <4 x i32> %b) {
44; CHECK-LABEL: test_vmodsw:
45; CHECK:       # %bb.0: # %entry
46; CHECK-NEXT:    vmodsw v2, v2, v3
47; CHECK-NEXT:    blr
48entry:
49  %rem = srem <4 x i32> %a, %b
50  ret <4 x i32> %rem
51}
52
53define <2 x i64> @test_vmodud_with_div(<2 x i64> %a, <2 x i64> %b) {
54; CHECK-LABEL: test_vmodud_with_div:
55; CHECK:       # %bb.0: # %entry
56; CHECK-NEXT:    vmodud v4, v2, v3
57; CHECK-NEXT:    vdivud v2, v2, v3
58; CHECK-NEXT:    vaddudm v2, v4, v2
59; CHECK-NEXT:    blr
60entry:
61  %rem = urem <2 x i64> %a, %b
62  %div = udiv <2 x i64> %a, %b
63  %add = add <2 x i64> %rem, %div
64  ret <2 x i64> %add
65}
66
67define <2 x i64> @test_vmodsd_with_div(<2 x i64> %a, <2 x i64> %b) {
68; CHECK-LABEL: test_vmodsd_with_div:
69; CHECK:       # %bb.0: # %entry
70; CHECK-NEXT:    vmodsd v4, v2, v3
71; CHECK-NEXT:    vdivsd v2, v2, v3
72; CHECK-NEXT:    vaddudm v2, v4, v2
73; CHECK-NEXT:    blr
74entry:
75  %rem = srem <2 x i64> %a, %b
76  %div = sdiv <2 x i64> %a, %b
77  %add = add <2 x i64> %rem, %div
78  ret <2 x i64> %add
79}
80
81define <4 x i32> @test_vmoduw_with_div(<4 x i32> %a, <4 x i32> %b) {
82; CHECK-LABEL: test_vmoduw_with_div:
83; CHECK:       # %bb.0: # %entry
84; CHECK-NEXT:    vmoduw v4, v2, v3
85; CHECK-NEXT:    vdivuw v2, v2, v3
86; CHECK-NEXT:    vadduwm v2, v4, v2
87; CHECK-NEXT:    blr
88entry:
89  %rem = urem <4 x i32> %a, %b
90  %div = udiv <4 x i32> %a, %b
91  %add = add <4 x i32> %rem, %div
92  ret <4 x i32> %add
93}
94
95define <4 x i32> @test_vmodsw_div(<4 x i32> %a, <4 x i32> %b) {
96; CHECK-LABEL: test_vmodsw_div:
97; CHECK:       # %bb.0: # %entry
98; CHECK-NEXT:    vmodsw v4, v2, v3
99; CHECK-NEXT:    vdivsw v2, v2, v3
100; CHECK-NEXT:    vadduwm v2, v4, v2
101; CHECK-NEXT:    blr
102entry:
103  %rem = srem <4 x i32> %a, %b
104  %div = sdiv <4 x i32> %a, %b
105  %add = add <4 x i32> %rem, %div
106  ret <4 x i32> %add
107}
108