1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
4; RUN:   -check-prefix=P9
5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
7; RUN:   -check-prefix=P8
8; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
10; RUN:   -check-prefix=P7
11; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
13; RUN:   -check-prefix=P9-AIX32
14; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
15; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
16; RUN:   -check-prefix=P8-AIX32
17; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
18; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
19; RUN:   -check-prefix=P7-AIX32
20
21; v2f64
22define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
23; P9-LABEL: test:
24; P9:       # %bb.0: # %entry
25; P9-NEXT:    addi r4, r4, 24
26; P9-NEXT:    lxvdsx vs0, 0, r4
27; P9-NEXT:    stxv vs0, 0(r3)
28; P9-NEXT:    blr
29;
30; P8-LABEL: test:
31; P8:       # %bb.0: # %entry
32; P8-NEXT:    addi r4, r4, 24
33; P8-NEXT:    lxvdsx vs0, 0, r4
34; P8-NEXT:    stxvd2x vs0, 0, r3
35; P8-NEXT:    blr
36;
37; P7-LABEL: test:
38; P7:       # %bb.0: # %entry
39; P7-NEXT:    addi r4, r4, 24
40; P7-NEXT:    lxvdsx vs0, 0, r4
41; P7-NEXT:    stxvd2x vs0, 0, r3
42; P7-NEXT:    blr
43;
44; P9-AIX32-LABEL: test:
45; P9-AIX32:       # %bb.0: # %entry
46; P9-AIX32-NEXT:    addi r4, r4, 24
47; P9-AIX32-NEXT:    lxvdsx vs0, 0, r4
48; P9-AIX32-NEXT:    stxv vs0, 0(r3)
49; P9-AIX32-NEXT:    blr
50;
51; P8-AIX32-LABEL: test:
52; P8-AIX32:       # %bb.0: # %entry
53; P8-AIX32-NEXT:    addi r4, r4, 24
54; P8-AIX32-NEXT:    lxvdsx vs0, 0, r4
55; P8-AIX32-NEXT:    stxvd2x vs0, 0, r3
56; P8-AIX32-NEXT:    blr
57;
58; P7-AIX32-LABEL: test:
59; P7-AIX32:       # %bb.0: # %entry
60; P7-AIX32-NEXT:    addi r4, r4, 24
61; P7-AIX32-NEXT:    lxvdsx vs0, 0, r4
62; P7-AIX32-NEXT:    stxvd2x vs0, 0, r3
63; P7-AIX32-NEXT:    blr
64entry:
65  %arrayidx = getelementptr inbounds double, double* %a, i64 3
66  %0 = load double, double* %arrayidx, align 8
67  %splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
68  %splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> zeroinitializer
69  store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
70  ret void
71}
72
73; v4f32
74define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonly %a) local_unnamed_addr {
75; P9-LABEL: test2:
76; P9:       # %bb.0: # %entry
77; P9-NEXT:    addi r4, r4, 12
78; P9-NEXT:    lxvwsx vs0, 0, r4
79; P9-NEXT:    stxv vs0, 0(r3)
80; P9-NEXT:    blr
81;
82; P8-LABEL: test2:
83; P8:       # %bb.0: # %entry
84; P8-NEXT:    addi r4, r4, 12
85; P8-NEXT:    lfiwzx f0, 0, r4
86; P8-NEXT:    xxspltw v2, vs0, 1
87; P8-NEXT:    stvx v2, 0, r3
88; P8-NEXT:    blr
89;
90; P7-LABEL: test2:
91; P7:       # %bb.0: # %entry
92; P7-NEXT:    addi r4, r4, 12
93; P7-NEXT:    lfiwzx f0, 0, r4
94; P7-NEXT:    xxspltw vs0, vs0, 1
95; P7-NEXT:    stxvw4x vs0, 0, r3
96; P7-NEXT:    blr
97;
98; P9-AIX32-LABEL: test2:
99; P9-AIX32:       # %bb.0: # %entry
100; P9-AIX32-NEXT:    addi r4, r4, 12
101; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
102; P9-AIX32-NEXT:    stxv vs0, 0(r3)
103; P9-AIX32-NEXT:    blr
104;
105; P8-AIX32-LABEL: test2:
106; P8-AIX32:       # %bb.0: # %entry
107; P8-AIX32-NEXT:    addi r4, r4, 12
108; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
109; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
110; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
111; P8-AIX32-NEXT:    blr
112;
113; P7-AIX32-LABEL: test2:
114; P7-AIX32:       # %bb.0: # %entry
115; P7-AIX32-NEXT:    addi r4, r4, 12
116; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
117; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
118; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
119; P7-AIX32-NEXT:    blr
120entry:
121  %arrayidx = getelementptr inbounds float, float* %a, i64 3
122  %0 = load float, float* %arrayidx, align 4
123  %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
124  %splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
125  store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
126  ret void
127}
128
129; v4i32
130define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
131; P9-LABEL: test3:
132; P9:       # %bb.0: # %entry
133; P9-NEXT:    addi r4, r4, 12
134; P9-NEXT:    lxvwsx vs0, 0, r4
135; P9-NEXT:    stxv vs0, 0(r3)
136; P9-NEXT:    blr
137;
138; P8-LABEL: test3:
139; P8:       # %bb.0: # %entry
140; P8-NEXT:    addi r4, r4, 12
141; P8-NEXT:    lfiwzx f0, 0, r4
142; P8-NEXT:    xxspltw v2, vs0, 1
143; P8-NEXT:    stvx v2, 0, r3
144; P8-NEXT:    blr
145;
146; P7-LABEL: test3:
147; P7:       # %bb.0: # %entry
148; P7-NEXT:    addi r4, r4, 12
149; P7-NEXT:    lfiwzx f0, 0, r4
150; P7-NEXT:    xxspltw vs0, vs0, 1
151; P7-NEXT:    stxvw4x vs0, 0, r3
152; P7-NEXT:    blr
153;
154; P9-AIX32-LABEL: test3:
155; P9-AIX32:       # %bb.0: # %entry
156; P9-AIX32-NEXT:    addi r4, r4, 12
157; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
158; P9-AIX32-NEXT:    stxv vs0, 0(r3)
159; P9-AIX32-NEXT:    blr
160;
161; P8-AIX32-LABEL: test3:
162; P8-AIX32:       # %bb.0: # %entry
163; P8-AIX32-NEXT:    addi r4, r4, 12
164; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
165; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
166; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
167; P8-AIX32-NEXT:    blr
168;
169; P7-AIX32-LABEL: test3:
170; P7-AIX32:       # %bb.0: # %entry
171; P7-AIX32-NEXT:    addi r4, r4, 12
172; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
173; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
174; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
175; P7-AIX32-NEXT:    blr
176entry:
177  %arrayidx = getelementptr inbounds i32, i32* %a, i64 3
178  %0 = load i32, i32* %arrayidx, align 4
179  %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
180  %splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
181  store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
182  ret void
183}
184
185
186; v2i64
187define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a) local_unnamed_addr {
188; P9-LABEL: test4:
189; P9:       # %bb.0: # %entry
190; P9-NEXT:    addi r4, r4, 24
191; P9-NEXT:    lxvdsx vs0, 0, r4
192; P9-NEXT:    stxv vs0, 0(r3)
193; P9-NEXT:    blr
194;
195; P8-LABEL: test4:
196; P8:       # %bb.0: # %entry
197; P8-NEXT:    addi r4, r4, 24
198; P8-NEXT:    lxvdsx vs0, 0, r4
199; P8-NEXT:    stxvd2x vs0, 0, r3
200; P8-NEXT:    blr
201;
202; P7-LABEL: test4:
203; P7:       # %bb.0: # %entry
204; P7-NEXT:    addi r4, r4, 24
205; P7-NEXT:    lxvdsx vs0, 0, r4
206; P7-NEXT:    stxvd2x vs0, 0, r3
207; P7-NEXT:    blr
208;
209; P9-AIX32-LABEL: test4:
210; P9-AIX32:       # %bb.0: # %entry
211; P9-AIX32-NEXT:    lwz r5, 24(r4)
212; P9-AIX32-NEXT:    lwz r4, 28(r4)
213; P9-AIX32-NEXT:    stw r4, -16(r1)
214; P9-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
215; P9-AIX32-NEXT:    stw r5, -32(r1)
216; P9-AIX32-NEXT:    lxv v3, -16(r1)
217; P9-AIX32-NEXT:    lxv v4, -32(r1)
218; P9-AIX32-NEXT:    lxv v2, 0(r4)
219; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
220; P9-AIX32-NEXT:    stxv v2, 0(r3)
221; P9-AIX32-NEXT:    blr
222;
223; P8-AIX32-LABEL: test4:
224; P8-AIX32:       # %bb.0: # %entry
225; P8-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
226; P8-AIX32-NEXT:    lwz r6, 28(r4)
227; P8-AIX32-NEXT:    lwz r4, 24(r4)
228; P8-AIX32-NEXT:    stw r6, -16(r1)
229; P8-AIX32-NEXT:    stw r4, -32(r1)
230; P8-AIX32-NEXT:    addi r4, r1, -16
231; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
232; P8-AIX32-NEXT:    addi r5, r1, -32
233; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
234; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
235; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
236; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
237; P8-AIX32-NEXT:    blr
238;
239; P7-AIX32-LABEL: test4:
240; P7-AIX32:       # %bb.0: # %entry
241; P7-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
242; P7-AIX32-NEXT:    lwz r6, 24(r4)
243; P7-AIX32-NEXT:    lwz r4, 28(r4)
244; P7-AIX32-NEXT:    stw r4, -16(r1)
245; P7-AIX32-NEXT:    stw r6, -32(r1)
246; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
247; P7-AIX32-NEXT:    addi r4, r1, -16
248; P7-AIX32-NEXT:    addi r5, r1, -32
249; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
250; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
251; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
252; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
253; P7-AIX32-NEXT:    blr
254entry:
255  %arrayidx = getelementptr inbounds i64, i64* %a, i64 3
256  %0 = load i64, i64* %arrayidx, align 8
257  %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
258  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
259  store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
260  ret void
261}
262
263; sext v2i64
264define void @test5(<2 x i64>* %a, i32* %in) {
265; P9-LABEL: test5:
266; P9:       # %bb.0: # %entry
267; P9-NEXT:    lfiwax f0, 0, r4
268; P9-NEXT:    xxspltd vs0, f0, 0
269; P9-NEXT:    stxv vs0, 0(r3)
270; P9-NEXT:    blr
271;
272; P8-LABEL: test5:
273; P8:       # %bb.0: # %entry
274; P8-NEXT:    lfiwax f0, 0, r4
275; P8-NEXT:    xxspltd vs0, f0, 0
276; P8-NEXT:    stxvd2x vs0, 0, r3
277; P8-NEXT:    blr
278;
279; P7-LABEL: test5:
280; P7:       # %bb.0: # %entry
281; P7-NEXT:    lfiwax f0, 0, r4
282; P7-NEXT:    xxspltd vs0, f0, 0
283; P7-NEXT:    stxvd2x vs0, 0, r3
284; P7-NEXT:    blr
285;
286; P9-AIX32-LABEL: test5:
287; P9-AIX32:       # %bb.0: # %entry
288; P9-AIX32-NEXT:    lwz r4, 0(r4)
289; P9-AIX32-NEXT:    srawi r5, r4, 31
290; P9-AIX32-NEXT:    stw r4, -16(r1)
291; P9-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
292; P9-AIX32-NEXT:    lxv v3, -16(r1)
293; P9-AIX32-NEXT:    stw r5, -32(r1)
294; P9-AIX32-NEXT:    lxv v4, -32(r1)
295; P9-AIX32-NEXT:    lxv v2, 0(r4)
296; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
297; P9-AIX32-NEXT:    stxv v2, 0(r3)
298; P9-AIX32-NEXT:    blr
299;
300; P8-AIX32-LABEL: test5:
301; P8-AIX32:       # %bb.0: # %entry
302; P8-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
303; P8-AIX32-NEXT:    lwz r4, 0(r4)
304; P8-AIX32-NEXT:    stw r4, -16(r1)
305; P8-AIX32-NEXT:    srawi r4, r4, 31
306; P8-AIX32-NEXT:    stw r4, -32(r1)
307; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
308; P8-AIX32-NEXT:    addi r4, r1, -16
309; P8-AIX32-NEXT:    addi r5, r1, -32
310; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
311; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
312; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
313; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
314; P8-AIX32-NEXT:    blr
315;
316; P7-AIX32-LABEL: test5:
317; P7-AIX32:       # %bb.0: # %entry
318; P7-AIX32-NEXT:    lwz r4, 0(r4)
319; P7-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
320; P7-AIX32-NEXT:    srawi r6, r4, 31
321; P7-AIX32-NEXT:    stw r4, -16(r1)
322; P7-AIX32-NEXT:    addi r4, r1, -16
323; P7-AIX32-NEXT:    stw r6, -32(r1)
324; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
325; P7-AIX32-NEXT:    addi r5, r1, -32
326; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
327; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
328; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
329; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
330; P7-AIX32-NEXT:    blr
331entry:
332  %0 = load i32, i32* %in, align 4
333  %conv = sext i32 %0 to i64
334  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
335  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
336  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
337  ret void
338}
339
340; zext v2i64
341define void @test6(<2 x i64>* %a, i32* %in) {
342; P9-LABEL: test6:
343; P9:       # %bb.0: # %entry
344; P9-NEXT:    lfiwzx f0, 0, r4
345; P9-NEXT:    xxspltd vs0, f0, 0
346; P9-NEXT:    stxv vs0, 0(r3)
347; P9-NEXT:    blr
348;
349; P8-LABEL: test6:
350; P8:       # %bb.0: # %entry
351; P8-NEXT:    lfiwzx f0, 0, r4
352; P8-NEXT:    xxspltd vs0, f0, 0
353; P8-NEXT:    stxvd2x vs0, 0, r3
354; P8-NEXT:    blr
355;
356; P7-LABEL: test6:
357; P7:       # %bb.0: # %entry
358; P7-NEXT:    lfiwzx f0, 0, r4
359; P7-NEXT:    xxspltd vs0, f0, 0
360; P7-NEXT:    stxvd2x vs0, 0, r3
361; P7-NEXT:    blr
362;
363; P9-AIX32-LABEL: test6:
364; P9-AIX32:       # %bb.0: # %entry
365; P9-AIX32-NEXT:    lwz r4, 0(r4)
366; P9-AIX32-NEXT:    li r5, 0
367; P9-AIX32-NEXT:    stw r5, -32(r1)
368; P9-AIX32-NEXT:    lxv v3, -32(r1)
369; P9-AIX32-NEXT:    stw r4, -16(r1)
370; P9-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
371; P9-AIX32-NEXT:    lxv v4, -16(r1)
372; P9-AIX32-NEXT:    lxv v2, 0(r4)
373; P9-AIX32-NEXT:    vperm v2, v3, v4, v2
374; P9-AIX32-NEXT:    stxv v2, 0(r3)
375; P9-AIX32-NEXT:    blr
376;
377; P8-AIX32-LABEL: test6:
378; P8-AIX32:       # %bb.0: # %entry
379; P8-AIX32-NEXT:    lwz r6, L..C2(r2) # %const.0
380; P8-AIX32-NEXT:    lwz r4, 0(r4)
381; P8-AIX32-NEXT:    li r5, 0
382; P8-AIX32-NEXT:    stw r5, -32(r1)
383; P8-AIX32-NEXT:    addi r5, r1, -16
384; P8-AIX32-NEXT:    stw r4, -16(r1)
385; P8-AIX32-NEXT:    addi r4, r1, -32
386; P8-AIX32-NEXT:    lxvw4x v2, 0, r6
387; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
388; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
389; P8-AIX32-NEXT:    vperm v2, v3, v4, v2
390; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
391; P8-AIX32-NEXT:    blr
392;
393; P7-AIX32-LABEL: test6:
394; P7-AIX32:       # %bb.0: # %entry
395; P7-AIX32-NEXT:    lwz r5, L..C2(r2) # %const.0
396; P7-AIX32-NEXT:    lwz r4, 0(r4)
397; P7-AIX32-NEXT:    li r6, 0
398; P7-AIX32-NEXT:    stw r6, -32(r1)
399; P7-AIX32-NEXT:    stw r4, -16(r1)
400; P7-AIX32-NEXT:    addi r4, r1, -32
401; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
402; P7-AIX32-NEXT:    addi r5, r1, -16
403; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
404; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
405; P7-AIX32-NEXT:    vperm v2, v3, v4, v2
406; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
407; P7-AIX32-NEXT:    blr
408entry:
409  %0 = load i32, i32* %in, align 4
410  %conv = zext i32 %0 to i64
411  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
412  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
413  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
414  ret void
415}
416
417; v8i16
418define void @test7(<8 x i16>* %a, i16* %in) {
419; P9-LABEL: test7:
420; P9:       # %bb.0: # %entry
421; P9-NEXT:    lxsihzx v2, 0, r4
422; P9-NEXT:    vsplth v2, v2, 3
423; P9-NEXT:    stxv v2, 0(r3)
424; P9-NEXT:    blr
425;
426; P8-LABEL: test7:
427; P8:       # %bb.0: # %entry
428; P8-NEXT:    lhzx r4, 0, r4
429; P8-NEXT:    mtvsrwz v2, r4
430; P8-NEXT:    vsplth v2, v2, 3
431; P8-NEXT:    stvx v2, 0, r3
432; P8-NEXT:    blr
433;
434; P7-LABEL: test7:
435; P7:       # %bb.0: # %entry
436; P7-NEXT:    li r5, 1
437; P7-NEXT:    lvx v2, 0, r4
438; P7-NEXT:    lvsl v4, 0, r4
439; P7-NEXT:    lvx v3, r5, r4
440; P7-NEXT:    vperm v2, v2, v3, v4
441; P7-NEXT:    vsplth v2, v2, 0
442; P7-NEXT:    stxvw4x v2, 0, r3
443; P7-NEXT:    blr
444;
445; P9-AIX32-LABEL: test7:
446; P9-AIX32:       # %bb.0: # %entry
447; P9-AIX32-NEXT:    lxsihzx v2, 0, r4
448; P9-AIX32-NEXT:    vsplth v2, v2, 3
449; P9-AIX32-NEXT:    stxv v2, 0(r3)
450; P9-AIX32-NEXT:    blr
451;
452; P8-AIX32-LABEL: test7:
453; P8-AIX32:       # %bb.0: # %entry
454; P8-AIX32-NEXT:    lhzx r4, 0, r4
455; P8-AIX32-NEXT:    mtvsrwz v2, r4
456; P8-AIX32-NEXT:    vsplth v2, v2, 3
457; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
458; P8-AIX32-NEXT:    blr
459;
460; P7-AIX32-LABEL: test7:
461; P7-AIX32:       # %bb.0: # %entry
462; P7-AIX32-NEXT:    li r5, 1
463; P7-AIX32-NEXT:    lvx v2, 0, r4
464; P7-AIX32-NEXT:    lvsl v4, 0, r4
465; P7-AIX32-NEXT:    lvx v3, r5, r4
466; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
467; P7-AIX32-NEXT:    vsplth v2, v2, 0
468; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
469; P7-AIX32-NEXT:    blr
470entry:
471  %0 = load i16, i16* %in, align 2
472  %splat.splatinsert.i = insertelement <8 x i16> poison, i16 %0, i32 0
473  %splat.splat.i = shufflevector <8 x i16> %splat.splatinsert.i, <8 x i16> poison, <8 x i32> zeroinitializer
474  store <8 x i16> %splat.splat.i, <8 x i16>* %a, align 16
475  ret void
476}
477
478; v16i8
479define void @test8(<16 x i8>* %a, i8* %in) {
480; P9-LABEL: test8:
481; P9:       # %bb.0: # %entry
482; P9-NEXT:    lxsibzx v2, 0, r4
483; P9-NEXT:    vspltb v2, v2, 7
484; P9-NEXT:    stxv v2, 0(r3)
485; P9-NEXT:    blr
486;
487; P8-LABEL: test8:
488; P8:       # %bb.0: # %entry
489; P8-NEXT:    lbzx r4, 0, r4
490; P8-NEXT:    mtvsrwz v2, r4
491; P8-NEXT:    vspltb v2, v2, 7
492; P8-NEXT:    stvx v2, 0, r3
493; P8-NEXT:    blr
494;
495; P7-LABEL: test8:
496; P7:       # %bb.0: # %entry
497; P7-NEXT:    lvsl v2, 0, r4
498; P7-NEXT:    lvx v3, 0, r4
499; P7-NEXT:    vperm v2, v3, v3, v2
500; P7-NEXT:    vspltb v2, v2, 0
501; P7-NEXT:    stxvw4x v2, 0, r3
502; P7-NEXT:    blr
503;
504; P9-AIX32-LABEL: test8:
505; P9-AIX32:       # %bb.0: # %entry
506; P9-AIX32-NEXT:    lxsibzx v2, 0, r4
507; P9-AIX32-NEXT:    vspltb v2, v2, 7
508; P9-AIX32-NEXT:    stxv v2, 0(r3)
509; P9-AIX32-NEXT:    blr
510;
511; P8-AIX32-LABEL: test8:
512; P8-AIX32:       # %bb.0: # %entry
513; P8-AIX32-NEXT:    lbzx r4, 0, r4
514; P8-AIX32-NEXT:    mtvsrwz v2, r4
515; P8-AIX32-NEXT:    vspltb v2, v2, 7
516; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
517; P8-AIX32-NEXT:    blr
518;
519; P7-AIX32-LABEL: test8:
520; P7-AIX32:       # %bb.0: # %entry
521; P7-AIX32-NEXT:    lvsl v2, 0, r4
522; P7-AIX32-NEXT:    lvx v3, 0, r4
523; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
524; P7-AIX32-NEXT:    vspltb v2, v2, 0
525; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
526; P7-AIX32-NEXT:    blr
527entry:
528  %0 = load i8, i8* %in, align 1
529  %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %0, i32 0
530  %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer
531  store <16 x i8> %splat.splat.i, <16 x i8>* %a, align 16
532  ret void
533}
534
535define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
536; P9-LABEL: unadjusted_lxvwsx:
537; P9:       # %bb.0: # %entry
538; P9-NEXT:    lxvwsx v2, 0, r3
539; P9-NEXT:    blr
540;
541; P8-LABEL: unadjusted_lxvwsx:
542; P8:       # %bb.0: # %entry
543; P8-NEXT:    lfiwzx f0, 0, r3
544; P8-NEXT:    xxspltw v2, vs0, 1
545; P8-NEXT:    blr
546;
547; P7-LABEL: unadjusted_lxvwsx:
548; P7:       # %bb.0: # %entry
549; P7-NEXT:    lfiwzx f0, 0, r3
550; P7-NEXT:    xxspltw v2, vs0, 1
551; P7-NEXT:    blr
552;
553; P9-AIX32-LABEL: unadjusted_lxvwsx:
554; P9-AIX32:       # %bb.0: # %entry
555; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
556; P9-AIX32-NEXT:    blr
557;
558; P8-AIX32-LABEL: unadjusted_lxvwsx:
559; P8-AIX32:       # %bb.0: # %entry
560; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
561; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
562; P8-AIX32-NEXT:    blr
563;
564; P7-AIX32-LABEL: unadjusted_lxvwsx:
565; P7-AIX32:       # %bb.0: # %entry
566; P7-AIX32-NEXT:    lfiwzx f0, 0, r3
567; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
568; P7-AIX32-NEXT:    blr
569  entry:
570    %0 = bitcast i32* %s to <4 x i8>*
571    %1 = load <4 x i8>, <4 x i8>* %0, align 4
572    %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
573    ret <16 x i8> %2
574}
575
576define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
577; P9-LABEL: adjusted_lxvwsx:
578; P9:       # %bb.0: # %entry
579; P9-NEXT:    addi r3, r3, 4
580; P9-NEXT:    lxvwsx v2, 0, r3
581; P9-NEXT:    blr
582;
583; P8-LABEL: adjusted_lxvwsx:
584; P8:       # %bb.0: # %entry
585; P8-NEXT:    lfdx f0, 0, r3
586; P8-NEXT:    xxspltw v2, vs0, 0
587; P8-NEXT:    blr
588;
589; P7-LABEL: adjusted_lxvwsx:
590; P7:       # %bb.0: # %entry
591; P7-NEXT:    ld r3, 0(r3)
592; P7-NEXT:    addi r4, r1, -16
593; P7-NEXT:    std r3, -16(r1)
594; P7-NEXT:    lxvw4x vs0, 0, r4
595; P7-NEXT:    xxspltw v2, vs0, 1
596; P7-NEXT:    blr
597;
598; P9-AIX32-LABEL: adjusted_lxvwsx:
599; P9-AIX32:       # %bb.0: # %entry
600; P9-AIX32-NEXT:    addi r3, r3, 4
601; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
602; P9-AIX32-NEXT:    blr
603;
604; P8-AIX32-LABEL: adjusted_lxvwsx:
605; P8-AIX32:       # %bb.0: # %entry
606; P8-AIX32-NEXT:    addi r3, r3, 4
607; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
608; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
609; P8-AIX32-NEXT:    blr
610;
611; P7-AIX32-LABEL: adjusted_lxvwsx:
612; P7-AIX32:       # %bb.0: # %entry
613; P7-AIX32-NEXT:    addi r3, r3, 4
614; P7-AIX32-NEXT:    lfiwzx f0, 0, r3
615; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
616; P7-AIX32-NEXT:    blr
617  entry:
618    %0 = bitcast i64* %s to <8 x i8>*
619    %1 = load <8 x i8>, <8 x i8>* %0, align 8
620    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
621    ret <16 x i8> %2
622}
623
624define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
625; P9-LABEL: unadjusted_lxvwsx_v16i8:
626; P9:       # %bb.0: # %entry
627; P9-NEXT:    lxvwsx v2, 0, r3
628; P9-NEXT:    blr
629;
630; P8-LABEL: unadjusted_lxvwsx_v16i8:
631; P8:       # %bb.0: # %entry
632; P8-NEXT:    lvx v2, 0, r3
633; P8-NEXT:    xxspltw v2, v2, 3
634; P8-NEXT:    blr
635;
636; P7-LABEL: unadjusted_lxvwsx_v16i8:
637; P7:       # %bb.0: # %entry
638; P7-NEXT:    lxvw4x vs0, 0, r3
639; P7-NEXT:    xxspltw v2, vs0, 0
640; P7-NEXT:    blr
641;
642; P9-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
643; P9-AIX32:       # %bb.0: # %entry
644; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
645; P9-AIX32-NEXT:    blr
646;
647; P8-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
648; P8-AIX32:       # %bb.0: # %entry
649; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
650; P8-AIX32-NEXT:    xxspltw v2, vs0, 0
651; P8-AIX32-NEXT:    blr
652;
653; P7-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
654; P7-AIX32:       # %bb.0: # %entry
655; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
656; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
657; P7-AIX32-NEXT:    blr
658  entry:
659    %0 = load <16 x i8>, <16 x i8>* %s, align 16
660    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
661    ret <16 x i8> %1
662}
663
664define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
665; P9-LABEL: adjusted_lxvwsx_v16i8:
666; P9:       # %bb.0: # %entry
667; P9-NEXT:    addi r3, r3, 4
668; P9-NEXT:    lxvwsx v2, 0, r3
669; P9-NEXT:    blr
670;
671; P8-LABEL: adjusted_lxvwsx_v16i8:
672; P8:       # %bb.0: # %entry
673; P8-NEXT:    lvx v2, 0, r3
674; P8-NEXT:    xxspltw v2, v2, 2
675; P8-NEXT:    blr
676;
677; P7-LABEL: adjusted_lxvwsx_v16i8:
678; P7:       # %bb.0: # %entry
679; P7-NEXT:    lxvw4x vs0, 0, r3
680; P7-NEXT:    xxspltw v2, vs0, 1
681; P7-NEXT:    blr
682;
683; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8:
684; P9-AIX32:       # %bb.0: # %entry
685; P9-AIX32-NEXT:    addi r3, r3, 4
686; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
687; P9-AIX32-NEXT:    blr
688;
689; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8:
690; P8-AIX32:       # %bb.0: # %entry
691; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
692; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
693; P8-AIX32-NEXT:    blr
694;
695; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8:
696; P7-AIX32:       # %bb.0: # %entry
697; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
698; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
699; P7-AIX32-NEXT:    blr
700  entry:
701    %0 = load <16 x i8>, <16 x i8>* %s, align 16
702    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
703    ret <16 x i8> %1
704}
705
706define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
707; P9-LABEL: adjusted_lxvwsx_v16i8_2:
708; P9:       # %bb.0: # %entry
709; P9-NEXT:    addi r3, r3, 8
710; P9-NEXT:    lxvwsx v2, 0, r3
711; P9-NEXT:    blr
712;
713; P8-LABEL: adjusted_lxvwsx_v16i8_2:
714; P8:       # %bb.0: # %entry
715; P8-NEXT:    lvx v2, 0, r3
716; P8-NEXT:    xxspltw v2, v2, 1
717; P8-NEXT:    blr
718;
719; P7-LABEL: adjusted_lxvwsx_v16i8_2:
720; P7:       # %bb.0: # %entry
721; P7-NEXT:    lxvw4x vs0, 0, r3
722; P7-NEXT:    xxspltw v2, vs0, 2
723; P7-NEXT:    blr
724;
725; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
726; P9-AIX32:       # %bb.0: # %entry
727; P9-AIX32-NEXT:    addi r3, r3, 8
728; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
729; P9-AIX32-NEXT:    blr
730;
731; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
732; P8-AIX32:       # %bb.0: # %entry
733; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
734; P8-AIX32-NEXT:    xxspltw v2, vs0, 2
735; P8-AIX32-NEXT:    blr
736;
737; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
738; P7-AIX32:       # %bb.0: # %entry
739; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
740; P7-AIX32-NEXT:    xxspltw v2, vs0, 2
741; P7-AIX32-NEXT:    blr
742  entry:
743    %0 = load <16 x i8>, <16 x i8>* %s, align 16
744    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
745    ret <16 x i8> %1
746}
747
748define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
749; P9-LABEL: adjusted_lxvwsx_v16i8_3:
750; P9:       # %bb.0: # %entry
751; P9-NEXT:    addi r3, r3, 12
752; P9-NEXT:    lxvwsx v2, 0, r3
753; P9-NEXT:    blr
754;
755; P8-LABEL: adjusted_lxvwsx_v16i8_3:
756; P8:       # %bb.0: # %entry
757; P8-NEXT:    lvx v2, 0, r3
758; P8-NEXT:    xxspltw v2, v2, 0
759; P8-NEXT:    blr
760;
761; P7-LABEL: adjusted_lxvwsx_v16i8_3:
762; P7:       # %bb.0: # %entry
763; P7-NEXT:    lxvw4x vs0, 0, r3
764; P7-NEXT:    xxspltw v2, vs0, 3
765; P7-NEXT:    blr
766;
767; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
768; P9-AIX32:       # %bb.0: # %entry
769; P9-AIX32-NEXT:    addi r3, r3, 12
770; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
771; P9-AIX32-NEXT:    blr
772;
773; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
774; P8-AIX32:       # %bb.0: # %entry
775; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
776; P8-AIX32-NEXT:    xxspltw v2, vs0, 3
777; P8-AIX32-NEXT:    blr
778;
779; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
780; P7-AIX32:       # %bb.0: # %entry
781; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
782; P7-AIX32-NEXT:    xxspltw v2, vs0, 3
783; P7-AIX32-NEXT:    blr
784  entry:
785    %0 = load <16 x i8>, <16 x i8>* %s, align 16
786    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
787    ret <16 x i8> %1
788}
789
790define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
791; P9-LABEL: unadjusted_lxvdsx:
792; P9:       # %bb.0: # %entry
793; P9-NEXT:    lxvdsx v2, 0, r3
794; P9-NEXT:    blr
795;
796; P8-LABEL: unadjusted_lxvdsx:
797; P8:       # %bb.0: # %entry
798; P8-NEXT:    lxvdsx v2, 0, r3
799; P8-NEXT:    blr
800;
801; P7-LABEL: unadjusted_lxvdsx:
802; P7:       # %bb.0: # %entry
803; P7-NEXT:    lxvdsx v2, 0, r3
804; P7-NEXT:    blr
805;
806; P9-AIX32-LABEL: unadjusted_lxvdsx:
807; P9-AIX32:       # %bb.0: # %entry
808; P9-AIX32-NEXT:    lwz r4, 4(r3)
809; P9-AIX32-NEXT:    stw r4, -16(r1)
810; P9-AIX32-NEXT:    lwz r3, 0(r3)
811; P9-AIX32-NEXT:    lxv vs0, -16(r1)
812; P9-AIX32-NEXT:    stw r3, -32(r1)
813; P9-AIX32-NEXT:    lxv vs1, -32(r1)
814; P9-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
815; P9-AIX32-NEXT:    xxmrghd v2, vs0, vs0
816; P9-AIX32-NEXT:    blr
817;
818; P8-AIX32-LABEL: unadjusted_lxvdsx:
819; P8-AIX32:       # %bb.0: # %entry
820; P8-AIX32-NEXT:    lwz r4, 4(r3)
821; P8-AIX32-NEXT:    stw r4, -16(r1)
822; P8-AIX32-NEXT:    addi r4, r1, -32
823; P8-AIX32-NEXT:    lwz r3, 0(r3)
824; P8-AIX32-NEXT:    stw r3, -32(r1)
825; P8-AIX32-NEXT:    addi r3, r1, -16
826; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
827; P8-AIX32-NEXT:    lxvw4x vs1, 0, r4
828; P8-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
829; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
830; P8-AIX32-NEXT:    blr
831;
832; P7-AIX32-LABEL: unadjusted_lxvdsx:
833; P7-AIX32:       # %bb.0: # %entry
834; P7-AIX32-NEXT:    lwz r5, 4(r3)
835; P7-AIX32-NEXT:    addi r4, r1, -16
836; P7-AIX32-NEXT:    stw r5, -16(r1)
837; P7-AIX32-NEXT:    lwz r3, 0(r3)
838; P7-AIX32-NEXT:    stw r3, -32(r1)
839; P7-AIX32-NEXT:    addi r3, r1, -32
840; P7-AIX32-NEXT:    lxvw4x vs0, 0, r4
841; P7-AIX32-NEXT:    lxvw4x vs1, 0, r3
842; P7-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
843; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
844; P7-AIX32-NEXT:    blr
845  entry:
846    %0 = bitcast i64* %s to <8 x i8>*
847    %1 = load <8 x i8>, <8 x i8>* %0, align 8
848    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
849    ret <16 x i8> %2
850}
851
852define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
853; P9-LABEL: unadjusted_lxvdsx_v16i8:
854; P9:       # %bb.0: # %entry
855; P9-NEXT:    lxvdsx v2, 0, r3
856; P9-NEXT:    blr
857;
858; P8-LABEL: unadjusted_lxvdsx_v16i8:
859; P8:       # %bb.0: # %entry
860; P8-NEXT:    lxvdsx v2, 0, r3
861; P8-NEXT:    blr
862;
863; P7-LABEL: unadjusted_lxvdsx_v16i8:
864; P7:       # %bb.0: # %entry
865; P7-NEXT:    lxvdsx v2, 0, r3
866; P7-NEXT:    blr
867;
868; P9-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
869; P9-AIX32:       # %bb.0: # %entry
870; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
871; P9-AIX32-NEXT:    blr
872;
873; P8-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
874; P8-AIX32:       # %bb.0: # %entry
875; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
876; P8-AIX32-NEXT:    blr
877;
878; P7-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
879; P7-AIX32:       # %bb.0: # %entry
880; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
881; P7-AIX32-NEXT:    blr
882  entry:
883    %0 = load <16 x i8>, <16 x i8>* %s, align 16
884    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
885    ret <16 x i8> %1
886}
887
888define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
889; P9-LABEL: adjusted_lxvdsx_v16i8:
890; P9:       # %bb.0: # %entry
891; P9-NEXT:    addi r3, r3, 8
892; P9-NEXT:    lxvdsx v2, 0, r3
893; P9-NEXT:    blr
894;
895; P8-LABEL: adjusted_lxvdsx_v16i8:
896; P8:       # %bb.0: # %entry
897; P8-NEXT:    addi r3, r3, 8
898; P8-NEXT:    lxvdsx v2, 0, r3
899; P8-NEXT:    blr
900;
901; P7-LABEL: adjusted_lxvdsx_v16i8:
902; P7:       # %bb.0: # %entry
903; P7-NEXT:    addi r3, r3, 8
904; P7-NEXT:    lxvdsx v2, 0, r3
905; P7-NEXT:    blr
906;
907; P9-AIX32-LABEL: adjusted_lxvdsx_v16i8:
908; P9-AIX32:       # %bb.0: # %entry
909; P9-AIX32-NEXT:    addi r3, r3, 8
910; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
911; P9-AIX32-NEXT:    blr
912;
913; P8-AIX32-LABEL: adjusted_lxvdsx_v16i8:
914; P8-AIX32:       # %bb.0: # %entry
915; P8-AIX32-NEXT:    addi r3, r3, 8
916; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
917; P8-AIX32-NEXT:    blr
918;
919; P7-AIX32-LABEL: adjusted_lxvdsx_v16i8:
920; P7-AIX32:       # %bb.0: # %entry
921; P7-AIX32-NEXT:    addi r3, r3, 8
922; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
923; P7-AIX32-NEXT:    blr
924  entry:
925    %0 = load <16 x i8>, <16 x i8>* %s, align 16
926    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
927    ret <16 x i8> %1
928}
929
930define <8 x i16> @test_unaligned_v8i16(i16* %Ptr) {
931; P9-LABEL: test_unaligned_v8i16:
932; P9:       # %bb.0: # %entry
933; P9-NEXT:    addi r3, r3, 6
934; P9-NEXT:    lxsihzx v2, 0, r3
935; P9-NEXT:    vsplth v2, v2, 3
936; P9-NEXT:    blr
937;
938; P8-LABEL: test_unaligned_v8i16:
939; P8:       # %bb.0: # %entry
940; P8-NEXT:    lhz r3, 6(r3)
941; P8-NEXT:    mtvsrwz v2, r3
942; P8-NEXT:    vsplth v2, v2, 3
943; P8-NEXT:    blr
944;
945; P7-LABEL: test_unaligned_v8i16:
946; P7:       # %bb.0: # %entry
947; P7-NEXT:    li r4, 1
948; P7-NEXT:    addi r3, r3, 6
949; P7-NEXT:    lvx v2, 0, r3
950; P7-NEXT:    lvx v3, r4, r3
951; P7-NEXT:    lvsl v4, 0, r3
952; P7-NEXT:    vperm v2, v2, v3, v4
953; P7-NEXT:    vsplth v2, v2, 0
954; P7-NEXT:    blr
955;
956; P9-AIX32-LABEL: test_unaligned_v8i16:
957; P9-AIX32:       # %bb.0: # %entry
958; P9-AIX32-NEXT:    addi r3, r3, 6
959; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
960; P9-AIX32-NEXT:    vsplth v2, v2, 3
961; P9-AIX32-NEXT:    blr
962;
963; P8-AIX32-LABEL: test_unaligned_v8i16:
964; P8-AIX32:       # %bb.0: # %entry
965; P8-AIX32-NEXT:    lhz r3, 6(r3)
966; P8-AIX32-NEXT:    mtvsrwz v2, r3
967; P8-AIX32-NEXT:    vsplth v2, v2, 3
968; P8-AIX32-NEXT:    blr
969;
970; P7-AIX32-LABEL: test_unaligned_v8i16:
971; P7-AIX32:       # %bb.0: # %entry
972; P7-AIX32-NEXT:    li r4, 1
973; P7-AIX32-NEXT:    addi r3, r3, 6
974; P7-AIX32-NEXT:    lvx v2, 0, r3
975; P7-AIX32-NEXT:    lvx v3, r4, r3
976; P7-AIX32-NEXT:    lvsl v4, 0, r3
977; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
978; P7-AIX32-NEXT:    vsplth v2, v2, 0
979; P7-AIX32-NEXT:    blr
980entry:
981  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 3
982  %0 = load i16, i16* %add.ptr, align 16
983  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
984  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
985  ret <8 x i16> %splat.splat
986}
987
988define <16 x i8> @test_unaligned_v16i8(i8* %Ptr) {
989; P9-LABEL: test_unaligned_v16i8:
990; P9:       # %bb.0: # %entry
991; P9-NEXT:    addi r3, r3, 3
992; P9-NEXT:    lxsibzx v2, 0, r3
993; P9-NEXT:    vspltb v2, v2, 7
994; P9-NEXT:    blr
995;
996; P8-LABEL: test_unaligned_v16i8:
997; P8:       # %bb.0: # %entry
998; P8-NEXT:    lbz r3, 3(r3)
999; P8-NEXT:    mtvsrwz v2, r3
1000; P8-NEXT:    vspltb v2, v2, 7
1001; P8-NEXT:    blr
1002;
1003; P7-LABEL: test_unaligned_v16i8:
1004; P7:       # %bb.0: # %entry
1005; P7-NEXT:    addi r3, r3, 3
1006; P7-NEXT:    lvsl v2, 0, r3
1007; P7-NEXT:    lvx v3, 0, r3
1008; P7-NEXT:    vperm v2, v3, v3, v2
1009; P7-NEXT:    vspltb v2, v2, 0
1010; P7-NEXT:    blr
1011;
1012; P9-AIX32-LABEL: test_unaligned_v16i8:
1013; P9-AIX32:       # %bb.0: # %entry
1014; P9-AIX32-NEXT:    addi r3, r3, 3
1015; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1016; P9-AIX32-NEXT:    vspltb v2, v2, 7
1017; P9-AIX32-NEXT:    blr
1018;
1019; P8-AIX32-LABEL: test_unaligned_v16i8:
1020; P8-AIX32:       # %bb.0: # %entry
1021; P8-AIX32-NEXT:    lbz r3, 3(r3)
1022; P8-AIX32-NEXT:    mtvsrwz v2, r3
1023; P8-AIX32-NEXT:    vspltb v2, v2, 7
1024; P8-AIX32-NEXT:    blr
1025;
1026; P7-AIX32-LABEL: test_unaligned_v16i8:
1027; P7-AIX32:       # %bb.0: # %entry
1028; P7-AIX32-NEXT:    addi r3, r3, 3
1029; P7-AIX32-NEXT:    lvsl v2, 0, r3
1030; P7-AIX32-NEXT:    lvx v3, 0, r3
1031; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
1032; P7-AIX32-NEXT:    vspltb v2, v2, 0
1033; P7-AIX32-NEXT:    blr
1034entry:
1035  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 3
1036  %0 = load i8, i8* %add.ptr, align 16
1037  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1038  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1039  ret <16 x i8> %splat.splat
1040}
1041
1042define <8 x i16> @test_aligned_v8i16_1(i16* %Ptr) {
1043; P9-LABEL: test_aligned_v8i16_1:
1044; P9:       # %bb.0: # %entry
1045; P9-NEXT:    lxsihzx v2, 0, r3
1046; P9-NEXT:    vsplth v2, v2, 3
1047; P9-NEXT:    blr
1048;
1049; P8-LABEL: test_aligned_v8i16_1:
1050; P8:       # %bb.0: # %entry
1051; P8-NEXT:    lvx v2, 0, r3
1052; P8-NEXT:    vsplth v2, v2, 7
1053; P8-NEXT:    blr
1054;
1055; P7-LABEL: test_aligned_v8i16_1:
1056; P7:       # %bb.0: # %entry
1057; P7-NEXT:    lvx v2, 0, r3
1058; P7-NEXT:    vsplth v2, v2, 0
1059; P7-NEXT:    blr
1060;
1061; P9-AIX32-LABEL: test_aligned_v8i16_1:
1062; P9-AIX32:       # %bb.0: # %entry
1063; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1064; P9-AIX32-NEXT:    vsplth v2, v2, 3
1065; P9-AIX32-NEXT:    blr
1066;
1067; P8-AIX32-LABEL: test_aligned_v8i16_1:
1068; P8-AIX32:       # %bb.0: # %entry
1069; P8-AIX32-NEXT:    lvx v2, 0, r3
1070; P8-AIX32-NEXT:    vsplth v2, v2, 0
1071; P8-AIX32-NEXT:    blr
1072;
1073; P7-AIX32-LABEL: test_aligned_v8i16_1:
1074; P7-AIX32:       # %bb.0: # %entry
1075; P7-AIX32-NEXT:    lvx v2, 0, r3
1076; P7-AIX32-NEXT:    vsplth v2, v2, 0
1077; P7-AIX32-NEXT:    blr
1078entry:
1079  %0 = load i16, i16* %Ptr, align 16
1080  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1081  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1082  ret <8 x i16> %splat.splat
1083}
1084
1085define <8 x i16> @test_aligned_v8i16_2(i16* %Ptr) {
1086; P9-LABEL: test_aligned_v8i16_2:
1087; P9:       # %bb.0: # %entry
1088; P9-NEXT:    addi r3, r3, 32
1089; P9-NEXT:    lxsihzx v2, 0, r3
1090; P9-NEXT:    vsplth v2, v2, 3
1091; P9-NEXT:    blr
1092;
1093; P8-LABEL: test_aligned_v8i16_2:
1094; P8:       # %bb.0: # %entry
1095; P8-NEXT:    addi r3, r3, 32
1096; P8-NEXT:    lvx v2, 0, r3
1097; P8-NEXT:    vsplth v2, v2, 7
1098; P8-NEXT:    blr
1099;
1100; P7-LABEL: test_aligned_v8i16_2:
1101; P7:       # %bb.0: # %entry
1102; P7-NEXT:    addi r3, r3, 32
1103; P7-NEXT:    lvx v2, 0, r3
1104; P7-NEXT:    vsplth v2, v2, 0
1105; P7-NEXT:    blr
1106;
1107; P9-AIX32-LABEL: test_aligned_v8i16_2:
1108; P9-AIX32:       # %bb.0: # %entry
1109; P9-AIX32-NEXT:    addi r3, r3, 32
1110; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1111; P9-AIX32-NEXT:    vsplth v2, v2, 3
1112; P9-AIX32-NEXT:    blr
1113;
1114; P8-AIX32-LABEL: test_aligned_v8i16_2:
1115; P8-AIX32:       # %bb.0: # %entry
1116; P8-AIX32-NEXT:    addi r3, r3, 32
1117; P8-AIX32-NEXT:    lvx v2, 0, r3
1118; P8-AIX32-NEXT:    vsplth v2, v2, 0
1119; P8-AIX32-NEXT:    blr
1120;
1121; P7-AIX32-LABEL: test_aligned_v8i16_2:
1122; P7-AIX32:       # %bb.0: # %entry
1123; P7-AIX32-NEXT:    addi r3, r3, 32
1124; P7-AIX32-NEXT:    lvx v2, 0, r3
1125; P7-AIX32-NEXT:    vsplth v2, v2, 0
1126; P7-AIX32-NEXT:    blr
1127entry:
1128  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 16
1129  %0 = load i16, i16* %add.ptr, align 16
1130  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1131  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1132  ret <8 x i16> %splat.splat
1133}
1134
1135define <16 x i8> @test_aligned_v16i8_1(i8* %Ptr) {
1136; P9-LABEL: test_aligned_v16i8_1:
1137; P9:       # %bb.0: # %entry
1138; P9-NEXT:    lxsibzx v2, 0, r3
1139; P9-NEXT:    vspltb v2, v2, 7
1140; P9-NEXT:    blr
1141;
1142; P8-LABEL: test_aligned_v16i8_1:
1143; P8:       # %bb.0: # %entry
1144; P8-NEXT:    lvx v2, 0, r3
1145; P8-NEXT:    vspltb v2, v2, 15
1146; P8-NEXT:    blr
1147;
1148; P7-LABEL: test_aligned_v16i8_1:
1149; P7:       # %bb.0: # %entry
1150; P7-NEXT:    lvx v2, 0, r3
1151; P7-NEXT:    vspltb v2, v2, 0
1152; P7-NEXT:    blr
1153;
1154; P9-AIX32-LABEL: test_aligned_v16i8_1:
1155; P9-AIX32:       # %bb.0: # %entry
1156; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1157; P9-AIX32-NEXT:    vspltb v2, v2, 7
1158; P9-AIX32-NEXT:    blr
1159;
1160; P8-AIX32-LABEL: test_aligned_v16i8_1:
1161; P8-AIX32:       # %bb.0: # %entry
1162; P8-AIX32-NEXT:    lvx v2, 0, r3
1163; P8-AIX32-NEXT:    vspltb v2, v2, 0
1164; P8-AIX32-NEXT:    blr
1165;
1166; P7-AIX32-LABEL: test_aligned_v16i8_1:
1167; P7-AIX32:       # %bb.0: # %entry
1168; P7-AIX32-NEXT:    lvx v2, 0, r3
1169; P7-AIX32-NEXT:    vspltb v2, v2, 0
1170; P7-AIX32-NEXT:    blr
1171entry:
1172  %0 = load i8, i8* %Ptr, align 16
1173  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1174  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1175  ret <16 x i8> %splat.splat
1176}
1177
1178define <16 x i8> @test_aligned_v16i8_2(i8* %Ptr) {
1179; P9-LABEL: test_aligned_v16i8_2:
1180; P9:       # %bb.0: # %entry
1181; P9-NEXT:    addi r3, r3, 16
1182; P9-NEXT:    lxsibzx v2, 0, r3
1183; P9-NEXT:    vspltb v2, v2, 7
1184; P9-NEXT:    blr
1185;
1186; P8-LABEL: test_aligned_v16i8_2:
1187; P8:       # %bb.0: # %entry
1188; P8-NEXT:    addi r3, r3, 16
1189; P8-NEXT:    lvx v2, 0, r3
1190; P8-NEXT:    vspltb v2, v2, 15
1191; P8-NEXT:    blr
1192;
1193; P7-LABEL: test_aligned_v16i8_2:
1194; P7:       # %bb.0: # %entry
1195; P7-NEXT:    addi r3, r3, 16
1196; P7-NEXT:    lvx v2, 0, r3
1197; P7-NEXT:    vspltb v2, v2, 0
1198; P7-NEXT:    blr
1199;
1200; P9-AIX32-LABEL: test_aligned_v16i8_2:
1201; P9-AIX32:       # %bb.0: # %entry
1202; P9-AIX32-NEXT:    addi r3, r3, 16
1203; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1204; P9-AIX32-NEXT:    vspltb v2, v2, 7
1205; P9-AIX32-NEXT:    blr
1206;
1207; P8-AIX32-LABEL: test_aligned_v16i8_2:
1208; P8-AIX32:       # %bb.0: # %entry
1209; P8-AIX32-NEXT:    addi r3, r3, 16
1210; P8-AIX32-NEXT:    lvx v2, 0, r3
1211; P8-AIX32-NEXT:    vspltb v2, v2, 0
1212; P8-AIX32-NEXT:    blr
1213;
1214; P7-AIX32-LABEL: test_aligned_v16i8_2:
1215; P7-AIX32:       # %bb.0: # %entry
1216; P7-AIX32-NEXT:    addi r3, r3, 16
1217; P7-AIX32-NEXT:    lvx v2, 0, r3
1218; P7-AIX32-NEXT:    vspltb v2, v2, 0
1219; P7-AIX32-NEXT:    blr
1220entry:
1221  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 16
1222  %0 = load i8, i8* %add.ptr, align 16
1223  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1224  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1225  ret <16 x i8> %splat.splat
1226}
1227
1228; The following test case should not produce a load and splat node,
1229; as we cannot handle extending loads (from f32 to f64), and this test
1230; shows that there are multiple uses of the extending load (other than
1231; a build vector node). `lxvdsx` should not be produced in this case.
1232define <2 x double> @test_v2f64_multiple_use(float* nocapture readonly %a, double* nocapture %b, double* nocapture %c) {
1233; P9-LABEL: test_v2f64_multiple_use:
1234; P9:       # %bb.0: # %entry
1235; P9-NEXT:    lfs f0, 0(r3)
1236; P9-NEXT:    xxspltd v2, vs0, 0
1237; P9-NEXT:    lfd f1, 0(r4)
1238; P9-NEXT:    xsadddp f1, f1, f0
1239; P9-NEXT:    stfd f1, 0(r4)
1240; P9-NEXT:    lfd f1, 0(r5)
1241; P9-NEXT:    xsadddp f1, f1, f0
1242; P9-NEXT:    stfd f1, 0(r5)
1243; P9-NEXT:    blr
1244;
1245; P8-LABEL: test_v2f64_multiple_use:
1246; P8:       # %bb.0: # %entry
1247; P8-NEXT:    lfs f0, 0(r3)
1248; P8-NEXT:    lfd f1, 0(r4)
1249; P8-NEXT:    xsadddp f1, f1, f0
1250; P8-NEXT:    xxspltd v2, vs0, 0
1251; P8-NEXT:    stfd f1, 0(r4)
1252; P8-NEXT:    lfd f1, 0(r5)
1253; P8-NEXT:    xsadddp f1, f1, f0
1254; P8-NEXT:    stfd f1, 0(r5)
1255; P8-NEXT:    blr
1256;
1257; P7-LABEL: test_v2f64_multiple_use:
1258; P7:       # %bb.0: # %entry
1259; P7-NEXT:    lfs f0, 0(r3)
1260; P7-NEXT:    lfd f1, 0(r4)
1261; P7-NEXT:    xsadddp f1, f1, f0
1262; P7-NEXT:    xxspltd v2, vs0, 0
1263; P7-NEXT:    stfd f1, 0(r4)
1264; P7-NEXT:    lfd f1, 0(r5)
1265; P7-NEXT:    xsadddp f1, f1, f0
1266; P7-NEXT:    stfd f1, 0(r5)
1267; P7-NEXT:    blr
1268;
1269; P9-AIX32-LABEL: test_v2f64_multiple_use:
1270; P9-AIX32:       # %bb.0: # %entry
1271; P9-AIX32-NEXT:    lfs f0, 0(r3)
1272; P9-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1273; P9-AIX32-NEXT:    lfd f1, 0(r4)
1274; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1275; P9-AIX32-NEXT:    stfd f1, 0(r4)
1276; P9-AIX32-NEXT:    lfd f1, 0(r5)
1277; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1278; P9-AIX32-NEXT:    stfd f1, 0(r5)
1279; P9-AIX32-NEXT:    blr
1280;
1281; P8-AIX32-LABEL: test_v2f64_multiple_use:
1282; P8-AIX32:       # %bb.0: # %entry
1283; P8-AIX32-NEXT:    lfs f0, 0(r3)
1284; P8-AIX32-NEXT:    lfd f1, 0(r4)
1285; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1286; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1287; P8-AIX32-NEXT:    stfd f1, 0(r4)
1288; P8-AIX32-NEXT:    lfd f1, 0(r5)
1289; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1290; P8-AIX32-NEXT:    stfd f1, 0(r5)
1291; P8-AIX32-NEXT:    blr
1292;
1293; P7-AIX32-LABEL: test_v2f64_multiple_use:
1294; P7-AIX32:       # %bb.0: # %entry
1295; P7-AIX32-NEXT:    lfs f0, 0(r3)
1296; P7-AIX32-NEXT:    lfd f1, 0(r4)
1297; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1298; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1299; P7-AIX32-NEXT:    stfd f1, 0(r4)
1300; P7-AIX32-NEXT:    lfd f1, 0(r5)
1301; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1302; P7-AIX32-NEXT:    stfd f1, 0(r5)
1303; P7-AIX32-NEXT:    blr
1304entry:
1305  %0 = load float, float* %a, align 4
1306  %conv = fpext float %0 to double
1307  %1 = load double, double* %b, align 8
1308  %add = fadd double %1, %conv
1309  store double %add, double* %b, align 8
1310  %2 = load double, double* %c, align 8
1311  %add2 = fadd double %2, %conv
1312  store double %add2, double* %c, align 8
1313  %vecinit = insertelement <2 x double> undef, double %conv, i64 0
1314  %vecinit5 = shufflevector <2 x double> %vecinit, <2 x double> poison, <2 x i32> zeroinitializer
1315  ret <2 x double> %vecinit5
1316}
1317