1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
4; RUN:   -check-prefix=P9
5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
7; RUN:   -check-prefix=P8
8; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
10; RUN:   -check-prefix=P7
11; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
13; RUN:   -check-prefix=P9-AIX32
14; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
15; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
16; RUN:   -check-prefix=P8-AIX32
17; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
18; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
19; RUN:   -check-prefix=P7-AIX32
20
21; v2f64
22define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
23; P9-LABEL: test:
24; P9:       # %bb.0: # %entry
25; P9-NEXT:    addi r4, r4, 24
26; P9-NEXT:    lxvdsx vs0, 0, r4
27; P9-NEXT:    stxv vs0, 0(r3)
28; P9-NEXT:    blr
29;
30; P8-LABEL: test:
31; P8:       # %bb.0: # %entry
32; P8-NEXT:    addi r4, r4, 24
33; P8-NEXT:    lxvdsx vs0, 0, r4
34; P8-NEXT:    stxvd2x vs0, 0, r3
35; P8-NEXT:    blr
36;
37; P7-LABEL: test:
38; P7:       # %bb.0: # %entry
39; P7-NEXT:    addi r4, r4, 24
40; P7-NEXT:    lxvdsx vs0, 0, r4
41; P7-NEXT:    stxvd2x vs0, 0, r3
42; P7-NEXT:    blr
43;
44; P9-AIX32-LABEL: test:
45; P9-AIX32:       # %bb.0: # %entry
46; P9-AIX32-NEXT:    addi r4, r4, 24
47; P9-AIX32-NEXT:    lxvdsx vs0, 0, r4
48; P9-AIX32-NEXT:    stxv vs0, 0(r3)
49; P9-AIX32-NEXT:    blr
50;
51; P8-AIX32-LABEL: test:
52; P8-AIX32:       # %bb.0: # %entry
53; P8-AIX32-NEXT:    addi r4, r4, 24
54; P8-AIX32-NEXT:    lxvdsx vs0, 0, r4
55; P8-AIX32-NEXT:    stxvd2x vs0, 0, r3
56; P8-AIX32-NEXT:    blr
57;
58; P7-AIX32-LABEL: test:
59; P7-AIX32:       # %bb.0: # %entry
60; P7-AIX32-NEXT:    addi r4, r4, 24
61; P7-AIX32-NEXT:    lxvdsx vs0, 0, r4
62; P7-AIX32-NEXT:    stxvd2x vs0, 0, r3
63; P7-AIX32-NEXT:    blr
64entry:
65  %arrayidx = getelementptr inbounds double, double* %a, i64 3
66  %0 = load double, double* %arrayidx, align 8
67  %splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
68  %splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> zeroinitializer
69  store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
70  ret void
71}
72
73; v4f32
74define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonly %a) local_unnamed_addr {
75; P9-LABEL: test2:
76; P9:       # %bb.0: # %entry
77; P9-NEXT:    addi r4, r4, 12
78; P9-NEXT:    lxvwsx vs0, 0, r4
79; P9-NEXT:    stxv vs0, 0(r3)
80; P9-NEXT:    blr
81;
82; P8-LABEL: test2:
83; P8:       # %bb.0: # %entry
84; P8-NEXT:    addi r4, r4, 12
85; P8-NEXT:    lfiwzx f0, 0, r4
86; P8-NEXT:    xxspltw v2, vs0, 1
87; P8-NEXT:    stvx v2, 0, r3
88; P8-NEXT:    blr
89;
90; P7-LABEL: test2:
91; P7:       # %bb.0: # %entry
92; P7-NEXT:    addi r4, r4, 12
93; P7-NEXT:    lfiwzx f0, 0, r4
94; P7-NEXT:    xxspltw vs0, vs0, 1
95; P7-NEXT:    stxvw4x vs0, 0, r3
96; P7-NEXT:    blr
97;
98; P9-AIX32-LABEL: test2:
99; P9-AIX32:       # %bb.0: # %entry
100; P9-AIX32-NEXT:    addi r4, r4, 12
101; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
102; P9-AIX32-NEXT:    stxv vs0, 0(r3)
103; P9-AIX32-NEXT:    blr
104;
105; P8-AIX32-LABEL: test2:
106; P8-AIX32:       # %bb.0: # %entry
107; P8-AIX32-NEXT:    addi r4, r4, 12
108; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
109; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
110; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
111; P8-AIX32-NEXT:    blr
112;
113; P7-AIX32-LABEL: test2:
114; P7-AIX32:       # %bb.0: # %entry
115; P7-AIX32-NEXT:    addi r4, r4, 12
116; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
117; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
118; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
119; P7-AIX32-NEXT:    blr
120entry:
121  %arrayidx = getelementptr inbounds float, float* %a, i64 3
122  %0 = load float, float* %arrayidx, align 4
123  %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
124  %splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
125  store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
126  ret void
127}
128
129; v4i32
130define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
131; P9-LABEL: test3:
132; P9:       # %bb.0: # %entry
133; P9-NEXT:    addi r4, r4, 12
134; P9-NEXT:    lxvwsx vs0, 0, r4
135; P9-NEXT:    stxv vs0, 0(r3)
136; P9-NEXT:    blr
137;
138; P8-LABEL: test3:
139; P8:       # %bb.0: # %entry
140; P8-NEXT:    addi r4, r4, 12
141; P8-NEXT:    lfiwzx f0, 0, r4
142; P8-NEXT:    xxspltw v2, vs0, 1
143; P8-NEXT:    stvx v2, 0, r3
144; P8-NEXT:    blr
145;
146; P7-LABEL: test3:
147; P7:       # %bb.0: # %entry
148; P7-NEXT:    addi r4, r4, 12
149; P7-NEXT:    lfiwzx f0, 0, r4
150; P7-NEXT:    xxspltw vs0, vs0, 1
151; P7-NEXT:    stxvw4x vs0, 0, r3
152; P7-NEXT:    blr
153;
154; P9-AIX32-LABEL: test3:
155; P9-AIX32:       # %bb.0: # %entry
156; P9-AIX32-NEXT:    addi r4, r4, 12
157; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
158; P9-AIX32-NEXT:    stxv vs0, 0(r3)
159; P9-AIX32-NEXT:    blr
160;
161; P8-AIX32-LABEL: test3:
162; P8-AIX32:       # %bb.0: # %entry
163; P8-AIX32-NEXT:    addi r4, r4, 12
164; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
165; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
166; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
167; P8-AIX32-NEXT:    blr
168;
169; P7-AIX32-LABEL: test3:
170; P7-AIX32:       # %bb.0: # %entry
171; P7-AIX32-NEXT:    addi r4, r4, 12
172; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
173; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
174; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
175; P7-AIX32-NEXT:    blr
176entry:
177  %arrayidx = getelementptr inbounds i32, i32* %a, i64 3
178  %0 = load i32, i32* %arrayidx, align 4
179  %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
180  %splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
181  store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
182  ret void
183}
184
185
186; v2i64
187define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a) local_unnamed_addr {
188; P9-LABEL: test4:
189; P9:       # %bb.0: # %entry
190; P9-NEXT:    addi r4, r4, 24
191; P9-NEXT:    lxvdsx vs0, 0, r4
192; P9-NEXT:    stxv vs0, 0(r3)
193; P9-NEXT:    blr
194;
195; P8-LABEL: test4:
196; P8:       # %bb.0: # %entry
197; P8-NEXT:    addi r4, r4, 24
198; P8-NEXT:    lxvdsx vs0, 0, r4
199; P8-NEXT:    stxvd2x vs0, 0, r3
200; P8-NEXT:    blr
201;
202; P7-LABEL: test4:
203; P7:       # %bb.0: # %entry
204; P7-NEXT:    addi r4, r4, 24
205; P7-NEXT:    lxvdsx vs0, 0, r4
206; P7-NEXT:    stxvd2x vs0, 0, r3
207; P7-NEXT:    blr
208;
209; P9-AIX32-LABEL: test4:
210; P9-AIX32:       # %bb.0: # %entry
211; P9-AIX32-NEXT:    lwz r5, 24(r4)
212; P9-AIX32-NEXT:    lwz r4, 28(r4)
213; P9-AIX32-NEXT:    stw r4, -16(r1)
214; P9-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
215; P9-AIX32-NEXT:    stw r5, -32(r1)
216; P9-AIX32-NEXT:    lxv v3, -16(r1)
217; P9-AIX32-NEXT:    lxv v4, -32(r1)
218; P9-AIX32-NEXT:    lxv v2, 0(r4)
219; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
220; P9-AIX32-NEXT:    stxv v2, 0(r3)
221; P9-AIX32-NEXT:    blr
222;
223; P8-AIX32-LABEL: test4:
224; P8-AIX32:       # %bb.0: # %entry
225; P8-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
226; P8-AIX32-NEXT:    lwz r6, 28(r4)
227; P8-AIX32-NEXT:    lwz r4, 24(r4)
228; P8-AIX32-NEXT:    stw r6, -16(r1)
229; P8-AIX32-NEXT:    stw r4, -32(r1)
230; P8-AIX32-NEXT:    addi r4, r1, -16
231; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
232; P8-AIX32-NEXT:    addi r5, r1, -32
233; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
234; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
235; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
236; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
237; P8-AIX32-NEXT:    blr
238;
239; P7-AIX32-LABEL: test4:
240; P7-AIX32:       # %bb.0: # %entry
241; P7-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
242; P7-AIX32-NEXT:    lwz r6, 24(r4)
243; P7-AIX32-NEXT:    lwz r4, 28(r4)
244; P7-AIX32-NEXT:    stw r4, -16(r1)
245; P7-AIX32-NEXT:    stw r6, -32(r1)
246; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
247; P7-AIX32-NEXT:    addi r4, r1, -16
248; P7-AIX32-NEXT:    addi r5, r1, -32
249; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
250; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
251; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
252; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
253; P7-AIX32-NEXT:    blr
254entry:
255  %arrayidx = getelementptr inbounds i64, i64* %a, i64 3
256  %0 = load i64, i64* %arrayidx, align 8
257  %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
258  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
259  store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
260  ret void
261}
262
263; sext v2i64
264define void @test5(<2 x i64>* %a, i32* %in) {
265; P9-LABEL: test5:
266; P9:       # %bb.0: # %entry
267; P9-NEXT:    lfiwax f0, 0, r4
268; P9-NEXT:    xxspltd vs0, f0, 0
269; P9-NEXT:    stxv vs0, 0(r3)
270; P9-NEXT:    blr
271;
272; P8-LABEL: test5:
273; P8:       # %bb.0: # %entry
274; P8-NEXT:    lfiwax f0, 0, r4
275; P8-NEXT:    xxspltd vs0, f0, 0
276; P8-NEXT:    stxvd2x vs0, 0, r3
277; P8-NEXT:    blr
278;
279; P7-LABEL: test5:
280; P7:       # %bb.0: # %entry
281; P7-NEXT:    lfiwax f0, 0, r4
282; P7-NEXT:    xxspltd vs0, f0, 0
283; P7-NEXT:    stxvd2x vs0, 0, r3
284; P7-NEXT:    blr
285;
286; P9-AIX32-LABEL: test5:
287; P9-AIX32:       # %bb.0: # %entry
288; P9-AIX32-NEXT:    lwz r4, 0(r4)
289; P9-AIX32-NEXT:    srawi r5, r4, 31
290; P9-AIX32-NEXT:    stw r4, -16(r1)
291; P9-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
292; P9-AIX32-NEXT:    lxv v3, -16(r1)
293; P9-AIX32-NEXT:    stw r5, -32(r1)
294; P9-AIX32-NEXT:    lxv v4, -32(r1)
295; P9-AIX32-NEXT:    lxv v2, 0(r4)
296; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
297; P9-AIX32-NEXT:    stxv v2, 0(r3)
298; P9-AIX32-NEXT:    blr
299;
300; P8-AIX32-LABEL: test5:
301; P8-AIX32:       # %bb.0: # %entry
302; P8-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
303; P8-AIX32-NEXT:    lwz r4, 0(r4)
304; P8-AIX32-NEXT:    stw r4, -16(r1)
305; P8-AIX32-NEXT:    srawi r4, r4, 31
306; P8-AIX32-NEXT:    stw r4, -32(r1)
307; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
308; P8-AIX32-NEXT:    addi r4, r1, -16
309; P8-AIX32-NEXT:    addi r5, r1, -32
310; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
311; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
312; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
313; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
314; P8-AIX32-NEXT:    blr
315;
316; P7-AIX32-LABEL: test5:
317; P7-AIX32:       # %bb.0: # %entry
318; P7-AIX32-NEXT:    lwz r4, 0(r4)
319; P7-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
320; P7-AIX32-NEXT:    srawi r6, r4, 31
321; P7-AIX32-NEXT:    stw r4, -16(r1)
322; P7-AIX32-NEXT:    addi r4, r1, -16
323; P7-AIX32-NEXT:    stw r6, -32(r1)
324; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
325; P7-AIX32-NEXT:    addi r5, r1, -32
326; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
327; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
328; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
329; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
330; P7-AIX32-NEXT:    blr
331entry:
332  %0 = load i32, i32* %in, align 4
333  %conv = sext i32 %0 to i64
334  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
335  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
336  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
337  ret void
338}
339
340; zext v2i64
341define void @test6(<2 x i64>* %a, i32* %in) {
342; P9-LABEL: test6:
343; P9:       # %bb.0: # %entry
344; P9-NEXT:    lfiwzx f0, 0, r4
345; P9-NEXT:    xxspltd vs0, f0, 0
346; P9-NEXT:    stxv vs0, 0(r3)
347; P9-NEXT:    blr
348;
349; P8-LABEL: test6:
350; P8:       # %bb.0: # %entry
351; P8-NEXT:    lfiwzx f0, 0, r4
352; P8-NEXT:    xxspltd vs0, f0, 0
353; P8-NEXT:    stxvd2x vs0, 0, r3
354; P8-NEXT:    blr
355;
356; P7-LABEL: test6:
357; P7:       # %bb.0: # %entry
358; P7-NEXT:    lfiwzx f0, 0, r4
359; P7-NEXT:    xxspltd vs0, f0, 0
360; P7-NEXT:    stxvd2x vs0, 0, r3
361; P7-NEXT:    blr
362;
363; P9-AIX32-LABEL: test6:
364; P9-AIX32:       # %bb.0: # %entry
365; P9-AIX32-NEXT:    lwz r4, 0(r4)
366; P9-AIX32-NEXT:    li r5, 0
367; P9-AIX32-NEXT:    stw r5, -32(r1)
368; P9-AIX32-NEXT:    lxv v3, -32(r1)
369; P9-AIX32-NEXT:    stw r4, -16(r1)
370; P9-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
371; P9-AIX32-NEXT:    lxv v4, -16(r1)
372; P9-AIX32-NEXT:    lxv v2, 0(r4)
373; P9-AIX32-NEXT:    vperm v2, v3, v4, v2
374; P9-AIX32-NEXT:    stxv v2, 0(r3)
375; P9-AIX32-NEXT:    blr
376;
377; P8-AIX32-LABEL: test6:
378; P8-AIX32:       # %bb.0: # %entry
379; P8-AIX32-NEXT:    lwz r6, L..C2(r2) # %const.0
380; P8-AIX32-NEXT:    lwz r4, 0(r4)
381; P8-AIX32-NEXT:    li r5, 0
382; P8-AIX32-NEXT:    stw r5, -32(r1)
383; P8-AIX32-NEXT:    addi r5, r1, -16
384; P8-AIX32-NEXT:    stw r4, -16(r1)
385; P8-AIX32-NEXT:    addi r4, r1, -32
386; P8-AIX32-NEXT:    lxvw4x v2, 0, r6
387; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
388; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
389; P8-AIX32-NEXT:    vperm v2, v3, v4, v2
390; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
391; P8-AIX32-NEXT:    blr
392;
393; P7-AIX32-LABEL: test6:
394; P7-AIX32:       # %bb.0: # %entry
395; P7-AIX32-NEXT:    lwz r5, L..C2(r2) # %const.0
396; P7-AIX32-NEXT:    lwz r4, 0(r4)
397; P7-AIX32-NEXT:    li r6, 0
398; P7-AIX32-NEXT:    stw r6, -32(r1)
399; P7-AIX32-NEXT:    stw r4, -16(r1)
400; P7-AIX32-NEXT:    addi r4, r1, -32
401; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
402; P7-AIX32-NEXT:    addi r5, r1, -16
403; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
404; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
405; P7-AIX32-NEXT:    vperm v2, v3, v4, v2
406; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
407; P7-AIX32-NEXT:    blr
408entry:
409  %0 = load i32, i32* %in, align 4
410  %conv = zext i32 %0 to i64
411  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
412  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
413  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
414  ret void
415}
416
417; v8i16
418define void @test7(<8 x i16>* %a, i16* %in) {
419; P9-LABEL: test7:
420; P9:       # %bb.0: # %entry
421; P9-NEXT:    lxsihzx v2, 0, r4
422; P9-NEXT:    vsplth v2, v2, 3
423; P9-NEXT:    stxv v2, 0(r3)
424; P9-NEXT:    blr
425;
426; P8-LABEL: test7:
427; P8:       # %bb.0: # %entry
428; P8-NEXT:    lhzx r4, 0, r4
429; P8-NEXT:    mtvsrwz v2, r4
430; P8-NEXT:    vsplth v2, v2, 3
431; P8-NEXT:    stvx v2, 0, r3
432; P8-NEXT:    blr
433;
434; P7-LABEL: test7:
435; P7:       # %bb.0: # %entry
436; P7-NEXT:    li r5, 1
437; P7-NEXT:    lvx v2, 0, r4
438; P7-NEXT:    lvsl v4, 0, r4
439; P7-NEXT:    lvx v3, r5, r4
440; P7-NEXT:    vperm v2, v2, v3, v4
441; P7-NEXT:    vsplth v2, v2, 0
442; P7-NEXT:    stxvw4x v2, 0, r3
443; P7-NEXT:    blr
444;
445; P9-AIX32-LABEL: test7:
446; P9-AIX32:       # %bb.0: # %entry
447; P9-AIX32-NEXT:    lxsihzx v2, 0, r4
448; P9-AIX32-NEXT:    vsplth v2, v2, 3
449; P9-AIX32-NEXT:    stxv v2, 0(r3)
450; P9-AIX32-NEXT:    blr
451;
452; P8-AIX32-LABEL: test7:
453; P8-AIX32:       # %bb.0: # %entry
454; P8-AIX32-NEXT:    lhzx r4, 0, r4
455; P8-AIX32-NEXT:    mtvsrwz v2, r4
456; P8-AIX32-NEXT:    vsplth v2, v2, 3
457; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
458; P8-AIX32-NEXT:    blr
459;
460; P7-AIX32-LABEL: test7:
461; P7-AIX32:       # %bb.0: # %entry
462; P7-AIX32-NEXT:    li r5, 1
463; P7-AIX32-NEXT:    lvx v2, 0, r4
464; P7-AIX32-NEXT:    lvsl v4, 0, r4
465; P7-AIX32-NEXT:    lvx v3, r5, r4
466; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
467; P7-AIX32-NEXT:    vsplth v2, v2, 0
468; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
469; P7-AIX32-NEXT:    blr
470entry:
471  %0 = load i16, i16* %in, align 2
472  %splat.splatinsert.i = insertelement <8 x i16> poison, i16 %0, i32 0
473  %splat.splat.i = shufflevector <8 x i16> %splat.splatinsert.i, <8 x i16> poison, <8 x i32> zeroinitializer
474  store <8 x i16> %splat.splat.i, <8 x i16>* %a, align 16
475  ret void
476}
477
478; v16i8
479define void @test8(<16 x i8>* %a, i8* %in) {
480; P9-LABEL: test8:
481; P9:       # %bb.0: # %entry
482; P9-NEXT:    lxsibzx v2, 0, r4
483; P9-NEXT:    vspltb v2, v2, 7
484; P9-NEXT:    stxv v2, 0(r3)
485; P9-NEXT:    blr
486;
487; P8-LABEL: test8:
488; P8:       # %bb.0: # %entry
489; P8-NEXT:    lbzx r4, 0, r4
490; P8-NEXT:    mtvsrwz v2, r4
491; P8-NEXT:    vspltb v2, v2, 7
492; P8-NEXT:    stvx v2, 0, r3
493; P8-NEXT:    blr
494;
495; P7-LABEL: test8:
496; P7:       # %bb.0: # %entry
497; P7-NEXT:    lvsl v2, 0, r4
498; P7-NEXT:    lvx v3, 0, r4
499; P7-NEXT:    vperm v2, v3, v3, v2
500; P7-NEXT:    vspltb v2, v2, 0
501; P7-NEXT:    stxvw4x v2, 0, r3
502; P7-NEXT:    blr
503;
504; P9-AIX32-LABEL: test8:
505; P9-AIX32:       # %bb.0: # %entry
506; P9-AIX32-NEXT:    lxsibzx v2, 0, r4
507; P9-AIX32-NEXT:    vspltb v2, v2, 7
508; P9-AIX32-NEXT:    stxv v2, 0(r3)
509; P9-AIX32-NEXT:    blr
510;
511; P8-AIX32-LABEL: test8:
512; P8-AIX32:       # %bb.0: # %entry
513; P8-AIX32-NEXT:    lbzx r4, 0, r4
514; P8-AIX32-NEXT:    mtvsrwz v2, r4
515; P8-AIX32-NEXT:    vspltb v2, v2, 7
516; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
517; P8-AIX32-NEXT:    blr
518;
519; P7-AIX32-LABEL: test8:
520; P7-AIX32:       # %bb.0: # %entry
521; P7-AIX32-NEXT:    lvsl v2, 0, r4
522; P7-AIX32-NEXT:    lvx v3, 0, r4
523; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
524; P7-AIX32-NEXT:    vspltb v2, v2, 0
525; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
526; P7-AIX32-NEXT:    blr
527entry:
528  %0 = load i8, i8* %in, align 1
529  %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %0, i32 0
530  %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer
531  store <16 x i8> %splat.splat.i, <16 x i8>* %a, align 16
532  ret void
533}
534
535define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
536; P9-LABEL: unadjusted_lxvwsx:
537; P9:       # %bb.0: # %entry
538; P9-NEXT:    lxvwsx v2, 0, r3
539; P9-NEXT:    blr
540;
541; P8-LABEL: unadjusted_lxvwsx:
542; P8:       # %bb.0: # %entry
543; P8-NEXT:    lfiwzx f0, 0, r3
544; P8-NEXT:    xxspltw v2, vs0, 1
545; P8-NEXT:    blr
546;
547; P7-LABEL: unadjusted_lxvwsx:
548; P7:       # %bb.0: # %entry
549; P7-NEXT:    lwz r3, 0(r3)
550; P7-NEXT:    addi r4, r1, -16
551; P7-NEXT:    stw r3, -16(r1)
552; P7-NEXT:    lxvw4x vs0, 0, r4
553; P7-NEXT:    xxspltw v2, vs0, 0
554; P7-NEXT:    blr
555;
556; P9-AIX32-LABEL: unadjusted_lxvwsx:
557; P9-AIX32:       # %bb.0: # %entry
558; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
559; P9-AIX32-NEXT:    blr
560;
561; P8-AIX32-LABEL: unadjusted_lxvwsx:
562; P8-AIX32:       # %bb.0: # %entry
563; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
564; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
565; P8-AIX32-NEXT:    blr
566;
567; P7-AIX32-LABEL: unadjusted_lxvwsx:
568; P7-AIX32:       # %bb.0: # %entry
569; P7-AIX32-NEXT:    lwz r3, 0(r3)
570; P7-AIX32-NEXT:    addi r4, r1, -16
571; P7-AIX32-NEXT:    stw r3, -16(r1)
572; P7-AIX32-NEXT:    lxvw4x vs0, 0, r4
573; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
574; P7-AIX32-NEXT:    blr
575  entry:
576    %0 = bitcast i32* %s to <4 x i8>*
577    %1 = load <4 x i8>, <4 x i8>* %0, align 4
578    %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
579    ret <16 x i8> %2
580}
581
582define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
583; P9-LABEL: adjusted_lxvwsx:
584; P9:       # %bb.0: # %entry
585; P9-NEXT:    addi r3, r3, 4
586; P9-NEXT:    lxvwsx v2, 0, r3
587; P9-NEXT:    blr
588;
589; P8-LABEL: adjusted_lxvwsx:
590; P8:       # %bb.0: # %entry
591; P8-NEXT:    lfdx f0, 0, r3
592; P8-NEXT:    xxspltw v2, vs0, 0
593; P8-NEXT:    blr
594;
595; P7-LABEL: adjusted_lxvwsx:
596; P7:       # %bb.0: # %entry
597; P7-NEXT:    ld r3, 0(r3)
598; P7-NEXT:    addi r4, r1, -16
599; P7-NEXT:    std r3, -16(r1)
600; P7-NEXT:    lxvw4x vs0, 0, r4
601; P7-NEXT:    xxspltw v2, vs0, 1
602; P7-NEXT:    blr
603;
604; P9-AIX32-LABEL: adjusted_lxvwsx:
605; P9-AIX32:       # %bb.0: # %entry
606; P9-AIX32-NEXT:    addi r3, r3, 4
607; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
608; P9-AIX32-NEXT:    blr
609;
610; P8-AIX32-LABEL: adjusted_lxvwsx:
611; P8-AIX32:       # %bb.0: # %entry
612; P8-AIX32-NEXT:    addi r3, r3, 4
613; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
614; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
615; P8-AIX32-NEXT:    blr
616;
617; P7-AIX32-LABEL: adjusted_lxvwsx:
618; P7-AIX32:       # %bb.0: # %entry
619; P7-AIX32-NEXT:    addi r3, r3, 4
620; P7-AIX32-NEXT:    lfiwzx f0, 0, r3
621; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
622; P7-AIX32-NEXT:    blr
623  entry:
624    %0 = bitcast i64* %s to <8 x i8>*
625    %1 = load <8 x i8>, <8 x i8>* %0, align 8
626    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
627    ret <16 x i8> %2
628}
629
630define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
631; P9-LABEL: unadjusted_lxvwsx_v16i8:
632; P9:       # %bb.0: # %entry
633; P9-NEXT:    lxvwsx v2, 0, r3
634; P9-NEXT:    blr
635;
636; P8-LABEL: unadjusted_lxvwsx_v16i8:
637; P8:       # %bb.0: # %entry
638; P8-NEXT:    lvx v2, 0, r3
639; P8-NEXT:    xxspltw v2, v2, 3
640; P8-NEXT:    blr
641;
642; P7-LABEL: unadjusted_lxvwsx_v16i8:
643; P7:       # %bb.0: # %entry
644; P7-NEXT:    lxvw4x vs0, 0, r3
645; P7-NEXT:    xxspltw v2, vs0, 0
646; P7-NEXT:    blr
647;
648; P9-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
649; P9-AIX32:       # %bb.0: # %entry
650; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
651; P9-AIX32-NEXT:    blr
652;
653; P8-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
654; P8-AIX32:       # %bb.0: # %entry
655; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
656; P8-AIX32-NEXT:    xxspltw v2, vs0, 0
657; P8-AIX32-NEXT:    blr
658;
659; P7-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
660; P7-AIX32:       # %bb.0: # %entry
661; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
662; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
663; P7-AIX32-NEXT:    blr
664  entry:
665    %0 = load <16 x i8>, <16 x i8>* %s, align 16
666    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
667    ret <16 x i8> %1
668}
669
670define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
671; P9-LABEL: adjusted_lxvwsx_v16i8:
672; P9:       # %bb.0: # %entry
673; P9-NEXT:    addi r3, r3, 4
674; P9-NEXT:    lxvwsx v2, 0, r3
675; P9-NEXT:    blr
676;
677; P8-LABEL: adjusted_lxvwsx_v16i8:
678; P8:       # %bb.0: # %entry
679; P8-NEXT:    lvx v2, 0, r3
680; P8-NEXT:    xxspltw v2, v2, 2
681; P8-NEXT:    blr
682;
683; P7-LABEL: adjusted_lxvwsx_v16i8:
684; P7:       # %bb.0: # %entry
685; P7-NEXT:    lxvw4x vs0, 0, r3
686; P7-NEXT:    xxspltw v2, vs0, 1
687; P7-NEXT:    blr
688;
689; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8:
690; P9-AIX32:       # %bb.0: # %entry
691; P9-AIX32-NEXT:    addi r3, r3, 4
692; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
693; P9-AIX32-NEXT:    blr
694;
695; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8:
696; P8-AIX32:       # %bb.0: # %entry
697; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
698; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
699; P8-AIX32-NEXT:    blr
700;
701; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8:
702; P7-AIX32:       # %bb.0: # %entry
703; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
704; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
705; P7-AIX32-NEXT:    blr
706  entry:
707    %0 = load <16 x i8>, <16 x i8>* %s, align 16
708    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
709    ret <16 x i8> %1
710}
711
712define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
713; P9-LABEL: adjusted_lxvwsx_v16i8_2:
714; P9:       # %bb.0: # %entry
715; P9-NEXT:    addi r3, r3, 8
716; P9-NEXT:    lxvwsx v2, 0, r3
717; P9-NEXT:    blr
718;
719; P8-LABEL: adjusted_lxvwsx_v16i8_2:
720; P8:       # %bb.0: # %entry
721; P8-NEXT:    lvx v2, 0, r3
722; P8-NEXT:    xxspltw v2, v2, 1
723; P8-NEXT:    blr
724;
725; P7-LABEL: adjusted_lxvwsx_v16i8_2:
726; P7:       # %bb.0: # %entry
727; P7-NEXT:    lxvw4x vs0, 0, r3
728; P7-NEXT:    xxspltw v2, vs0, 2
729; P7-NEXT:    blr
730;
731; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
732; P9-AIX32:       # %bb.0: # %entry
733; P9-AIX32-NEXT:    addi r3, r3, 8
734; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
735; P9-AIX32-NEXT:    blr
736;
737; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
738; P8-AIX32:       # %bb.0: # %entry
739; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
740; P8-AIX32-NEXT:    xxspltw v2, vs0, 2
741; P8-AIX32-NEXT:    blr
742;
743; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
744; P7-AIX32:       # %bb.0: # %entry
745; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
746; P7-AIX32-NEXT:    xxspltw v2, vs0, 2
747; P7-AIX32-NEXT:    blr
748  entry:
749    %0 = load <16 x i8>, <16 x i8>* %s, align 16
750    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
751    ret <16 x i8> %1
752}
753
754define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
755; P9-LABEL: adjusted_lxvwsx_v16i8_3:
756; P9:       # %bb.0: # %entry
757; P9-NEXT:    addi r3, r3, 12
758; P9-NEXT:    lxvwsx v2, 0, r3
759; P9-NEXT:    blr
760;
761; P8-LABEL: adjusted_lxvwsx_v16i8_3:
762; P8:       # %bb.0: # %entry
763; P8-NEXT:    lvx v2, 0, r3
764; P8-NEXT:    xxspltw v2, v2, 0
765; P8-NEXT:    blr
766;
767; P7-LABEL: adjusted_lxvwsx_v16i8_3:
768; P7:       # %bb.0: # %entry
769; P7-NEXT:    lxvw4x vs0, 0, r3
770; P7-NEXT:    xxspltw v2, vs0, 3
771; P7-NEXT:    blr
772;
773; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
774; P9-AIX32:       # %bb.0: # %entry
775; P9-AIX32-NEXT:    addi r3, r3, 12
776; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
777; P9-AIX32-NEXT:    blr
778;
779; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
780; P8-AIX32:       # %bb.0: # %entry
781; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
782; P8-AIX32-NEXT:    xxspltw v2, vs0, 3
783; P8-AIX32-NEXT:    blr
784;
785; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
786; P7-AIX32:       # %bb.0: # %entry
787; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
788; P7-AIX32-NEXT:    xxspltw v2, vs0, 3
789; P7-AIX32-NEXT:    blr
790  entry:
791    %0 = load <16 x i8>, <16 x i8>* %s, align 16
792    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
793    ret <16 x i8> %1
794}
795
796define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
797; P9-LABEL: unadjusted_lxvdsx:
798; P9:       # %bb.0: # %entry
799; P9-NEXT:    lxvdsx v2, 0, r3
800; P9-NEXT:    blr
801;
802; P8-LABEL: unadjusted_lxvdsx:
803; P8:       # %bb.0: # %entry
804; P8-NEXT:    lxvdsx v2, 0, r3
805; P8-NEXT:    blr
806;
807; P7-LABEL: unadjusted_lxvdsx:
808; P7:       # %bb.0: # %entry
809; P7-NEXT:    lxvdsx v2, 0, r3
810; P7-NEXT:    blr
811;
812; P9-AIX32-LABEL: unadjusted_lxvdsx:
813; P9-AIX32:       # %bb.0: # %entry
814; P9-AIX32-NEXT:    lwz r4, 0(r3)
815; P9-AIX32-NEXT:    stw r4, -16(r1)
816; P9-AIX32-NEXT:    lwz r3, 4(r3)
817; P9-AIX32-NEXT:    lxv vs1, -16(r1)
818; P9-AIX32-NEXT:    mtfprwz f0, r3
819; P9-AIX32-NEXT:    xxinsertw vs1, vs0, 4
820; P9-AIX32-NEXT:    xxmrghd v2, vs1, vs1
821; P9-AIX32-NEXT:    blr
822;
823; P8-AIX32-LABEL: unadjusted_lxvdsx:
824; P8-AIX32:       # %bb.0: # %entry
825; P8-AIX32-NEXT:    lwz r5, 4(r3)
826; P8-AIX32-NEXT:    lwz r4, L..C3(r2) # %const.0
827; P8-AIX32-NEXT:    stw r5, -32(r1)
828; P8-AIX32-NEXT:    lwz r3, 0(r3)
829; P8-AIX32-NEXT:    lxvw4x v2, 0, r4
830; P8-AIX32-NEXT:    addi r4, r1, -16
831; P8-AIX32-NEXT:    stw r3, -16(r1)
832; P8-AIX32-NEXT:    addi r3, r1, -32
833; P8-AIX32-NEXT:    lxvw4x v3, 0, r3
834; P8-AIX32-NEXT:    lxvw4x v4, 0, r4
835; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
836; P8-AIX32-NEXT:    xxmrghd v2, v2, v2
837; P8-AIX32-NEXT:    blr
838;
839; P7-AIX32-LABEL: unadjusted_lxvdsx:
840; P7-AIX32:       # %bb.0: # %entry
841; P7-AIX32-NEXT:    lwz r5, 4(r3)
842; P7-AIX32-NEXT:    lwz r4, L..C3(r2) # %const.0
843; P7-AIX32-NEXT:    stw r5, -32(r1)
844; P7-AIX32-NEXT:    lwz r3, 0(r3)
845; P7-AIX32-NEXT:    lxvw4x v2, 0, r4
846; P7-AIX32-NEXT:    addi r4, r1, -16
847; P7-AIX32-NEXT:    stw r3, -16(r1)
848; P7-AIX32-NEXT:    addi r3, r1, -32
849; P7-AIX32-NEXT:    lxvw4x v3, 0, r3
850; P7-AIX32-NEXT:    lxvw4x v4, 0, r4
851; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
852; P7-AIX32-NEXT:    xxmrghd v2, v2, v2
853; P7-AIX32-NEXT:    blr
854  entry:
855    %0 = bitcast i64* %s to <8 x i8>*
856    %1 = load <8 x i8>, <8 x i8>* %0, align 8
857    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
858    ret <16 x i8> %2
859}
860
861define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
862; P9-LABEL: unadjusted_lxvdsx_v16i8:
863; P9:       # %bb.0: # %entry
864; P9-NEXT:    lxvdsx v2, 0, r3
865; P9-NEXT:    blr
866;
867; P8-LABEL: unadjusted_lxvdsx_v16i8:
868; P8:       # %bb.0: # %entry
869; P8-NEXT:    lxvdsx v2, 0, r3
870; P8-NEXT:    blr
871;
872; P7-LABEL: unadjusted_lxvdsx_v16i8:
873; P7:       # %bb.0: # %entry
874; P7-NEXT:    lxvdsx v2, 0, r3
875; P7-NEXT:    blr
876;
877; P9-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
878; P9-AIX32:       # %bb.0: # %entry
879; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
880; P9-AIX32-NEXT:    blr
881;
882; P8-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
883; P8-AIX32:       # %bb.0: # %entry
884; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
885; P8-AIX32-NEXT:    blr
886;
887; P7-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
888; P7-AIX32:       # %bb.0: # %entry
889; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
890; P7-AIX32-NEXT:    blr
891  entry:
892    %0 = load <16 x i8>, <16 x i8>* %s, align 16
893    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
894    ret <16 x i8> %1
895}
896
897define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
898; P9-LABEL: adjusted_lxvdsx_v16i8:
899; P9:       # %bb.0: # %entry
900; P9-NEXT:    addi r3, r3, 8
901; P9-NEXT:    lxvdsx v2, 0, r3
902; P9-NEXT:    blr
903;
904; P8-LABEL: adjusted_lxvdsx_v16i8:
905; P8:       # %bb.0: # %entry
906; P8-NEXT:    addi r3, r3, 8
907; P8-NEXT:    lxvdsx v2, 0, r3
908; P8-NEXT:    blr
909;
910; P7-LABEL: adjusted_lxvdsx_v16i8:
911; P7:       # %bb.0: # %entry
912; P7-NEXT:    addi r3, r3, 8
913; P7-NEXT:    lxvdsx v2, 0, r3
914; P7-NEXT:    blr
915;
916; P9-AIX32-LABEL: adjusted_lxvdsx_v16i8:
917; P9-AIX32:       # %bb.0: # %entry
918; P9-AIX32-NEXT:    addi r3, r3, 8
919; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
920; P9-AIX32-NEXT:    blr
921;
922; P8-AIX32-LABEL: adjusted_lxvdsx_v16i8:
923; P8-AIX32:       # %bb.0: # %entry
924; P8-AIX32-NEXT:    addi r3, r3, 8
925; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
926; P8-AIX32-NEXT:    blr
927;
928; P7-AIX32-LABEL: adjusted_lxvdsx_v16i8:
929; P7-AIX32:       # %bb.0: # %entry
930; P7-AIX32-NEXT:    addi r3, r3, 8
931; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
932; P7-AIX32-NEXT:    blr
933  entry:
934    %0 = load <16 x i8>, <16 x i8>* %s, align 16
935    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
936    ret <16 x i8> %1
937}
938
939define <8 x i16> @test_unaligned_v8i16(i16* %Ptr) {
940; P9-LABEL: test_unaligned_v8i16:
941; P9:       # %bb.0: # %entry
942; P9-NEXT:    addi r3, r3, 6
943; P9-NEXT:    lxsihzx v2, 0, r3
944; P9-NEXT:    vsplth v2, v2, 3
945; P9-NEXT:    blr
946;
947; P8-LABEL: test_unaligned_v8i16:
948; P8:       # %bb.0: # %entry
949; P8-NEXT:    lhz r3, 6(r3)
950; P8-NEXT:    mtvsrwz v2, r3
951; P8-NEXT:    vsplth v2, v2, 3
952; P8-NEXT:    blr
953;
954; P7-LABEL: test_unaligned_v8i16:
955; P7:       # %bb.0: # %entry
956; P7-NEXT:    li r4, 1
957; P7-NEXT:    addi r3, r3, 6
958; P7-NEXT:    lvx v2, 0, r3
959; P7-NEXT:    lvx v3, r4, r3
960; P7-NEXT:    lvsl v4, 0, r3
961; P7-NEXT:    vperm v2, v2, v3, v4
962; P7-NEXT:    vsplth v2, v2, 0
963; P7-NEXT:    blr
964;
965; P9-AIX32-LABEL: test_unaligned_v8i16:
966; P9-AIX32:       # %bb.0: # %entry
967; P9-AIX32-NEXT:    addi r3, r3, 6
968; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
969; P9-AIX32-NEXT:    vsplth v2, v2, 3
970; P9-AIX32-NEXT:    blr
971;
972; P8-AIX32-LABEL: test_unaligned_v8i16:
973; P8-AIX32:       # %bb.0: # %entry
974; P8-AIX32-NEXT:    lhz r3, 6(r3)
975; P8-AIX32-NEXT:    mtvsrwz v2, r3
976; P8-AIX32-NEXT:    vsplth v2, v2, 3
977; P8-AIX32-NEXT:    blr
978;
979; P7-AIX32-LABEL: test_unaligned_v8i16:
980; P7-AIX32:       # %bb.0: # %entry
981; P7-AIX32-NEXT:    li r4, 1
982; P7-AIX32-NEXT:    addi r3, r3, 6
983; P7-AIX32-NEXT:    lvx v2, 0, r3
984; P7-AIX32-NEXT:    lvx v3, r4, r3
985; P7-AIX32-NEXT:    lvsl v4, 0, r3
986; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
987; P7-AIX32-NEXT:    vsplth v2, v2, 0
988; P7-AIX32-NEXT:    blr
989entry:
990  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 3
991  %0 = load i16, i16* %add.ptr, align 16
992  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
993  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
994  ret <8 x i16> %splat.splat
995}
996
997define <16 x i8> @test_unaligned_v16i8(i8* %Ptr) {
998; P9-LABEL: test_unaligned_v16i8:
999; P9:       # %bb.0: # %entry
1000; P9-NEXT:    addi r3, r3, 3
1001; P9-NEXT:    lxsibzx v2, 0, r3
1002; P9-NEXT:    vspltb v2, v2, 7
1003; P9-NEXT:    blr
1004;
1005; P8-LABEL: test_unaligned_v16i8:
1006; P8:       # %bb.0: # %entry
1007; P8-NEXT:    lbz r3, 3(r3)
1008; P8-NEXT:    mtvsrwz v2, r3
1009; P8-NEXT:    vspltb v2, v2, 7
1010; P8-NEXT:    blr
1011;
1012; P7-LABEL: test_unaligned_v16i8:
1013; P7:       # %bb.0: # %entry
1014; P7-NEXT:    addi r3, r3, 3
1015; P7-NEXT:    lvsl v2, 0, r3
1016; P7-NEXT:    lvx v3, 0, r3
1017; P7-NEXT:    vperm v2, v3, v3, v2
1018; P7-NEXT:    vspltb v2, v2, 0
1019; P7-NEXT:    blr
1020;
1021; P9-AIX32-LABEL: test_unaligned_v16i8:
1022; P9-AIX32:       # %bb.0: # %entry
1023; P9-AIX32-NEXT:    addi r3, r3, 3
1024; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1025; P9-AIX32-NEXT:    vspltb v2, v2, 7
1026; P9-AIX32-NEXT:    blr
1027;
1028; P8-AIX32-LABEL: test_unaligned_v16i8:
1029; P8-AIX32:       # %bb.0: # %entry
1030; P8-AIX32-NEXT:    lbz r3, 3(r3)
1031; P8-AIX32-NEXT:    mtvsrwz v2, r3
1032; P8-AIX32-NEXT:    vspltb v2, v2, 7
1033; P8-AIX32-NEXT:    blr
1034;
1035; P7-AIX32-LABEL: test_unaligned_v16i8:
1036; P7-AIX32:       # %bb.0: # %entry
1037; P7-AIX32-NEXT:    addi r3, r3, 3
1038; P7-AIX32-NEXT:    lvsl v2, 0, r3
1039; P7-AIX32-NEXT:    lvx v3, 0, r3
1040; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
1041; P7-AIX32-NEXT:    vspltb v2, v2, 0
1042; P7-AIX32-NEXT:    blr
1043entry:
1044  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 3
1045  %0 = load i8, i8* %add.ptr, align 16
1046  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1047  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1048  ret <16 x i8> %splat.splat
1049}
1050
1051define <8 x i16> @test_aligned_v8i16_1(i16* %Ptr) {
1052; P9-LABEL: test_aligned_v8i16_1:
1053; P9:       # %bb.0: # %entry
1054; P9-NEXT:    lxsihzx v2, 0, r3
1055; P9-NEXT:    vsplth v2, v2, 3
1056; P9-NEXT:    blr
1057;
1058; P8-LABEL: test_aligned_v8i16_1:
1059; P8:       # %bb.0: # %entry
1060; P8-NEXT:    lvx v2, 0, r3
1061; P8-NEXT:    vsplth v2, v2, 7
1062; P8-NEXT:    blr
1063;
1064; P7-LABEL: test_aligned_v8i16_1:
1065; P7:       # %bb.0: # %entry
1066; P7-NEXT:    lvx v2, 0, r3
1067; P7-NEXT:    vsplth v2, v2, 0
1068; P7-NEXT:    blr
1069;
1070; P9-AIX32-LABEL: test_aligned_v8i16_1:
1071; P9-AIX32:       # %bb.0: # %entry
1072; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1073; P9-AIX32-NEXT:    vsplth v2, v2, 3
1074; P9-AIX32-NEXT:    blr
1075;
1076; P8-AIX32-LABEL: test_aligned_v8i16_1:
1077; P8-AIX32:       # %bb.0: # %entry
1078; P8-AIX32-NEXT:    lvx v2, 0, r3
1079; P8-AIX32-NEXT:    vsplth v2, v2, 0
1080; P8-AIX32-NEXT:    blr
1081;
1082; P7-AIX32-LABEL: test_aligned_v8i16_1:
1083; P7-AIX32:       # %bb.0: # %entry
1084; P7-AIX32-NEXT:    lvx v2, 0, r3
1085; P7-AIX32-NEXT:    vsplth v2, v2, 0
1086; P7-AIX32-NEXT:    blr
1087entry:
1088  %0 = load i16, i16* %Ptr, align 16
1089  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1090  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1091  ret <8 x i16> %splat.splat
1092}
1093
1094define <8 x i16> @test_aligned_v8i16_2(i16* %Ptr) {
1095; P9-LABEL: test_aligned_v8i16_2:
1096; P9:       # %bb.0: # %entry
1097; P9-NEXT:    addi r3, r3, 32
1098; P9-NEXT:    lxsihzx v2, 0, r3
1099; P9-NEXT:    vsplth v2, v2, 3
1100; P9-NEXT:    blr
1101;
1102; P8-LABEL: test_aligned_v8i16_2:
1103; P8:       # %bb.0: # %entry
1104; P8-NEXT:    addi r3, r3, 32
1105; P8-NEXT:    lvx v2, 0, r3
1106; P8-NEXT:    vsplth v2, v2, 7
1107; P8-NEXT:    blr
1108;
1109; P7-LABEL: test_aligned_v8i16_2:
1110; P7:       # %bb.0: # %entry
1111; P7-NEXT:    addi r3, r3, 32
1112; P7-NEXT:    lvx v2, 0, r3
1113; P7-NEXT:    vsplth v2, v2, 0
1114; P7-NEXT:    blr
1115;
1116; P9-AIX32-LABEL: test_aligned_v8i16_2:
1117; P9-AIX32:       # %bb.0: # %entry
1118; P9-AIX32-NEXT:    addi r3, r3, 32
1119; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1120; P9-AIX32-NEXT:    vsplth v2, v2, 3
1121; P9-AIX32-NEXT:    blr
1122;
1123; P8-AIX32-LABEL: test_aligned_v8i16_2:
1124; P8-AIX32:       # %bb.0: # %entry
1125; P8-AIX32-NEXT:    addi r3, r3, 32
1126; P8-AIX32-NEXT:    lvx v2, 0, r3
1127; P8-AIX32-NEXT:    vsplth v2, v2, 0
1128; P8-AIX32-NEXT:    blr
1129;
1130; P7-AIX32-LABEL: test_aligned_v8i16_2:
1131; P7-AIX32:       # %bb.0: # %entry
1132; P7-AIX32-NEXT:    addi r3, r3, 32
1133; P7-AIX32-NEXT:    lvx v2, 0, r3
1134; P7-AIX32-NEXT:    vsplth v2, v2, 0
1135; P7-AIX32-NEXT:    blr
1136entry:
1137  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 16
1138  %0 = load i16, i16* %add.ptr, align 16
1139  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1140  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1141  ret <8 x i16> %splat.splat
1142}
1143
1144define <16 x i8> @test_aligned_v16i8_1(i8* %Ptr) {
1145; P9-LABEL: test_aligned_v16i8_1:
1146; P9:       # %bb.0: # %entry
1147; P9-NEXT:    lxsibzx v2, 0, r3
1148; P9-NEXT:    vspltb v2, v2, 7
1149; P9-NEXT:    blr
1150;
1151; P8-LABEL: test_aligned_v16i8_1:
1152; P8:       # %bb.0: # %entry
1153; P8-NEXT:    lvx v2, 0, r3
1154; P8-NEXT:    vspltb v2, v2, 15
1155; P8-NEXT:    blr
1156;
1157; P7-LABEL: test_aligned_v16i8_1:
1158; P7:       # %bb.0: # %entry
1159; P7-NEXT:    lvx v2, 0, r3
1160; P7-NEXT:    vspltb v2, v2, 0
1161; P7-NEXT:    blr
1162;
1163; P9-AIX32-LABEL: test_aligned_v16i8_1:
1164; P9-AIX32:       # %bb.0: # %entry
1165; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1166; P9-AIX32-NEXT:    vspltb v2, v2, 7
1167; P9-AIX32-NEXT:    blr
1168;
1169; P8-AIX32-LABEL: test_aligned_v16i8_1:
1170; P8-AIX32:       # %bb.0: # %entry
1171; P8-AIX32-NEXT:    lvx v2, 0, r3
1172; P8-AIX32-NEXT:    vspltb v2, v2, 0
1173; P8-AIX32-NEXT:    blr
1174;
1175; P7-AIX32-LABEL: test_aligned_v16i8_1:
1176; P7-AIX32:       # %bb.0: # %entry
1177; P7-AIX32-NEXT:    lvx v2, 0, r3
1178; P7-AIX32-NEXT:    vspltb v2, v2, 0
1179; P7-AIX32-NEXT:    blr
1180entry:
1181  %0 = load i8, i8* %Ptr, align 16
1182  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1183  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1184  ret <16 x i8> %splat.splat
1185}
1186
1187define <16 x i8> @test_aligned_v16i8_2(i8* %Ptr) {
1188; P9-LABEL: test_aligned_v16i8_2:
1189; P9:       # %bb.0: # %entry
1190; P9-NEXT:    addi r3, r3, 16
1191; P9-NEXT:    lxsibzx v2, 0, r3
1192; P9-NEXT:    vspltb v2, v2, 7
1193; P9-NEXT:    blr
1194;
1195; P8-LABEL: test_aligned_v16i8_2:
1196; P8:       # %bb.0: # %entry
1197; P8-NEXT:    addi r3, r3, 16
1198; P8-NEXT:    lvx v2, 0, r3
1199; P8-NEXT:    vspltb v2, v2, 15
1200; P8-NEXT:    blr
1201;
1202; P7-LABEL: test_aligned_v16i8_2:
1203; P7:       # %bb.0: # %entry
1204; P7-NEXT:    addi r3, r3, 16
1205; P7-NEXT:    lvx v2, 0, r3
1206; P7-NEXT:    vspltb v2, v2, 0
1207; P7-NEXT:    blr
1208;
1209; P9-AIX32-LABEL: test_aligned_v16i8_2:
1210; P9-AIX32:       # %bb.0: # %entry
1211; P9-AIX32-NEXT:    addi r3, r3, 16
1212; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1213; P9-AIX32-NEXT:    vspltb v2, v2, 7
1214; P9-AIX32-NEXT:    blr
1215;
1216; P8-AIX32-LABEL: test_aligned_v16i8_2:
1217; P8-AIX32:       # %bb.0: # %entry
1218; P8-AIX32-NEXT:    addi r3, r3, 16
1219; P8-AIX32-NEXT:    lvx v2, 0, r3
1220; P8-AIX32-NEXT:    vspltb v2, v2, 0
1221; P8-AIX32-NEXT:    blr
1222;
1223; P7-AIX32-LABEL: test_aligned_v16i8_2:
1224; P7-AIX32:       # %bb.0: # %entry
1225; P7-AIX32-NEXT:    addi r3, r3, 16
1226; P7-AIX32-NEXT:    lvx v2, 0, r3
1227; P7-AIX32-NEXT:    vspltb v2, v2, 0
1228; P7-AIX32-NEXT:    blr
1229entry:
1230  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 16
1231  %0 = load i8, i8* %add.ptr, align 16
1232  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1233  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1234  ret <16 x i8> %splat.splat
1235}
1236
1237; The following test case should not produce a load and splat node,
1238; as we cannot handle extending loads (from f32 to f64), and this test
1239; shows that there are multiple uses of the extending load (other than
1240; a build vector node). `lxvdsx` should not be produced in this case.
1241define <2 x double> @test_v2f64_multiple_use(float* nocapture readonly %a, double* nocapture %b, double* nocapture %c) {
1242; P9-LABEL: test_v2f64_multiple_use:
1243; P9:       # %bb.0: # %entry
1244; P9-NEXT:    lfs f0, 0(r3)
1245; P9-NEXT:    xxspltd v2, vs0, 0
1246; P9-NEXT:    lfd f1, 0(r4)
1247; P9-NEXT:    xsadddp f1, f1, f0
1248; P9-NEXT:    stfd f1, 0(r4)
1249; P9-NEXT:    lfd f1, 0(r5)
1250; P9-NEXT:    xsadddp f1, f1, f0
1251; P9-NEXT:    stfd f1, 0(r5)
1252; P9-NEXT:    blr
1253;
1254; P8-LABEL: test_v2f64_multiple_use:
1255; P8:       # %bb.0: # %entry
1256; P8-NEXT:    lfs f0, 0(r3)
1257; P8-NEXT:    lfd f1, 0(r4)
1258; P8-NEXT:    xsadddp f1, f1, f0
1259; P8-NEXT:    xxspltd v2, vs0, 0
1260; P8-NEXT:    stfd f1, 0(r4)
1261; P8-NEXT:    lfd f1, 0(r5)
1262; P8-NEXT:    xsadddp f1, f1, f0
1263; P8-NEXT:    stfd f1, 0(r5)
1264; P8-NEXT:    blr
1265;
1266; P7-LABEL: test_v2f64_multiple_use:
1267; P7:       # %bb.0: # %entry
1268; P7-NEXT:    lfs f0, 0(r3)
1269; P7-NEXT:    lfd f1, 0(r4)
1270; P7-NEXT:    xsadddp f1, f1, f0
1271; P7-NEXT:    xxspltd v2, vs0, 0
1272; P7-NEXT:    stfd f1, 0(r4)
1273; P7-NEXT:    lfd f1, 0(r5)
1274; P7-NEXT:    xsadddp f1, f1, f0
1275; P7-NEXT:    stfd f1, 0(r5)
1276; P7-NEXT:    blr
1277;
1278; P9-AIX32-LABEL: test_v2f64_multiple_use:
1279; P9-AIX32:       # %bb.0: # %entry
1280; P9-AIX32-NEXT:    lfs f0, 0(r3)
1281; P9-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1282; P9-AIX32-NEXT:    lfd f1, 0(r4)
1283; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1284; P9-AIX32-NEXT:    stfd f1, 0(r4)
1285; P9-AIX32-NEXT:    lfd f1, 0(r5)
1286; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1287; P9-AIX32-NEXT:    stfd f1, 0(r5)
1288; P9-AIX32-NEXT:    blr
1289;
1290; P8-AIX32-LABEL: test_v2f64_multiple_use:
1291; P8-AIX32:       # %bb.0: # %entry
1292; P8-AIX32-NEXT:    lfs f0, 0(r3)
1293; P8-AIX32-NEXT:    lfd f1, 0(r4)
1294; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1295; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1296; P8-AIX32-NEXT:    stfd f1, 0(r4)
1297; P8-AIX32-NEXT:    lfd f1, 0(r5)
1298; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1299; P8-AIX32-NEXT:    stfd f1, 0(r5)
1300; P8-AIX32-NEXT:    blr
1301;
1302; P7-AIX32-LABEL: test_v2f64_multiple_use:
1303; P7-AIX32:       # %bb.0: # %entry
1304; P7-AIX32-NEXT:    lfs f0, 0(r3)
1305; P7-AIX32-NEXT:    lfd f1, 0(r4)
1306; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1307; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1308; P7-AIX32-NEXT:    stfd f1, 0(r4)
1309; P7-AIX32-NEXT:    lfd f1, 0(r5)
1310; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1311; P7-AIX32-NEXT:    stfd f1, 0(r5)
1312; P7-AIX32-NEXT:    blr
1313entry:
1314  %0 = load float, float* %a, align 4
1315  %conv = fpext float %0 to double
1316  %1 = load double, double* %b, align 8
1317  %add = fadd double %1, %conv
1318  store double %add, double* %b, align 8
1319  %2 = load double, double* %c, align 8
1320  %add2 = fadd double %2, %conv
1321  store double %add2, double* %c, align 8
1322  %vecinit = insertelement <2 x double> undef, double %conv, i64 0
1323  %vecinit5 = shufflevector <2 x double> %vecinit, <2 x double> poison, <2 x i32> zeroinitializer
1324  ret <2 x double> %vecinit5
1325}
1326