1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
4; RUN:   -check-prefix=P9
5; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6; RUN:   -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
7; RUN:   -check-prefix=P8
8; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9; RUN:   -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
10; RUN:   -check-prefix=P7
11; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
13; RUN:   -check-prefix=P9-AIX32
14; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
15; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
16; RUN:   -check-prefix=P8-AIX32
17; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
18; RUN:   -mtriple=powerpc-ibm-aix-xcoff < %s | FileCheck %s \
19; RUN:   -check-prefix=P7-AIX32
20
21; v2f64
22define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
23; P9-LABEL: test:
24; P9:       # %bb.0: # %entry
25; P9-NEXT:    addi r4, r4, 24
26; P9-NEXT:    lxvdsx vs0, 0, r4
27; P9-NEXT:    stxv vs0, 0(r3)
28; P9-NEXT:    blr
29;
30; P8-LABEL: test:
31; P8:       # %bb.0: # %entry
32; P8-NEXT:    addi r4, r4, 24
33; P8-NEXT:    lxvdsx vs0, 0, r4
34; P8-NEXT:    stxvd2x vs0, 0, r3
35; P8-NEXT:    blr
36;
37; P7-LABEL: test:
38; P7:       # %bb.0: # %entry
39; P7-NEXT:    addi r4, r4, 24
40; P7-NEXT:    lxvdsx vs0, 0, r4
41; P7-NEXT:    stxvd2x vs0, 0, r3
42; P7-NEXT:    blr
43;
44; P9-AIX32-LABEL: test:
45; P9-AIX32:       # %bb.0: # %entry
46; P9-AIX32-NEXT:    addi r4, r4, 24
47; P9-AIX32-NEXT:    lxvdsx vs0, 0, r4
48; P9-AIX32-NEXT:    stxv vs0, 0(r3)
49; P9-AIX32-NEXT:    blr
50;
51; P8-AIX32-LABEL: test:
52; P8-AIX32:       # %bb.0: # %entry
53; P8-AIX32-NEXT:    addi r4, r4, 24
54; P8-AIX32-NEXT:    lxvdsx vs0, 0, r4
55; P8-AIX32-NEXT:    stxvd2x vs0, 0, r3
56; P8-AIX32-NEXT:    blr
57;
58; P7-AIX32-LABEL: test:
59; P7-AIX32:       # %bb.0: # %entry
60; P7-AIX32-NEXT:    addi r4, r4, 24
61; P7-AIX32-NEXT:    lxvdsx vs0, 0, r4
62; P7-AIX32-NEXT:    stxvd2x vs0, 0, r3
63; P7-AIX32-NEXT:    blr
64entry:
65  %arrayidx = getelementptr inbounds double, double* %a, i64 3
66  %0 = load double, double* %arrayidx, align 8
67  %splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
68  %splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> zeroinitializer
69  store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
70  ret void
71}
72
73; v4f32
74define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonly %a) local_unnamed_addr {
75; P9-LABEL: test2:
76; P9:       # %bb.0: # %entry
77; P9-NEXT:    addi r4, r4, 12
78; P9-NEXT:    lxvwsx vs0, 0, r4
79; P9-NEXT:    stxv vs0, 0(r3)
80; P9-NEXT:    blr
81;
82; P8-LABEL: test2:
83; P8:       # %bb.0: # %entry
84; P8-NEXT:    addi r4, r4, 12
85; P8-NEXT:    lfiwzx f0, 0, r4
86; P8-NEXT:    xxspltw v2, vs0, 1
87; P8-NEXT:    stvx v2, 0, r3
88; P8-NEXT:    blr
89;
90; P7-LABEL: test2:
91; P7:       # %bb.0: # %entry
92; P7-NEXT:    addi r4, r4, 12
93; P7-NEXT:    lfiwzx f0, 0, r4
94; P7-NEXT:    xxspltw vs0, vs0, 1
95; P7-NEXT:    stxvw4x vs0, 0, r3
96; P7-NEXT:    blr
97;
98; P9-AIX32-LABEL: test2:
99; P9-AIX32:       # %bb.0: # %entry
100; P9-AIX32-NEXT:    addi r4, r4, 12
101; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
102; P9-AIX32-NEXT:    stxv vs0, 0(r3)
103; P9-AIX32-NEXT:    blr
104;
105; P8-AIX32-LABEL: test2:
106; P8-AIX32:       # %bb.0: # %entry
107; P8-AIX32-NEXT:    addi r4, r4, 12
108; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
109; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
110; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
111; P8-AIX32-NEXT:    blr
112;
113; P7-AIX32-LABEL: test2:
114; P7-AIX32:       # %bb.0: # %entry
115; P7-AIX32-NEXT:    addi r4, r4, 12
116; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
117; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
118; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
119; P7-AIX32-NEXT:    blr
120entry:
121  %arrayidx = getelementptr inbounds float, float* %a, i64 3
122  %0 = load float, float* %arrayidx, align 4
123  %splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
124  %splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
125  store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
126  ret void
127}
128
129; v4i32
130define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
131; P9-LABEL: test3:
132; P9:       # %bb.0: # %entry
133; P9-NEXT:    addi r4, r4, 12
134; P9-NEXT:    lxvwsx vs0, 0, r4
135; P9-NEXT:    stxv vs0, 0(r3)
136; P9-NEXT:    blr
137;
138; P8-LABEL: test3:
139; P8:       # %bb.0: # %entry
140; P8-NEXT:    addi r4, r4, 12
141; P8-NEXT:    lfiwzx f0, 0, r4
142; P8-NEXT:    xxspltw v2, vs0, 1
143; P8-NEXT:    stvx v2, 0, r3
144; P8-NEXT:    blr
145;
146; P7-LABEL: test3:
147; P7:       # %bb.0: # %entry
148; P7-NEXT:    addi r4, r4, 12
149; P7-NEXT:    lfiwzx f0, 0, r4
150; P7-NEXT:    xxspltw vs0, vs0, 1
151; P7-NEXT:    stxvw4x vs0, 0, r3
152; P7-NEXT:    blr
153;
154; P9-AIX32-LABEL: test3:
155; P9-AIX32:       # %bb.0: # %entry
156; P9-AIX32-NEXT:    addi r4, r4, 12
157; P9-AIX32-NEXT:    lxvwsx vs0, 0, r4
158; P9-AIX32-NEXT:    stxv vs0, 0(r3)
159; P9-AIX32-NEXT:    blr
160;
161; P8-AIX32-LABEL: test3:
162; P8-AIX32:       # %bb.0: # %entry
163; P8-AIX32-NEXT:    addi r4, r4, 12
164; P8-AIX32-NEXT:    lfiwzx f0, 0, r4
165; P8-AIX32-NEXT:    xxspltw vs0, vs0, 1
166; P8-AIX32-NEXT:    stxvw4x vs0, 0, r3
167; P8-AIX32-NEXT:    blr
168;
169; P7-AIX32-LABEL: test3:
170; P7-AIX32:       # %bb.0: # %entry
171; P7-AIX32-NEXT:    addi r4, r4, 12
172; P7-AIX32-NEXT:    lfiwzx f0, 0, r4
173; P7-AIX32-NEXT:    xxspltw vs0, vs0, 1
174; P7-AIX32-NEXT:    stxvw4x vs0, 0, r3
175; P7-AIX32-NEXT:    blr
176entry:
177  %arrayidx = getelementptr inbounds i32, i32* %a, i64 3
178  %0 = load i32, i32* %arrayidx, align 4
179  %splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
180  %splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
181  store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
182  ret void
183}
184
185
186; v2i64
187define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a) local_unnamed_addr {
188; P9-LABEL: test4:
189; P9:       # %bb.0: # %entry
190; P9-NEXT:    addi r4, r4, 24
191; P9-NEXT:    lxvdsx vs0, 0, r4
192; P9-NEXT:    stxv vs0, 0(r3)
193; P9-NEXT:    blr
194;
195; P8-LABEL: test4:
196; P8:       # %bb.0: # %entry
197; P8-NEXT:    addi r4, r4, 24
198; P8-NEXT:    lxvdsx vs0, 0, r4
199; P8-NEXT:    stxvd2x vs0, 0, r3
200; P8-NEXT:    blr
201;
202; P7-LABEL: test4:
203; P7:       # %bb.0: # %entry
204; P7-NEXT:    addi r4, r4, 24
205; P7-NEXT:    lxvdsx vs0, 0, r4
206; P7-NEXT:    stxvd2x vs0, 0, r3
207; P7-NEXT:    blr
208;
209; P9-AIX32-LABEL: test4:
210; P9-AIX32:       # %bb.0: # %entry
211; P9-AIX32-NEXT:    lwz r5, 24(r4)
212; P9-AIX32-NEXT:    lwz r4, 28(r4)
213; P9-AIX32-NEXT:    stw r4, -16(r1)
214; P9-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
215; P9-AIX32-NEXT:    stw r5, -32(r1)
216; P9-AIX32-NEXT:    lxv v3, -16(r1)
217; P9-AIX32-NEXT:    lxv v4, -32(r1)
218; P9-AIX32-NEXT:    lxv v2, 0(r4)
219; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
220; P9-AIX32-NEXT:    stxv v2, 0(r3)
221; P9-AIX32-NEXT:    blr
222;
223; P8-AIX32-LABEL: test4:
224; P8-AIX32:       # %bb.0: # %entry
225; P8-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
226; P8-AIX32-NEXT:    lwz r6, 28(r4)
227; P8-AIX32-NEXT:    lwz r4, 24(r4)
228; P8-AIX32-NEXT:    stw r6, -16(r1)
229; P8-AIX32-NEXT:    stw r4, -32(r1)
230; P8-AIX32-NEXT:    addi r4, r1, -16
231; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
232; P8-AIX32-NEXT:    addi r5, r1, -32
233; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
234; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
235; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
236; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
237; P8-AIX32-NEXT:    blr
238;
239; P7-AIX32-LABEL: test4:
240; P7-AIX32:       # %bb.0: # %entry
241; P7-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
242; P7-AIX32-NEXT:    lwz r6, 24(r4)
243; P7-AIX32-NEXT:    lwz r4, 28(r4)
244; P7-AIX32-NEXT:    stw r4, -16(r1)
245; P7-AIX32-NEXT:    stw r6, -32(r1)
246; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
247; P7-AIX32-NEXT:    addi r4, r1, -16
248; P7-AIX32-NEXT:    addi r5, r1, -32
249; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
250; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
251; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
252; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
253; P7-AIX32-NEXT:    blr
254entry:
255  %arrayidx = getelementptr inbounds i64, i64* %a, i64 3
256  %0 = load i64, i64* %arrayidx, align 8
257  %splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
258  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
259  store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
260  ret void
261}
262
263; sext v2i64
264define void @test5(<2 x i64>* %a, i32* %in) {
265; P9-LABEL: test5:
266; P9:       # %bb.0: # %entry
267; P9-NEXT:    lfiwax f0, 0, r4
268; P9-NEXT:    xxspltd vs0, f0, 0
269; P9-NEXT:    stxv vs0, 0(r3)
270; P9-NEXT:    blr
271;
272; P8-LABEL: test5:
273; P8:       # %bb.0: # %entry
274; P8-NEXT:    lfiwax f0, 0, r4
275; P8-NEXT:    xxspltd vs0, f0, 0
276; P8-NEXT:    stxvd2x vs0, 0, r3
277; P8-NEXT:    blr
278;
279; P7-LABEL: test5:
280; P7:       # %bb.0: # %entry
281; P7-NEXT:    lfiwax f0, 0, r4
282; P7-NEXT:    xxspltd vs0, f0, 0
283; P7-NEXT:    stxvd2x vs0, 0, r3
284; P7-NEXT:    blr
285;
286; P9-AIX32-LABEL: test5:
287; P9-AIX32:       # %bb.0: # %entry
288; P9-AIX32-NEXT:    lwz r4, 0(r4)
289; P9-AIX32-NEXT:    srawi r5, r4, 31
290; P9-AIX32-NEXT:    stw r4, -16(r1)
291; P9-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
292; P9-AIX32-NEXT:    lxv v3, -16(r1)
293; P9-AIX32-NEXT:    stw r5, -32(r1)
294; P9-AIX32-NEXT:    lxv v4, -32(r1)
295; P9-AIX32-NEXT:    lxv v2, 0(r4)
296; P9-AIX32-NEXT:    vperm v2, v4, v3, v2
297; P9-AIX32-NEXT:    stxv v2, 0(r3)
298; P9-AIX32-NEXT:    blr
299;
300; P8-AIX32-LABEL: test5:
301; P8-AIX32:       # %bb.0: # %entry
302; P8-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
303; P8-AIX32-NEXT:    lwz r4, 0(r4)
304; P8-AIX32-NEXT:    stw r4, -16(r1)
305; P8-AIX32-NEXT:    srawi r4, r4, 31
306; P8-AIX32-NEXT:    stw r4, -32(r1)
307; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
308; P8-AIX32-NEXT:    addi r4, r1, -16
309; P8-AIX32-NEXT:    addi r5, r1, -32
310; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
311; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
312; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
313; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
314; P8-AIX32-NEXT:    blr
315;
316; P7-AIX32-LABEL: test5:
317; P7-AIX32:       # %bb.0: # %entry
318; P7-AIX32-NEXT:    lwz r4, 0(r4)
319; P7-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
320; P7-AIX32-NEXT:    srawi r6, r4, 31
321; P7-AIX32-NEXT:    stw r4, -16(r1)
322; P7-AIX32-NEXT:    addi r4, r1, -16
323; P7-AIX32-NEXT:    stw r6, -32(r1)
324; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
325; P7-AIX32-NEXT:    addi r5, r1, -32
326; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
327; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
328; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
329; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
330; P7-AIX32-NEXT:    blr
331entry:
332  %0 = load i32, i32* %in, align 4
333  %conv = sext i32 %0 to i64
334  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
335  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
336  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
337  ret void
338}
339
340; zext v2i64
341define void @test6(<2 x i64>* %a, i32* %in) {
342; P9-LABEL: test6:
343; P9:       # %bb.0: # %entry
344; P9-NEXT:    lfiwzx f0, 0, r4
345; P9-NEXT:    xxspltd vs0, f0, 0
346; P9-NEXT:    stxv vs0, 0(r3)
347; P9-NEXT:    blr
348;
349; P8-LABEL: test6:
350; P8:       # %bb.0: # %entry
351; P8-NEXT:    lfiwzx f0, 0, r4
352; P8-NEXT:    xxspltd vs0, f0, 0
353; P8-NEXT:    stxvd2x vs0, 0, r3
354; P8-NEXT:    blr
355;
356; P7-LABEL: test6:
357; P7:       # %bb.0: # %entry
358; P7-NEXT:    lfiwzx f0, 0, r4
359; P7-NEXT:    xxspltd vs0, f0, 0
360; P7-NEXT:    stxvd2x vs0, 0, r3
361; P7-NEXT:    blr
362;
363; P9-AIX32-LABEL: test6:
364; P9-AIX32:       # %bb.0: # %entry
365; P9-AIX32-NEXT:    lwz r4, 0(r4)
366; P9-AIX32-NEXT:    li r5, 0
367; P9-AIX32-NEXT:    stw r5, -32(r1)
368; P9-AIX32-NEXT:    lxv v3, -32(r1)
369; P9-AIX32-NEXT:    stw r4, -16(r1)
370; P9-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
371; P9-AIX32-NEXT:    lxv v4, -16(r1)
372; P9-AIX32-NEXT:    lxv v2, 0(r4)
373; P9-AIX32-NEXT:    vperm v2, v3, v4, v2
374; P9-AIX32-NEXT:    stxv v2, 0(r3)
375; P9-AIX32-NEXT:    blr
376;
377; P8-AIX32-LABEL: test6:
378; P8-AIX32:       # %bb.0: # %entry
379; P8-AIX32-NEXT:    lwz r6, L..C2(r2) # %const.0
380; P8-AIX32-NEXT:    lwz r4, 0(r4)
381; P8-AIX32-NEXT:    li r5, 0
382; P8-AIX32-NEXT:    stw r5, -32(r1)
383; P8-AIX32-NEXT:    addi r5, r1, -16
384; P8-AIX32-NEXT:    stw r4, -16(r1)
385; P8-AIX32-NEXT:    addi r4, r1, -32
386; P8-AIX32-NEXT:    lxvw4x v2, 0, r6
387; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
388; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
389; P8-AIX32-NEXT:    vperm v2, v3, v4, v2
390; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
391; P8-AIX32-NEXT:    blr
392;
393; P7-AIX32-LABEL: test6:
394; P7-AIX32:       # %bb.0: # %entry
395; P7-AIX32-NEXT:    lwz r5, L..C2(r2) # %const.0
396; P7-AIX32-NEXT:    lwz r4, 0(r4)
397; P7-AIX32-NEXT:    li r6, 0
398; P7-AIX32-NEXT:    stw r6, -32(r1)
399; P7-AIX32-NEXT:    stw r4, -16(r1)
400; P7-AIX32-NEXT:    addi r4, r1, -32
401; P7-AIX32-NEXT:    lxvw4x v2, 0, r5
402; P7-AIX32-NEXT:    addi r5, r1, -16
403; P7-AIX32-NEXT:    lxvw4x v3, 0, r4
404; P7-AIX32-NEXT:    lxvw4x v4, 0, r5
405; P7-AIX32-NEXT:    vperm v2, v3, v4, v2
406; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
407; P7-AIX32-NEXT:    blr
408entry:
409  %0 = load i32, i32* %in, align 4
410  %conv = zext i32 %0 to i64
411  %splat.splatinsert.i = insertelement <2 x i64> poison, i64 %conv, i32 0
412  %splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> poison, <2 x i32> zeroinitializer
413  store <2 x i64> %splat.splat.i, <2 x i64>* %a, align 16
414  ret void
415}
416
417; v8i16
418define void @test7(<8 x i16>* %a, i16* %in) {
419; P9-LABEL: test7:
420; P9:       # %bb.0: # %entry
421; P9-NEXT:    lxsihzx v2, 0, r4
422; P9-NEXT:    vsplth v2, v2, 3
423; P9-NEXT:    stxv v2, 0(r3)
424; P9-NEXT:    blr
425;
426; P8-LABEL: test7:
427; P8:       # %bb.0: # %entry
428; P8-NEXT:    lhzx r4, 0, r4
429; P8-NEXT:    mtvsrwz v2, r4
430; P8-NEXT:    vsplth v2, v2, 3
431; P8-NEXT:    stvx v2, 0, r3
432; P8-NEXT:    blr
433;
434; P7-LABEL: test7:
435; P7:       # %bb.0: # %entry
436; P7-NEXT:    li r5, 1
437; P7-NEXT:    lvx v2, 0, r4
438; P7-NEXT:    lvsl v4, 0, r4
439; P7-NEXT:    lvx v3, r5, r4
440; P7-NEXT:    vperm v2, v2, v3, v4
441; P7-NEXT:    vsplth v2, v2, 0
442; P7-NEXT:    stxvw4x v2, 0, r3
443; P7-NEXT:    blr
444;
445; P9-AIX32-LABEL: test7:
446; P9-AIX32:       # %bb.0: # %entry
447; P9-AIX32-NEXT:    lxsihzx v2, 0, r4
448; P9-AIX32-NEXT:    vsplth v2, v2, 3
449; P9-AIX32-NEXT:    stxv v2, 0(r3)
450; P9-AIX32-NEXT:    blr
451;
452; P8-AIX32-LABEL: test7:
453; P8-AIX32:       # %bb.0: # %entry
454; P8-AIX32-NEXT:    lhzx r4, 0, r4
455; P8-AIX32-NEXT:    mtvsrwz v2, r4
456; P8-AIX32-NEXT:    vsplth v2, v2, 3
457; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
458; P8-AIX32-NEXT:    blr
459;
460; P7-AIX32-LABEL: test7:
461; P7-AIX32:       # %bb.0: # %entry
462; P7-AIX32-NEXT:    li r5, 1
463; P7-AIX32-NEXT:    lvx v2, 0, r4
464; P7-AIX32-NEXT:    lvsl v4, 0, r4
465; P7-AIX32-NEXT:    lvx v3, r5, r4
466; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
467; P7-AIX32-NEXT:    vsplth v2, v2, 0
468; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
469; P7-AIX32-NEXT:    blr
470entry:
471  %0 = load i16, i16* %in, align 2
472  %splat.splatinsert.i = insertelement <8 x i16> poison, i16 %0, i32 0
473  %splat.splat.i = shufflevector <8 x i16> %splat.splatinsert.i, <8 x i16> poison, <8 x i32> zeroinitializer
474  store <8 x i16> %splat.splat.i, <8 x i16>* %a, align 16
475  ret void
476}
477
478; v16i8
479define void @test8(<16 x i8>* %a, i8* %in) {
480; P9-LABEL: test8:
481; P9:       # %bb.0: # %entry
482; P9-NEXT:    lxsibzx v2, 0, r4
483; P9-NEXT:    vspltb v2, v2, 7
484; P9-NEXT:    stxv v2, 0(r3)
485; P9-NEXT:    blr
486;
487; P8-LABEL: test8:
488; P8:       # %bb.0: # %entry
489; P8-NEXT:    lbzx r4, 0, r4
490; P8-NEXT:    mtvsrwz v2, r4
491; P8-NEXT:    vspltb v2, v2, 7
492; P8-NEXT:    stvx v2, 0, r3
493; P8-NEXT:    blr
494;
495; P7-LABEL: test8:
496; P7:       # %bb.0: # %entry
497; P7-NEXT:    lvsl v2, 0, r4
498; P7-NEXT:    lvx v3, 0, r4
499; P7-NEXT:    vperm v2, v3, v3, v2
500; P7-NEXT:    vspltb v2, v2, 0
501; P7-NEXT:    stxvw4x v2, 0, r3
502; P7-NEXT:    blr
503;
504; P9-AIX32-LABEL: test8:
505; P9-AIX32:       # %bb.0: # %entry
506; P9-AIX32-NEXT:    lxsibzx v2, 0, r4
507; P9-AIX32-NEXT:    vspltb v2, v2, 7
508; P9-AIX32-NEXT:    stxv v2, 0(r3)
509; P9-AIX32-NEXT:    blr
510;
511; P8-AIX32-LABEL: test8:
512; P8-AIX32:       # %bb.0: # %entry
513; P8-AIX32-NEXT:    lbzx r4, 0, r4
514; P8-AIX32-NEXT:    mtvsrwz v2, r4
515; P8-AIX32-NEXT:    vspltb v2, v2, 7
516; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
517; P8-AIX32-NEXT:    blr
518;
519; P7-AIX32-LABEL: test8:
520; P7-AIX32:       # %bb.0: # %entry
521; P7-AIX32-NEXT:    lvsl v2, 0, r4
522; P7-AIX32-NEXT:    lvx v3, 0, r4
523; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
524; P7-AIX32-NEXT:    vspltb v2, v2, 0
525; P7-AIX32-NEXT:    stxvw4x v2, 0, r3
526; P7-AIX32-NEXT:    blr
527entry:
528  %0 = load i8, i8* %in, align 1
529  %splat.splatinsert.i = insertelement <16 x i8> poison, i8 %0, i32 0
530  %splat.splat.i = shufflevector <16 x i8> %splat.splatinsert.i, <16 x i8> poison, <16 x i32> zeroinitializer
531  store <16 x i8> %splat.splat.i, <16 x i8>* %a, align 16
532  ret void
533}
534
535define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
536; P9-LABEL: unadjusted_lxvwsx:
537; P9:       # %bb.0: # %entry
538; P9-NEXT:    lxvwsx v2, 0, r3
539; P9-NEXT:    blr
540;
541; P8-LABEL: unadjusted_lxvwsx:
542; P8:       # %bb.0: # %entry
543; P8-NEXT:    lfiwzx f0, 0, r3
544; P8-NEXT:    xxspltw v2, vs0, 1
545; P8-NEXT:    blr
546;
547; P7-LABEL: unadjusted_lxvwsx:
548; P7:       # %bb.0: # %entry
549; P7-NEXT:    lwz r3, 0(r3)
550; P7-NEXT:    addi r4, r1, -16
551; P7-NEXT:    stw r3, -16(r1)
552; P7-NEXT:    lxvw4x vs0, 0, r4
553; P7-NEXT:    xxspltw v2, vs0, 0
554; P7-NEXT:    blr
555;
556; P9-AIX32-LABEL: unadjusted_lxvwsx:
557; P9-AIX32:       # %bb.0: # %entry
558; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
559; P9-AIX32-NEXT:    blr
560;
561; P8-AIX32-LABEL: unadjusted_lxvwsx:
562; P8-AIX32:       # %bb.0: # %entry
563; P8-AIX32-NEXT:    lwz r3, 0(r3)
564; P8-AIX32-NEXT:    mtfprwz f0, r3
565; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
566; P8-AIX32-NEXT:    blr
567;
568; P7-AIX32-LABEL: unadjusted_lxvwsx:
569; P7-AIX32:       # %bb.0: # %entry
570; P7-AIX32-NEXT:    lwz r3, 0(r3)
571; P7-AIX32-NEXT:    addi r4, r1, -16
572; P7-AIX32-NEXT:    stw r3, -16(r1)
573; P7-AIX32-NEXT:    lxvw4x vs0, 0, r4
574; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
575; P7-AIX32-NEXT:    blr
576  entry:
577    %0 = bitcast i32* %s to <4 x i8>*
578    %1 = load <4 x i8>, <4 x i8>* %0, align 4
579    %2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
580    ret <16 x i8> %2
581}
582
583define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
584; P9-LABEL: adjusted_lxvwsx:
585; P9:       # %bb.0: # %entry
586; P9-NEXT:    addi r3, r3, 4
587; P9-NEXT:    lxvwsx v2, 0, r3
588; P9-NEXT:    blr
589;
590; P8-LABEL: adjusted_lxvwsx:
591; P8:       # %bb.0: # %entry
592; P8-NEXT:    lfdx f0, 0, r3
593; P8-NEXT:    xxspltw v2, vs0, 0
594; P8-NEXT:    blr
595;
596; P7-LABEL: adjusted_lxvwsx:
597; P7:       # %bb.0: # %entry
598; P7-NEXT:    ld r3, 0(r3)
599; P7-NEXT:    addi r4, r1, -16
600; P7-NEXT:    std r3, -16(r1)
601; P7-NEXT:    lxvw4x vs0, 0, r4
602; P7-NEXT:    xxspltw v2, vs0, 1
603; P7-NEXT:    blr
604;
605; P9-AIX32-LABEL: adjusted_lxvwsx:
606; P9-AIX32:       # %bb.0: # %entry
607; P9-AIX32-NEXT:    addi r3, r3, 4
608; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
609; P9-AIX32-NEXT:    blr
610;
611; P8-AIX32-LABEL: adjusted_lxvwsx:
612; P8-AIX32:       # %bb.0: # %entry
613; P8-AIX32-NEXT:    addi r3, r3, 4
614; P8-AIX32-NEXT:    lfiwzx f0, 0, r3
615; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
616; P8-AIX32-NEXT:    blr
617;
618; P7-AIX32-LABEL: adjusted_lxvwsx:
619; P7-AIX32:       # %bb.0: # %entry
620; P7-AIX32-NEXT:    addi r3, r3, 4
621; P7-AIX32-NEXT:    lfiwzx f0, 0, r3
622; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
623; P7-AIX32-NEXT:    blr
624  entry:
625    %0 = bitcast i64* %s to <8 x i8>*
626    %1 = load <8 x i8>, <8 x i8>* %0, align 8
627    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
628    ret <16 x i8> %2
629}
630
631define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
632; P9-LABEL: unadjusted_lxvwsx_v16i8:
633; P9:       # %bb.0: # %entry
634; P9-NEXT:    lxvwsx v2, 0, r3
635; P9-NEXT:    blr
636;
637; P8-LABEL: unadjusted_lxvwsx_v16i8:
638; P8:       # %bb.0: # %entry
639; P8-NEXT:    lvx v2, 0, r3
640; P8-NEXT:    xxspltw v2, v2, 3
641; P8-NEXT:    blr
642;
643; P7-LABEL: unadjusted_lxvwsx_v16i8:
644; P7:       # %bb.0: # %entry
645; P7-NEXT:    lxvw4x vs0, 0, r3
646; P7-NEXT:    xxspltw v2, vs0, 0
647; P7-NEXT:    blr
648;
649; P9-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
650; P9-AIX32:       # %bb.0: # %entry
651; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
652; P9-AIX32-NEXT:    blr
653;
654; P8-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
655; P8-AIX32:       # %bb.0: # %entry
656; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
657; P8-AIX32-NEXT:    xxspltw v2, vs0, 0
658; P8-AIX32-NEXT:    blr
659;
660; P7-AIX32-LABEL: unadjusted_lxvwsx_v16i8:
661; P7-AIX32:       # %bb.0: # %entry
662; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
663; P7-AIX32-NEXT:    xxspltw v2, vs0, 0
664; P7-AIX32-NEXT:    blr
665  entry:
666    %0 = load <16 x i8>, <16 x i8>* %s, align 16
667    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
668    ret <16 x i8> %1
669}
670
671define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
672; P9-LABEL: adjusted_lxvwsx_v16i8:
673; P9:       # %bb.0: # %entry
674; P9-NEXT:    addi r3, r3, 4
675; P9-NEXT:    lxvwsx v2, 0, r3
676; P9-NEXT:    blr
677;
678; P8-LABEL: adjusted_lxvwsx_v16i8:
679; P8:       # %bb.0: # %entry
680; P8-NEXT:    lvx v2, 0, r3
681; P8-NEXT:    xxspltw v2, v2, 2
682; P8-NEXT:    blr
683;
684; P7-LABEL: adjusted_lxvwsx_v16i8:
685; P7:       # %bb.0: # %entry
686; P7-NEXT:    lxvw4x vs0, 0, r3
687; P7-NEXT:    xxspltw v2, vs0, 1
688; P7-NEXT:    blr
689;
690; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8:
691; P9-AIX32:       # %bb.0: # %entry
692; P9-AIX32-NEXT:    addi r3, r3, 4
693; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
694; P9-AIX32-NEXT:    blr
695;
696; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8:
697; P8-AIX32:       # %bb.0: # %entry
698; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
699; P8-AIX32-NEXT:    xxspltw v2, vs0, 1
700; P8-AIX32-NEXT:    blr
701;
702; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8:
703; P7-AIX32:       # %bb.0: # %entry
704; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
705; P7-AIX32-NEXT:    xxspltw v2, vs0, 1
706; P7-AIX32-NEXT:    blr
707  entry:
708    %0 = load <16 x i8>, <16 x i8>* %s, align 16
709    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
710    ret <16 x i8> %1
711}
712
713define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
714; P9-LABEL: adjusted_lxvwsx_v16i8_2:
715; P9:       # %bb.0: # %entry
716; P9-NEXT:    addi r3, r3, 8
717; P9-NEXT:    lxvwsx v2, 0, r3
718; P9-NEXT:    blr
719;
720; P8-LABEL: adjusted_lxvwsx_v16i8_2:
721; P8:       # %bb.0: # %entry
722; P8-NEXT:    lvx v2, 0, r3
723; P8-NEXT:    xxspltw v2, v2, 1
724; P8-NEXT:    blr
725;
726; P7-LABEL: adjusted_lxvwsx_v16i8_2:
727; P7:       # %bb.0: # %entry
728; P7-NEXT:    lxvw4x vs0, 0, r3
729; P7-NEXT:    xxspltw v2, vs0, 2
730; P7-NEXT:    blr
731;
732; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
733; P9-AIX32:       # %bb.0: # %entry
734; P9-AIX32-NEXT:    addi r3, r3, 8
735; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
736; P9-AIX32-NEXT:    blr
737;
738; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
739; P8-AIX32:       # %bb.0: # %entry
740; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
741; P8-AIX32-NEXT:    xxspltw v2, vs0, 2
742; P8-AIX32-NEXT:    blr
743;
744; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_2:
745; P7-AIX32:       # %bb.0: # %entry
746; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
747; P7-AIX32-NEXT:    xxspltw v2, vs0, 2
748; P7-AIX32-NEXT:    blr
749  entry:
750    %0 = load <16 x i8>, <16 x i8>* %s, align 16
751    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
752    ret <16 x i8> %1
753}
754
755define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
756; P9-LABEL: adjusted_lxvwsx_v16i8_3:
757; P9:       # %bb.0: # %entry
758; P9-NEXT:    addi r3, r3, 12
759; P9-NEXT:    lxvwsx v2, 0, r3
760; P9-NEXT:    blr
761;
762; P8-LABEL: adjusted_lxvwsx_v16i8_3:
763; P8:       # %bb.0: # %entry
764; P8-NEXT:    lvx v2, 0, r3
765; P8-NEXT:    xxspltw v2, v2, 0
766; P8-NEXT:    blr
767;
768; P7-LABEL: adjusted_lxvwsx_v16i8_3:
769; P7:       # %bb.0: # %entry
770; P7-NEXT:    lxvw4x vs0, 0, r3
771; P7-NEXT:    xxspltw v2, vs0, 3
772; P7-NEXT:    blr
773;
774; P9-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
775; P9-AIX32:       # %bb.0: # %entry
776; P9-AIX32-NEXT:    addi r3, r3, 12
777; P9-AIX32-NEXT:    lxvwsx v2, 0, r3
778; P9-AIX32-NEXT:    blr
779;
780; P8-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
781; P8-AIX32:       # %bb.0: # %entry
782; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
783; P8-AIX32-NEXT:    xxspltw v2, vs0, 3
784; P8-AIX32-NEXT:    blr
785;
786; P7-AIX32-LABEL: adjusted_lxvwsx_v16i8_3:
787; P7-AIX32:       # %bb.0: # %entry
788; P7-AIX32-NEXT:    lxvw4x vs0, 0, r3
789; P7-AIX32-NEXT:    xxspltw v2, vs0, 3
790; P7-AIX32-NEXT:    blr
791  entry:
792    %0 = load <16 x i8>, <16 x i8>* %s, align 16
793    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
794    ret <16 x i8> %1
795}
796
797define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
798; P9-LABEL: unadjusted_lxvdsx:
799; P9:       # %bb.0: # %entry
800; P9-NEXT:    lxvdsx v2, 0, r3
801; P9-NEXT:    blr
802;
803; P8-LABEL: unadjusted_lxvdsx:
804; P8:       # %bb.0: # %entry
805; P8-NEXT:    lxvdsx v2, 0, r3
806; P8-NEXT:    blr
807;
808; P7-LABEL: unadjusted_lxvdsx:
809; P7:       # %bb.0: # %entry
810; P7-NEXT:    lxvdsx v2, 0, r3
811; P7-NEXT:    blr
812;
813; P9-AIX32-LABEL: unadjusted_lxvdsx:
814; P9-AIX32:       # %bb.0: # %entry
815; P9-AIX32-NEXT:    lwz r4, 0(r3)
816; P9-AIX32-NEXT:    stw r4, -16(r1)
817; P9-AIX32-NEXT:    lwz r3, 4(r3)
818; P9-AIX32-NEXT:    lxv vs1, -16(r1)
819; P9-AIX32-NEXT:    mtfprwz f0, r3
820; P9-AIX32-NEXT:    xxinsertw vs1, vs0, 4
821; P9-AIX32-NEXT:    xxmrghd v2, vs1, vs1
822; P9-AIX32-NEXT:    blr
823;
824; P8-AIX32-LABEL: unadjusted_lxvdsx:
825; P8-AIX32:       # %bb.0: # %entry
826; P8-AIX32-NEXT:    lwz r5, 4(r3)
827; P8-AIX32-NEXT:    lwz r4, L..C3(r2) # %const.0
828; P8-AIX32-NEXT:    stw r5, -32(r1)
829; P8-AIX32-NEXT:    lwz r3, 0(r3)
830; P8-AIX32-NEXT:    lxvw4x v2, 0, r4
831; P8-AIX32-NEXT:    addi r4, r1, -16
832; P8-AIX32-NEXT:    stw r3, -16(r1)
833; P8-AIX32-NEXT:    addi r3, r1, -32
834; P8-AIX32-NEXT:    lxvw4x v3, 0, r3
835; P8-AIX32-NEXT:    lxvw4x v4, 0, r4
836; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
837; P8-AIX32-NEXT:    xxmrghd v2, v2, v2
838; P8-AIX32-NEXT:    blr
839;
840; P7-AIX32-LABEL: unadjusted_lxvdsx:
841; P7-AIX32:       # %bb.0: # %entry
842; P7-AIX32-NEXT:    lwz r5, 4(r3)
843; P7-AIX32-NEXT:    lwz r4, L..C3(r2) # %const.0
844; P7-AIX32-NEXT:    stw r5, -32(r1)
845; P7-AIX32-NEXT:    lwz r3, 0(r3)
846; P7-AIX32-NEXT:    lxvw4x v2, 0, r4
847; P7-AIX32-NEXT:    addi r4, r1, -16
848; P7-AIX32-NEXT:    stw r3, -16(r1)
849; P7-AIX32-NEXT:    addi r3, r1, -32
850; P7-AIX32-NEXT:    lxvw4x v3, 0, r3
851; P7-AIX32-NEXT:    lxvw4x v4, 0, r4
852; P7-AIX32-NEXT:    vperm v2, v4, v3, v2
853; P7-AIX32-NEXT:    xxmrghd v2, v2, v2
854; P7-AIX32-NEXT:    blr
855  entry:
856    %0 = bitcast i64* %s to <8 x i8>*
857    %1 = load <8 x i8>, <8 x i8>* %0, align 8
858    %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
859    ret <16 x i8> %2
860}
861
862define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
863; P9-LABEL: unadjusted_lxvdsx_v16i8:
864; P9:       # %bb.0: # %entry
865; P9-NEXT:    lxvdsx v2, 0, r3
866; P9-NEXT:    blr
867;
868; P8-LABEL: unadjusted_lxvdsx_v16i8:
869; P8:       # %bb.0: # %entry
870; P8-NEXT:    lxvdsx v2, 0, r3
871; P8-NEXT:    blr
872;
873; P7-LABEL: unadjusted_lxvdsx_v16i8:
874; P7:       # %bb.0: # %entry
875; P7-NEXT:    lxvdsx v2, 0, r3
876; P7-NEXT:    blr
877;
878; P9-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
879; P9-AIX32:       # %bb.0: # %entry
880; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
881; P9-AIX32-NEXT:    blr
882;
883; P8-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
884; P8-AIX32:       # %bb.0: # %entry
885; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
886; P8-AIX32-NEXT:    blr
887;
888; P7-AIX32-LABEL: unadjusted_lxvdsx_v16i8:
889; P7-AIX32:       # %bb.0: # %entry
890; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
891; P7-AIX32-NEXT:    blr
892  entry:
893    %0 = load <16 x i8>, <16 x i8>* %s, align 16
894    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
895    ret <16 x i8> %1
896}
897
898define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
899; P9-LABEL: adjusted_lxvdsx_v16i8:
900; P9:       # %bb.0: # %entry
901; P9-NEXT:    addi r3, r3, 8
902; P9-NEXT:    lxvdsx v2, 0, r3
903; P9-NEXT:    blr
904;
905; P8-LABEL: adjusted_lxvdsx_v16i8:
906; P8:       # %bb.0: # %entry
907; P8-NEXT:    addi r3, r3, 8
908; P8-NEXT:    lxvdsx v2, 0, r3
909; P8-NEXT:    blr
910;
911; P7-LABEL: adjusted_lxvdsx_v16i8:
912; P7:       # %bb.0: # %entry
913; P7-NEXT:    addi r3, r3, 8
914; P7-NEXT:    lxvdsx v2, 0, r3
915; P7-NEXT:    blr
916;
917; P9-AIX32-LABEL: adjusted_lxvdsx_v16i8:
918; P9-AIX32:       # %bb.0: # %entry
919; P9-AIX32-NEXT:    addi r3, r3, 8
920; P9-AIX32-NEXT:    lxvdsx v2, 0, r3
921; P9-AIX32-NEXT:    blr
922;
923; P8-AIX32-LABEL: adjusted_lxvdsx_v16i8:
924; P8-AIX32:       # %bb.0: # %entry
925; P8-AIX32-NEXT:    addi r3, r3, 8
926; P8-AIX32-NEXT:    lxvdsx v2, 0, r3
927; P8-AIX32-NEXT:    blr
928;
929; P7-AIX32-LABEL: adjusted_lxvdsx_v16i8:
930; P7-AIX32:       # %bb.0: # %entry
931; P7-AIX32-NEXT:    addi r3, r3, 8
932; P7-AIX32-NEXT:    lxvdsx v2, 0, r3
933; P7-AIX32-NEXT:    blr
934  entry:
935    %0 = load <16 x i8>, <16 x i8>* %s, align 16
936    %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
937    ret <16 x i8> %1
938}
939
940define <8 x i16> @test_unaligned_v8i16(i16* %Ptr) {
941; P9-LABEL: test_unaligned_v8i16:
942; P9:       # %bb.0: # %entry
943; P9-NEXT:    addi r3, r3, 6
944; P9-NEXT:    lxsihzx v2, 0, r3
945; P9-NEXT:    vsplth v2, v2, 3
946; P9-NEXT:    blr
947;
948; P8-LABEL: test_unaligned_v8i16:
949; P8:       # %bb.0: # %entry
950; P8-NEXT:    lhz r3, 6(r3)
951; P8-NEXT:    mtvsrwz v2, r3
952; P8-NEXT:    vsplth v2, v2, 3
953; P8-NEXT:    blr
954;
955; P7-LABEL: test_unaligned_v8i16:
956; P7:       # %bb.0: # %entry
957; P7-NEXT:    li r4, 1
958; P7-NEXT:    addi r3, r3, 6
959; P7-NEXT:    lvx v2, 0, r3
960; P7-NEXT:    lvx v3, r4, r3
961; P7-NEXT:    lvsl v4, 0, r3
962; P7-NEXT:    vperm v2, v2, v3, v4
963; P7-NEXT:    vsplth v2, v2, 0
964; P7-NEXT:    blr
965;
966; P9-AIX32-LABEL: test_unaligned_v8i16:
967; P9-AIX32:       # %bb.0: # %entry
968; P9-AIX32-NEXT:    addi r3, r3, 6
969; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
970; P9-AIX32-NEXT:    vsplth v2, v2, 3
971; P9-AIX32-NEXT:    blr
972;
973; P8-AIX32-LABEL: test_unaligned_v8i16:
974; P8-AIX32:       # %bb.0: # %entry
975; P8-AIX32-NEXT:    lhz r3, 6(r3)
976; P8-AIX32-NEXT:    mtvsrwz v2, r3
977; P8-AIX32-NEXT:    vsplth v2, v2, 3
978; P8-AIX32-NEXT:    blr
979;
980; P7-AIX32-LABEL: test_unaligned_v8i16:
981; P7-AIX32:       # %bb.0: # %entry
982; P7-AIX32-NEXT:    li r4, 1
983; P7-AIX32-NEXT:    addi r3, r3, 6
984; P7-AIX32-NEXT:    lvx v2, 0, r3
985; P7-AIX32-NEXT:    lvx v3, r4, r3
986; P7-AIX32-NEXT:    lvsl v4, 0, r3
987; P7-AIX32-NEXT:    vperm v2, v2, v3, v4
988; P7-AIX32-NEXT:    vsplth v2, v2, 0
989; P7-AIX32-NEXT:    blr
990entry:
991  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 3
992  %0 = load i16, i16* %add.ptr, align 16
993  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
994  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
995  ret <8 x i16> %splat.splat
996}
997
998define <16 x i8> @test_unaligned_v16i8(i8* %Ptr) {
999; P9-LABEL: test_unaligned_v16i8:
1000; P9:       # %bb.0: # %entry
1001; P9-NEXT:    addi r3, r3, 3
1002; P9-NEXT:    lxsibzx v2, 0, r3
1003; P9-NEXT:    vspltb v2, v2, 7
1004; P9-NEXT:    blr
1005;
1006; P8-LABEL: test_unaligned_v16i8:
1007; P8:       # %bb.0: # %entry
1008; P8-NEXT:    lbz r3, 3(r3)
1009; P8-NEXT:    mtvsrwz v2, r3
1010; P8-NEXT:    vspltb v2, v2, 7
1011; P8-NEXT:    blr
1012;
1013; P7-LABEL: test_unaligned_v16i8:
1014; P7:       # %bb.0: # %entry
1015; P7-NEXT:    addi r3, r3, 3
1016; P7-NEXT:    lvsl v2, 0, r3
1017; P7-NEXT:    lvx v3, 0, r3
1018; P7-NEXT:    vperm v2, v3, v3, v2
1019; P7-NEXT:    vspltb v2, v2, 0
1020; P7-NEXT:    blr
1021;
1022; P9-AIX32-LABEL: test_unaligned_v16i8:
1023; P9-AIX32:       # %bb.0: # %entry
1024; P9-AIX32-NEXT:    addi r3, r3, 3
1025; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1026; P9-AIX32-NEXT:    vspltb v2, v2, 7
1027; P9-AIX32-NEXT:    blr
1028;
1029; P8-AIX32-LABEL: test_unaligned_v16i8:
1030; P8-AIX32:       # %bb.0: # %entry
1031; P8-AIX32-NEXT:    lbz r3, 3(r3)
1032; P8-AIX32-NEXT:    mtvsrwz v2, r3
1033; P8-AIX32-NEXT:    vspltb v2, v2, 7
1034; P8-AIX32-NEXT:    blr
1035;
1036; P7-AIX32-LABEL: test_unaligned_v16i8:
1037; P7-AIX32:       # %bb.0: # %entry
1038; P7-AIX32-NEXT:    addi r3, r3, 3
1039; P7-AIX32-NEXT:    lvsl v2, 0, r3
1040; P7-AIX32-NEXT:    lvx v3, 0, r3
1041; P7-AIX32-NEXT:    vperm v2, v3, v3, v2
1042; P7-AIX32-NEXT:    vspltb v2, v2, 0
1043; P7-AIX32-NEXT:    blr
1044entry:
1045  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 3
1046  %0 = load i8, i8* %add.ptr, align 16
1047  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1048  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1049  ret <16 x i8> %splat.splat
1050}
1051
1052define <8 x i16> @test_aligned_v8i16_1(i16* %Ptr) {
1053; P9-LABEL: test_aligned_v8i16_1:
1054; P9:       # %bb.0: # %entry
1055; P9-NEXT:    lxsihzx v2, 0, r3
1056; P9-NEXT:    vsplth v2, v2, 3
1057; P9-NEXT:    blr
1058;
1059; P8-LABEL: test_aligned_v8i16_1:
1060; P8:       # %bb.0: # %entry
1061; P8-NEXT:    lvx v2, 0, r3
1062; P8-NEXT:    vsplth v2, v2, 7
1063; P8-NEXT:    blr
1064;
1065; P7-LABEL: test_aligned_v8i16_1:
1066; P7:       # %bb.0: # %entry
1067; P7-NEXT:    lvx v2, 0, r3
1068; P7-NEXT:    vsplth v2, v2, 0
1069; P7-NEXT:    blr
1070;
1071; P9-AIX32-LABEL: test_aligned_v8i16_1:
1072; P9-AIX32:       # %bb.0: # %entry
1073; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1074; P9-AIX32-NEXT:    vsplth v2, v2, 3
1075; P9-AIX32-NEXT:    blr
1076;
1077; P8-AIX32-LABEL: test_aligned_v8i16_1:
1078; P8-AIX32:       # %bb.0: # %entry
1079; P8-AIX32-NEXT:    lvx v2, 0, r3
1080; P8-AIX32-NEXT:    vsplth v2, v2, 0
1081; P8-AIX32-NEXT:    blr
1082;
1083; P7-AIX32-LABEL: test_aligned_v8i16_1:
1084; P7-AIX32:       # %bb.0: # %entry
1085; P7-AIX32-NEXT:    lvx v2, 0, r3
1086; P7-AIX32-NEXT:    vsplth v2, v2, 0
1087; P7-AIX32-NEXT:    blr
1088entry:
1089  %0 = load i16, i16* %Ptr, align 16
1090  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1091  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1092  ret <8 x i16> %splat.splat
1093}
1094
1095define <8 x i16> @test_aligned_v8i16_2(i16* %Ptr) {
1096; P9-LABEL: test_aligned_v8i16_2:
1097; P9:       # %bb.0: # %entry
1098; P9-NEXT:    addi r3, r3, 32
1099; P9-NEXT:    lxsihzx v2, 0, r3
1100; P9-NEXT:    vsplth v2, v2, 3
1101; P9-NEXT:    blr
1102;
1103; P8-LABEL: test_aligned_v8i16_2:
1104; P8:       # %bb.0: # %entry
1105; P8-NEXT:    addi r3, r3, 32
1106; P8-NEXT:    lvx v2, 0, r3
1107; P8-NEXT:    vsplth v2, v2, 7
1108; P8-NEXT:    blr
1109;
1110; P7-LABEL: test_aligned_v8i16_2:
1111; P7:       # %bb.0: # %entry
1112; P7-NEXT:    addi r3, r3, 32
1113; P7-NEXT:    lvx v2, 0, r3
1114; P7-NEXT:    vsplth v2, v2, 0
1115; P7-NEXT:    blr
1116;
1117; P9-AIX32-LABEL: test_aligned_v8i16_2:
1118; P9-AIX32:       # %bb.0: # %entry
1119; P9-AIX32-NEXT:    addi r3, r3, 32
1120; P9-AIX32-NEXT:    lxsihzx v2, 0, r3
1121; P9-AIX32-NEXT:    vsplth v2, v2, 3
1122; P9-AIX32-NEXT:    blr
1123;
1124; P8-AIX32-LABEL: test_aligned_v8i16_2:
1125; P8-AIX32:       # %bb.0: # %entry
1126; P8-AIX32-NEXT:    addi r3, r3, 32
1127; P8-AIX32-NEXT:    lvx v2, 0, r3
1128; P8-AIX32-NEXT:    vsplth v2, v2, 0
1129; P8-AIX32-NEXT:    blr
1130;
1131; P7-AIX32-LABEL: test_aligned_v8i16_2:
1132; P7-AIX32:       # %bb.0: # %entry
1133; P7-AIX32-NEXT:    addi r3, r3, 32
1134; P7-AIX32-NEXT:    lvx v2, 0, r3
1135; P7-AIX32-NEXT:    vsplth v2, v2, 0
1136; P7-AIX32-NEXT:    blr
1137entry:
1138  %add.ptr = getelementptr inbounds i16, i16* %Ptr, i64 16
1139  %0 = load i16, i16* %add.ptr, align 16
1140  %splat.splatinsert = insertelement <8 x i16> poison, i16 %0, i32 0
1141  %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> poison, <8 x i32> zeroinitializer
1142  ret <8 x i16> %splat.splat
1143}
1144
1145define <16 x i8> @test_aligned_v16i8_1(i8* %Ptr) {
1146; P9-LABEL: test_aligned_v16i8_1:
1147; P9:       # %bb.0: # %entry
1148; P9-NEXT:    lxsibzx v2, 0, r3
1149; P9-NEXT:    vspltb v2, v2, 7
1150; P9-NEXT:    blr
1151;
1152; P8-LABEL: test_aligned_v16i8_1:
1153; P8:       # %bb.0: # %entry
1154; P8-NEXT:    lvx v2, 0, r3
1155; P8-NEXT:    vspltb v2, v2, 15
1156; P8-NEXT:    blr
1157;
1158; P7-LABEL: test_aligned_v16i8_1:
1159; P7:       # %bb.0: # %entry
1160; P7-NEXT:    lvx v2, 0, r3
1161; P7-NEXT:    vspltb v2, v2, 0
1162; P7-NEXT:    blr
1163;
1164; P9-AIX32-LABEL: test_aligned_v16i8_1:
1165; P9-AIX32:       # %bb.0: # %entry
1166; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1167; P9-AIX32-NEXT:    vspltb v2, v2, 7
1168; P9-AIX32-NEXT:    blr
1169;
1170; P8-AIX32-LABEL: test_aligned_v16i8_1:
1171; P8-AIX32:       # %bb.0: # %entry
1172; P8-AIX32-NEXT:    lvx v2, 0, r3
1173; P8-AIX32-NEXT:    vspltb v2, v2, 0
1174; P8-AIX32-NEXT:    blr
1175;
1176; P7-AIX32-LABEL: test_aligned_v16i8_1:
1177; P7-AIX32:       # %bb.0: # %entry
1178; P7-AIX32-NEXT:    lvx v2, 0, r3
1179; P7-AIX32-NEXT:    vspltb v2, v2, 0
1180; P7-AIX32-NEXT:    blr
1181entry:
1182  %0 = load i8, i8* %Ptr, align 16
1183  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1184  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1185  ret <16 x i8> %splat.splat
1186}
1187
1188define <16 x i8> @test_aligned_v16i8_2(i8* %Ptr) {
1189; P9-LABEL: test_aligned_v16i8_2:
1190; P9:       # %bb.0: # %entry
1191; P9-NEXT:    addi r3, r3, 16
1192; P9-NEXT:    lxsibzx v2, 0, r3
1193; P9-NEXT:    vspltb v2, v2, 7
1194; P9-NEXT:    blr
1195;
1196; P8-LABEL: test_aligned_v16i8_2:
1197; P8:       # %bb.0: # %entry
1198; P8-NEXT:    addi r3, r3, 16
1199; P8-NEXT:    lvx v2, 0, r3
1200; P8-NEXT:    vspltb v2, v2, 15
1201; P8-NEXT:    blr
1202;
1203; P7-LABEL: test_aligned_v16i8_2:
1204; P7:       # %bb.0: # %entry
1205; P7-NEXT:    addi r3, r3, 16
1206; P7-NEXT:    lvx v2, 0, r3
1207; P7-NEXT:    vspltb v2, v2, 0
1208; P7-NEXT:    blr
1209;
1210; P9-AIX32-LABEL: test_aligned_v16i8_2:
1211; P9-AIX32:       # %bb.0: # %entry
1212; P9-AIX32-NEXT:    addi r3, r3, 16
1213; P9-AIX32-NEXT:    lxsibzx v2, 0, r3
1214; P9-AIX32-NEXT:    vspltb v2, v2, 7
1215; P9-AIX32-NEXT:    blr
1216;
1217; P8-AIX32-LABEL: test_aligned_v16i8_2:
1218; P8-AIX32:       # %bb.0: # %entry
1219; P8-AIX32-NEXT:    addi r3, r3, 16
1220; P8-AIX32-NEXT:    lvx v2, 0, r3
1221; P8-AIX32-NEXT:    vspltb v2, v2, 0
1222; P8-AIX32-NEXT:    blr
1223;
1224; P7-AIX32-LABEL: test_aligned_v16i8_2:
1225; P7-AIX32:       # %bb.0: # %entry
1226; P7-AIX32-NEXT:    addi r3, r3, 16
1227; P7-AIX32-NEXT:    lvx v2, 0, r3
1228; P7-AIX32-NEXT:    vspltb v2, v2, 0
1229; P7-AIX32-NEXT:    blr
1230entry:
1231  %add.ptr = getelementptr inbounds i8, i8* %Ptr, i64 16
1232  %0 = load i8, i8* %add.ptr, align 16
1233  %splat.splatinsert = insertelement <16 x i8> poison, i8 %0, i32 0
1234  %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> poison, <16 x i32> zeroinitializer
1235  ret <16 x i8> %splat.splat
1236}
1237
1238; The following test case should not produce a load and splat node,
1239; as we cannot handle extending loads (from f32 to f64), and this test
1240; shows that there are multiple uses of the extending load (other than
1241; a build vector node). `lxvdsx` should not be produced in this case.
1242define <2 x double> @test_v2f64_multiple_use(float* nocapture readonly %a, double* nocapture %b, double* nocapture %c) {
1243; P9-LABEL: test_v2f64_multiple_use:
1244; P9:       # %bb.0: # %entry
1245; P9-NEXT:    lfs f0, 0(r3)
1246; P9-NEXT:    xxspltd v2, vs0, 0
1247; P9-NEXT:    lfd f1, 0(r4)
1248; P9-NEXT:    xsadddp f1, f1, f0
1249; P9-NEXT:    stfd f1, 0(r4)
1250; P9-NEXT:    lfd f1, 0(r5)
1251; P9-NEXT:    xsadddp f1, f1, f0
1252; P9-NEXT:    stfd f1, 0(r5)
1253; P9-NEXT:    blr
1254;
1255; P8-LABEL: test_v2f64_multiple_use:
1256; P8:       # %bb.0: # %entry
1257; P8-NEXT:    lfs f0, 0(r3)
1258; P8-NEXT:    lfd f1, 0(r4)
1259; P8-NEXT:    xsadddp f1, f1, f0
1260; P8-NEXT:    xxspltd v2, vs0, 0
1261; P8-NEXT:    stfd f1, 0(r4)
1262; P8-NEXT:    lfd f1, 0(r5)
1263; P8-NEXT:    xsadddp f1, f1, f0
1264; P8-NEXT:    stfd f1, 0(r5)
1265; P8-NEXT:    blr
1266;
1267; P7-LABEL: test_v2f64_multiple_use:
1268; P7:       # %bb.0: # %entry
1269; P7-NEXT:    lfs f0, 0(r3)
1270; P7-NEXT:    lfd f1, 0(r4)
1271; P7-NEXT:    xsadddp f1, f1, f0
1272; P7-NEXT:    xxspltd v2, vs0, 0
1273; P7-NEXT:    stfd f1, 0(r4)
1274; P7-NEXT:    lfd f1, 0(r5)
1275; P7-NEXT:    xsadddp f1, f1, f0
1276; P7-NEXT:    stfd f1, 0(r5)
1277; P7-NEXT:    blr
1278;
1279; P9-AIX32-LABEL: test_v2f64_multiple_use:
1280; P9-AIX32:       # %bb.0: # %entry
1281; P9-AIX32-NEXT:    lfs f0, 0(r3)
1282; P9-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1283; P9-AIX32-NEXT:    lfd f1, 0(r4)
1284; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1285; P9-AIX32-NEXT:    stfd f1, 0(r4)
1286; P9-AIX32-NEXT:    lfd f1, 0(r5)
1287; P9-AIX32-NEXT:    xsadddp f1, f1, f0
1288; P9-AIX32-NEXT:    stfd f1, 0(r5)
1289; P9-AIX32-NEXT:    blr
1290;
1291; P8-AIX32-LABEL: test_v2f64_multiple_use:
1292; P8-AIX32:       # %bb.0: # %entry
1293; P8-AIX32-NEXT:    lfs f0, 0(r3)
1294; P8-AIX32-NEXT:    lfd f1, 0(r4)
1295; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1296; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1297; P8-AIX32-NEXT:    stfd f1, 0(r4)
1298; P8-AIX32-NEXT:    lfd f1, 0(r5)
1299; P8-AIX32-NEXT:    xsadddp f1, f1, f0
1300; P8-AIX32-NEXT:    stfd f1, 0(r5)
1301; P8-AIX32-NEXT:    blr
1302;
1303; P7-AIX32-LABEL: test_v2f64_multiple_use:
1304; P7-AIX32:       # %bb.0: # %entry
1305; P7-AIX32-NEXT:    lfs f0, 0(r3)
1306; P7-AIX32-NEXT:    lfd f1, 0(r4)
1307; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1308; P7-AIX32-NEXT:    xxmrghd v2, vs0, vs0
1309; P7-AIX32-NEXT:    stfd f1, 0(r4)
1310; P7-AIX32-NEXT:    lfd f1, 0(r5)
1311; P7-AIX32-NEXT:    xsadddp f1, f1, f0
1312; P7-AIX32-NEXT:    stfd f1, 0(r5)
1313; P7-AIX32-NEXT:    blr
1314entry:
1315  %0 = load float, float* %a, align 4
1316  %conv = fpext float %0 to double
1317  %1 = load double, double* %b, align 8
1318  %add = fadd double %1, %conv
1319  store double %add, double* %b, align 8
1320  %2 = load double, double* %c, align 8
1321  %add2 = fadd double %2, %conv
1322  store double %add2, double* %c, align 8
1323  %vecinit = insertelement <2 x double> undef, double %conv, i64 0
1324  %vecinit5 = shufflevector <2 x double> %vecinit, <2 x double> poison, <2 x i32> zeroinitializer
1325  ret <2 x double> %vecinit5
1326}
1327