1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-- | FileCheck %s
3
4declare i8 @llvm.fshl.i8(i8, i8, i8)
5declare i16 @llvm.fshl.i16(i16, i16, i16)
6declare i32 @llvm.fshl.i32(i32, i32, i32)
7declare i64 @llvm.fshl.i64(i64, i64, i64)
8declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
9
10declare i8 @llvm.fshr.i8(i8, i8, i8)
11declare i16 @llvm.fshr.i16(i16, i16, i16)
12declare i32 @llvm.fshr.i32(i32, i32, i32)
13declare i64 @llvm.fshr.i64(i64, i64, i64)
14declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
15
16; When first 2 operands match, it's a rotate.
17
18define i8 @rotl_i8_const_shift(i8 %x) {
19; CHECK-LABEL: rotl_i8_const_shift:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    rotlwi 4, 3, 27
22; CHECK-NEXT:    rlwimi 4, 3, 3, 0, 28
23; CHECK-NEXT:    mr 3, 4
24; CHECK-NEXT:    blr
25  %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
26  ret i8 %f
27}
28
29define i64 @rotl_i64_const_shift(i64 %x) {
30; CHECK-LABEL: rotl_i64_const_shift:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    rotldi 3, 3, 3
33; CHECK-NEXT:    blr
34  %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
35  ret i64 %f
36}
37
38; When first 2 operands match, it's a rotate (by variable amount).
39
40define i16 @rotl_i16(i16 %x, i16 %z) {
41; CHECK-LABEL: rotl_i16:
42; CHECK:       # %bb.0:
43; CHECK-NEXT:    neg 5, 4
44; CHECK-NEXT:    clrlwi 6, 3, 16
45; CHECK-NEXT:    clrlwi 4, 4, 28
46; CHECK-NEXT:    clrlwi 5, 5, 28
47; CHECK-NEXT:    slw 3, 3, 4
48; CHECK-NEXT:    srw 4, 6, 5
49; CHECK-NEXT:    or 3, 3, 4
50; CHECK-NEXT:    blr
51  %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
52  ret i16 %f
53}
54
55define i32 @rotl_i32(i32 %x, i32 %z) {
56; CHECK-LABEL: rotl_i32:
57; CHECK:       # %bb.0:
58; CHECK-NEXT:    rotlw 3, 3, 4
59; CHECK-NEXT:    blr
60  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
61  ret i32 %f
62}
63
64define i64 @rotl_i64(i64 %x, i64 %z) {
65; CHECK-LABEL: rotl_i64:
66; CHECK:       # %bb.0:
67; CHECK-NEXT:    rotld 3, 3, 4
68; CHECK-NEXT:    blr
69  %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
70  ret i64 %f
71}
72
73; Vector rotate.
74
75define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
76; CHECK-LABEL: rotl_v4i32:
77; CHECK:       # %bb.0:
78; CHECK-NEXT:    vrlw 2, 2, 3
79; CHECK-NEXT:    blr
80  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
81  ret <4 x i32> %f
82}
83
84; Vector rotate by constant splat amount.
85
86define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) {
87; CHECK-LABEL: rotl_v4i32_const_shift:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vspltisw 3, 3
90; CHECK-NEXT:    vrlw 2, 2, 3
91; CHECK-NEXT:    blr
92  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
93  ret <4 x i32> %f
94}
95
96; Repeat everything for funnel shift right.
97
98define i8 @rotr_i8_const_shift(i8 %x) {
99; CHECK-LABEL: rotr_i8_const_shift:
100; CHECK:       # %bb.0:
101; CHECK-NEXT:    rotlwi 4, 3, 29
102; CHECK-NEXT:    rlwimi 4, 3, 5, 0, 26
103; CHECK-NEXT:    mr 3, 4
104; CHECK-NEXT:    blr
105  %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
106  ret i8 %f
107}
108
109define i32 @rotr_i32_const_shift(i32 %x) {
110; CHECK-LABEL: rotr_i32_const_shift:
111; CHECK:       # %bb.0:
112; CHECK-NEXT:    rotlwi 3, 3, 29
113; CHECK-NEXT:    blr
114  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
115  ret i32 %f
116}
117
118; When first 2 operands match, it's a rotate (by variable amount).
119
120define i16 @rotr_i16(i16 %x, i16 %z) {
121; CHECK-LABEL: rotr_i16:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    neg 5, 4
124; CHECK-NEXT:    clrlwi 6, 3, 16
125; CHECK-NEXT:    clrlwi 4, 4, 28
126; CHECK-NEXT:    clrlwi 5, 5, 28
127; CHECK-NEXT:    srw 4, 6, 4
128; CHECK-NEXT:    slw 3, 3, 5
129; CHECK-NEXT:    or 3, 3, 4
130; CHECK-NEXT:    blr
131  %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
132  ret i16 %f
133}
134
135define i32 @rotr_i32(i32 %x, i32 %z) {
136; CHECK-LABEL: rotr_i32:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    neg 4, 4
139; CHECK-NEXT:    rotlw 3, 3, 4
140; CHECK-NEXT:    blr
141  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
142  ret i32 %f
143}
144
145define i64 @rotr_i64(i64 %x, i64 %z) {
146; CHECK-LABEL: rotr_i64:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    neg 4, 4
149; CHECK-NEXT:    rotld 3, 3, 4
150; CHECK-NEXT:    blr
151  %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
152  ret i64 %f
153}
154
155; Vector rotate.
156
157define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
158; CHECK-LABEL: rotr_v4i32:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    xxlxor 36, 36, 36
161; CHECK-NEXT:    vsubuwm 3, 4, 3
162; CHECK-NEXT:    vrlw 2, 2, 3
163; CHECK-NEXT:    blr
164  %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
165  ret <4 x i32> %f
166}
167
168; Vector rotate by constant splat amount.
169
170define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
171; CHECK-LABEL: rotr_v4i32_const_shift:
172; CHECK:       # %bb.0:
173; CHECK-NEXT:    vspltisw 3, -16
174; CHECK-NEXT:    vspltisw 4, 13
175; CHECK-NEXT:    vsubuwm 3, 4, 3
176; CHECK-NEXT:    vrlw 2, 2, 3
177; CHECK-NEXT:    blr
178  %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
179  ret <4 x i32> %f
180}
181
182define i32 @rotl_i32_shift_by_bitwidth(i32 %x) {
183; CHECK-LABEL: rotl_i32_shift_by_bitwidth:
184; CHECK:       # %bb.0:
185; CHECK-NEXT:    blr
186  %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 32)
187  ret i32 %f
188}
189
190define i32 @rotr_i32_shift_by_bitwidth(i32 %x) {
191; CHECK-LABEL: rotr_i32_shift_by_bitwidth:
192; CHECK:       # %bb.0:
193; CHECK-NEXT:    blr
194  %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 32)
195  ret i32 %f
196}
197
198define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) {
199; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
200; CHECK:       # %bb.0:
201; CHECK-NEXT:    blr
202  %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
203  ret <4 x i32> %f
204}
205
206define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) {
207; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
208; CHECK:       # %bb.0:
209; CHECK-NEXT:    blr
210  %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
211  ret <4 x i32> %f
212}
213
214