1; NOTE: This test ensures that, for both Big and Little Endian cases, a set of
2; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld
3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
4; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
5; RUN: | FileCheck %s -check-prefix=CHECK-LE
6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
7; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
8; RUN: | FileCheck %s -check-prefix=CHECK-BE
9; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
10; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff < %s \
11; RUN: | FileCheck %s -check-prefix=CHECK-BE
12; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
13; RUN: -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff < %s \
14; RUN: | FileCheck %s -check-prefix=CHECK-BE-AIX-32
15define dso_local <4 x float> @vector_gatherf(float* nocapture readonly %a,
16float* nocapture readonly %b, float* nocapture readonly %c,
17float* nocapture readonly %d) {
18; C code from which this IR test case was generated:
19; vector float test(float *a, float *b, float *c, float *d) {
20;  return (vector float) { *a, *b, *c, *d };
21; }
22; CHECK-LE-LABEL: vector_gatherf:
23; CHECK-LE:       # %bb.0: # %entry
24; CHECK-LE-DAG:    lfiwzx f[[REG0:[0-9]+]], 0, r6
25; CHECK-LE-DAG:    lfiwzx f[[REG1:[0-9]+]], 0, r5
26; CHECK-LE-DAG:    lfiwzx f[[REG2:[0-9]+]], 0, r4
27; CHECK-LE-DAG:    lfiwzx f[[REG3:[0-9]+]], 0, r3
28; CHECK-LE-DAG:    xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]
29; CHECK-LE-DAG:    xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]
30; CHECK-LE-NEXT:   xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]
31; CHECK-LE-NEXT:   blr
32
33; CHECK-BE-LABEL: vector_gatherf:
34; CHECK-BE:       # %bb.0: # %entry
35; CHECK-BE-DAG:    lfiwzx f[[REG0:[0-9]+]], 0, r3
36; CHECK-BE-DAG:    lfiwzx f[[REG1:[0-9]+]], 0, r4
37; CHECK-BE-DAG:    lfiwzx f[[REG2:[0-9]+]], 0, r5
38; CHECK-BE-DAG:    lfiwzx f[[REG3:[0-9]+]], 0, r6
39; CHECK-BE-DAG:    xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]]
40; CHECK-BE-DAG:    xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]]
41; CHECK-BE-NEXT:   xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]]
42; CHECK-BE-NEXT:   blr
43
44; CHECK-BE-AIX-32-LABEL: vector_gatherf:
45; CHECK-BE-AIX-32-LABEL: # %bb.0: # %entry
46; CHECK-BE-AIX-32-DAG: lfs f[[REG0:[0-9]+]]
47; CHECK-BE-AIX-32-DAG: lfs f[[REG1:[0-9]+]]
48; CHECK-BE-AIX-32-DAG: lfs f[[REG2:[0-9]+]]
49; CHECK-BE-AIX-32-DAG: lfs f[[REG3:[0-9]+]]
50; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG0:[0-9]+]], f[[REG0]]
51; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG1:[0-9]+]], f[[REG1]]
52; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG2:[0-9]+]], f[[REG2]]
53; CHECK-BE-AIX-32-DAG: xscvdpspn v[[VREG0:[0-9]+]], f[[REG3]]
54; CHECK-BE-AIX-32-DAG: vmrgow v[[VREG1]], v[[VREG0]], v[[VREG1]]
55; CHECK-BE-AIX-32-DAG: vmrgow v[[VREG0]], v[[VREG2]], v[[VREG0]]
56; CHECK-BE-AIX-32-NEXT: xxmrghd v[[VREG1]], v[[VREG0]], v[[VREG1]]
57; CHECK-BE-AIX-32-NEXT: blr
58entry:
59  %0 = load float, float* %a, align 4
60  %vecinit = insertelement <4 x float> undef, float %0, i32 0
61  %1 = load float, float* %b, align 4
62  %vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 1
63  %2 = load float, float* %c, align 4
64  %vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 2
65  %3 = load float, float* %d, align 4
66  %vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 3
67  ret <4 x float> %vecinit3
68}
69
70