1; FIXME: FastISel currently returns false if it hits code that uses VSX
2; registers and with -fast-isel-abort=1 turned on the test case will then fail.
3; When fastisel better supports VSX fix up this test case.
4;
5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s
7; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
8
9;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
10;; to SelectionDAG in some cases.
11
12; Test sitofp
13
14define void @sitofp_single_i64(i64 %a, float %b) nounwind {
15entry:
16; CHECK: sitofp_single_i64
17; PPC970: sitofp_single_i64
18  %b.addr = alloca float, align 4
19  %conv = sitofp i64 %a to float
20; CHECK: std
21; CHECK: lfd
22; CHECK: fcfids
23; PPC970: std
24; PPC970: lfd
25; PPC970: fcfid
26; PPC970: frsp
27  store float %conv, float* %b.addr, align 4
28  ret void
29}
30
31define void @sitofp_single_i32(i32 %a, float %b) nounwind {
32entry:
33; CHECK: sitofp_single_i32
34; PPC970: sitofp_single_i32
35  %b.addr = alloca float, align 4
36  %conv = sitofp i32 %a to float
37; CHECK: std
38; CHECK-NEXT: li
39; CHECK-NEXT: lfiwax
40; CHECK-NEXT: fcfids
41; PPC970: std
42; PPC970: lfd
43; PPC970: fcfid
44; PPC970: frsp
45  store float %conv, float* %b.addr, align 4
46  ret void
47}
48
49define void @sitofp_single_i16(i16 %a, float %b) nounwind {
50entry:
51; CHECK: sitofp_single_i16
52; PPC970: sitofp_single_i16
53  %b.addr = alloca float, align 4
54  %conv = sitofp i16 %a to float
55; CHECK: extsh
56; CHECK: std
57; CHECK: lfd
58; CHECK: fcfids
59; PPC970: extsh
60; PPC970: std
61; PPC970: lfd
62; PPC970: fcfid
63; PPC970: frsp
64  store float %conv, float* %b.addr, align 4
65  ret void
66}
67
68define void @sitofp_single_i8(i8 %a) nounwind {
69entry:
70; CHECK: sitofp_single_i8
71; PPC970: sitofp_single_i8
72  %b.addr = alloca float, align 4
73  %conv = sitofp i8 %a to float
74; CHECK: extsb
75; CHECK: std
76; CHECK: lfd
77; CHECK: fcfids
78; PPC970: extsb
79; PPC970: std
80; PPC970: lfd
81; PPC970: fcfid
82; PPC970: frsp
83  store float %conv, float* %b.addr, align 4
84  ret void
85}
86
87define void @sitofp_double_i32(i32 %a, double %b) nounwind {
88entry:
89; CHECK: sitofp_double_i32
90; PPC970: sitofp_double_i32
91  %b.addr = alloca double, align 8
92  %conv = sitofp i32 %a to double
93; CHECK: std
94; CHECK-NOT: ori
95; CHECK: li
96; CHECK-NOT: ori
97; CHECK: lfiwax
98; CHECK: fcfid
99; PPC970: std
100; PPC970: lfd
101; PPC970: fcfid
102  store double %conv, double* %b.addr, align 8
103  ret void
104}
105
106define void @sitofp_double_i64(i64 %a, double %b) nounwind {
107entry:
108; CHECK: sitofp_double_i64
109; PPC970: sitofp_double_i64
110  %b.addr = alloca double, align 8
111  %conv = sitofp i64 %a to double
112; CHECK: std
113; CHECK: lfd
114; CHECK: fcfid
115; PPC970: std
116; PPC970: lfd
117; PPC970: fcfid
118  store double %conv, double* %b.addr, align 8
119  ret void
120}
121
122define void @sitofp_double_i16(i16 %a, double %b) nounwind {
123entry:
124; CHECK: sitofp_double_i16
125; PPC970: sitofp_double_i16
126  %b.addr = alloca double, align 8
127  %conv = sitofp i16 %a to double
128; CHECK: extsh
129; CHECK: std
130; CHECK: lfd
131; CHECK: fcfid
132; PPC970: extsh
133; PPC970: std
134; PPC970: lfd
135; PPC970: fcfid
136  store double %conv, double* %b.addr, align 8
137  ret void
138}
139
140define void @sitofp_double_i8(i8 %a, double %b) nounwind {
141entry:
142; CHECK: sitofp_double_i8
143; PPC970: sitofp_double_i8
144  %b.addr = alloca double, align 8
145  %conv = sitofp i8 %a to double
146; CHECK: extsb
147; CHECK: std
148; CHECK: lfd
149; CHECK: fcfid
150; PPC970: extsb
151; PPC970: std
152; PPC970: lfd
153; PPC970: fcfid
154  store double %conv, double* %b.addr, align 8
155  ret void
156}
157
158; Test uitofp
159
160define void @uitofp_single_i64(i64 %a, float %b) nounwind {
161entry:
162; CHECK: uitofp_single_i64
163; PPC970: uitofp_single_i64
164  %b.addr = alloca float, align 4
165  %conv = uitofp i64 %a to float
166; CHECK: std
167; CHECK: lfd
168; CHECK: fcfidus
169; PPC970-NOT: fcfidus
170  store float %conv, float* %b.addr, align 4
171  ret void
172}
173
174define void @uitofp_single_i32(i32 %a, float %b) nounwind {
175entry:
176; CHECK: uitofp_single_i32
177; PPC970: uitofp_single_i32
178  %b.addr = alloca float, align 4
179  %conv = uitofp i32 %a to float
180; CHECK: std
181; CHECK-NOT: ori
182; CHECK: li
183; CHECK-NOT: ori
184; CHECK: lfiwzx
185; CHECK: fcfidus
186; PPC970-NOT: lfiwzx
187; PPC970-NOT: fcfidus
188  store float %conv, float* %b.addr, align 4
189  ret void
190}
191
192define void @uitofp_single_i16(i16 %a, float %b) nounwind {
193entry:
194; CHECK: uitofp_single_i16
195; PPC970: uitofp_single_i16
196  %b.addr = alloca float, align 4
197  %conv = uitofp i16 %a to float
198; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
199; CHECK: std
200; CHECK: lfd
201; CHECK: fcfidus
202; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
203; PPC970: std
204; PPC970: lfd
205; PPC970: fcfid
206; PPC970: frsp
207  store float %conv, float* %b.addr, align 4
208  ret void
209}
210
211define void @uitofp_single_i8(i8 %a) nounwind {
212entry:
213; CHECK: uitofp_single_i8
214; PPC970: uitofp_single_i8
215  %b.addr = alloca float, align 4
216  %conv = uitofp i8 %a to float
217; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
218; CHECK: std
219; CHECK: lfd
220; CHECK: fcfidus
221; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
222; PPC970: std
223; PPC970: lfd
224; PPC970: fcfid
225; PPC970: frsp
226  store float %conv, float* %b.addr, align 4
227  ret void
228}
229
230define void @uitofp_double_i64(i64 %a, double %b) nounwind {
231entry:
232; CHECK: uitofp_double_i64
233; PPC970: uitofp_double_i64
234  %b.addr = alloca double, align 8
235  %conv = uitofp i64 %a to double
236; CHECK: std
237; CHECK: lfd
238; CHECK: fcfidu
239; PPC970-NOT: fcfidu
240  store double %conv, double* %b.addr, align 8
241  ret void
242}
243
244define void @uitofp_double_i32(i32 %a, double %b) nounwind {
245entry:
246; CHECK: uitofp_double_i32
247; PPC970: uitofp_double_i32
248  %b.addr = alloca double, align 8
249  %conv = uitofp i32 %a to double
250; CHECK: std
251; CHECK-NEXT: li
252; CHECK-NEXT: lfiwzx
253; CHECK-NEXT: fcfidu
254; CHECKLE: fcfidu
255; PPC970-NOT: lfiwzx
256; PPC970-NOT: fcfidu
257  store double %conv, double* %b.addr, align 8
258  ret void
259}
260
261define void @uitofp_double_i16(i16 %a, double %b) nounwind {
262entry:
263; CHECK: uitofp_double_i16
264; PPC970: uitofp_double_i16
265  %b.addr = alloca double, align 8
266  %conv = uitofp i16 %a to double
267; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
268; CHECK: std
269; CHECK: lfd
270; CHECK: fcfidu
271; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
272; PPC970: std
273; PPC970: lfd
274; PPC970: fcfid
275  store double %conv, double* %b.addr, align 8
276  ret void
277}
278
279define void @uitofp_double_i8(i8 %a, double %b) nounwind {
280entry:
281; CHECK: uitofp_double_i8
282; PPC970: uitofp_double_i8
283  %b.addr = alloca double, align 8
284  %conv = uitofp i8 %a to double
285; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
286; CHECK: std
287; CHECK: lfd
288; CHECK: fcfidu
289; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
290; PPC970: std
291; PPC970: lfd
292; PPC970: fcfid
293  store double %conv, double* %b.addr, align 8
294  ret void
295}
296
297; Test fptosi
298
299define void @fptosi_float_i32(float %a) nounwind {
300entry:
301; CHECK: fptosi_float_i32
302; PPC970: fptosi_float_i32
303  %b.addr = alloca i32, align 4
304  %conv = fptosi float %a to i32
305; CHECK: fctiwz
306; CHECK: stfd
307; CHECK: lwa
308; PPC970: fctiwz
309; PPC970: stfd
310; PPC970: lwa
311  store i32 %conv, i32* %b.addr, align 4
312  ret void
313}
314
315define void @fptosi_float_i64(float %a) nounwind {
316entry:
317; CHECK: fptosi_float_i64
318; PPC970: fptosi_float_i64
319  %b.addr = alloca i64, align 4
320  %conv = fptosi float %a to i64
321; CHECK: fctidz
322; CHECK: stfd
323; CHECK: ld
324; PPC970: fctidz
325; PPC970: stfd
326; PPC970: ld
327  store i64 %conv, i64* %b.addr, align 4
328  ret void
329}
330
331define void @fptosi_double_i32(double %a) nounwind {
332entry:
333; CHECK: fptosi_double_i32
334; PPC970: fptosi_double_i32
335  %b.addr = alloca i32, align 8
336  %conv = fptosi double %a to i32
337; CHECK: fctiwz
338; CHECK: stfd
339; CHECK: lwa
340; PPC970: fctiwz
341; PPC970: stfd
342; PPC970: lwa
343  store i32 %conv, i32* %b.addr, align 8
344  ret void
345}
346
347define void @fptosi_double_i64(double %a) nounwind {
348entry:
349; CHECK: fptosi_double_i64
350; PPC970: fptosi_double_i64
351  %b.addr = alloca i64, align 8
352  %conv = fptosi double %a to i64
353; CHECK: fctidz
354; CHECK: stfd
355; CHECK: ld
356; PPC970: fctidz
357; PPC970: stfd
358; PPC970: ld
359  store i64 %conv, i64* %b.addr, align 8
360  ret void
361}
362
363; Test fptoui
364
365define void @fptoui_float_i32(float %a) nounwind {
366entry:
367; CHECK: fptoui_float_i32
368; PPC970: fptoui_float_i32
369  %b.addr = alloca i32, align 4
370  %conv = fptoui float %a to i32
371; CHECK: fctiwuz
372; CHECK: stfd
373; CHECK: lwz
374; PPC970: fctidz
375; PPC970: stfd
376; PPC970: lwz
377  store i32 %conv, i32* %b.addr, align 4
378  ret void
379}
380
381define void @fptoui_float_i64(float %a) nounwind {
382entry:
383; CHECK: fptoui_float_i64
384; PPC970: fptoui_float_i64
385  %b.addr = alloca i64, align 4
386  %conv = fptoui float %a to i64
387; CHECK: fctiduz
388; CHECK: stfd
389; CHECK: ld
390; PPC970-NOT: fctiduz
391  store i64 %conv, i64* %b.addr, align 4
392  ret void
393}
394
395define void @fptoui_double_i32(double %a) nounwind {
396entry:
397; CHECK: fptoui_double_i32
398; PPC970: fptoui_double_i32
399  %b.addr = alloca i32, align 8
400  %conv = fptoui double %a to i32
401; CHECK: fctiwuz
402; CHECK: stfd
403; CHECK: lwz
404; PPC970: fctidz
405; PPC970: stfd
406; PPC970: lwz
407  store i32 %conv, i32* %b.addr, align 8
408  ret void
409}
410
411define void @fptoui_double_i64(double %a) nounwind {
412entry:
413; CHECK: fptoui_double_i64
414; PPC970: fptoui_double_i64
415  %b.addr = alloca i64, align 8
416  %conv = fptoui double %a to i64
417; CHECK: fctiduz
418; CHECK: stfd
419; CHECK: ld
420; PPC970-NOT: fctiduz
421  store i64 %conv, i64* %b.addr, align 8
422  ret void
423}
424