1; XFAIL: *
2; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
4target datalayout = "E-m:e-i64:64-n32:64"
5target triple = "powerpc64-unknown-linux-gnu"
6
7; Function Attrs: nounwind readnone
8define zeroext i1 @test1(float %v1, float %v2) #0 {
9entry:
10  %cmp = fcmp oge float %v1, %v2
11  %cmp2 = fcmp ole float %v2, 0.000000e+00
12  %and5 = and i1 %cmp, %cmp2
13  ret i1 %and5
14
15; CHECK-LABEL: @test1
16; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
17; CHECK-DAG: li [[REG1:[0-9]+]], 1
18; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
19; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
20; CHECK: crnor
21; CHECK: crnor
22; CHECK: crnand [[REG4:[0-9]+]],
23; CHECK: isel 3, 0, [[REG1]], [[REG4]]
24; CHECK-NO-ISEL-LABEL: @test1
25; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
26; CHECK-NO-ISEL-NEXT: blr
27; CHECK-NO-ISEL-NEXT: [[TRUE]]
28; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
29; CHECK-NO-ISEL-NEXT: blr
30; CHECK: blr
31}
32
33; Function Attrs: nounwind readnone
34define zeroext i1 @test2(float %v1, float %v2) #0 {
35entry:
36  %cmp = fcmp oge float %v1, %v2
37  %cmp2 = fcmp ole float %v2, 0.000000e+00
38  %xor5 = xor i1 %cmp, %cmp2
39  ret i1 %xor5
40
41; CHECK-LABEL: @test2
42; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
43; CHECK-DAG: li [[REG1:[0-9]+]], 1
44; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
45; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
46; CHECK: crnor
47; CHECK: crnor
48; CHECK: creqv [[REG4:[0-9]+]],
49; CHECK: isel 3, 0, [[REG1]], [[REG4]]
50; CHECK: blr
51}
52
53; Function Attrs: nounwind readnone
54define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
55entry:
56  %cmp = fcmp oge float %v1, %v2
57  %cmp2 = fcmp ole float %v2, 0.000000e+00
58  %cmp4 = icmp ne i32 %x, -2
59  %and7 = and i1 %cmp2, %cmp4
60  %xor8 = xor i1 %cmp, %and7
61  ret i1 %xor8
62
63; CHECK-LABEL: @test3
64; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
65; CHECK-DAG: li [[REG1:[0-9]+]], 1
66; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
67; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
68; CHECK: crnor
69; CHECK: crnor
70; CHECK: crandc
71; CHECK: creqv [[REG4:[0-9]+]],
72; CHECK: isel 3, 0, [[REG1]], [[REG4]]
73; CHECK: blr
74}
75
76; Function Attrs: nounwind readnone
77define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 {
78entry:
79  %and8 = and i1 %v1, %v2
80  %or9 = or i1 %and8, %v3
81  ret i1 %or9
82
83; CHECK-DAG: @test4
84; CHECK: and [[REG1:[0-9]+]], 3, 4
85; CHECK: or 3, [[REG1]], 5
86; CHECK: blr
87}
88
89; Function Attrs: nounwind readnone
90define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
91entry:
92  %and6 = and i1 %v1, %v2
93  %cmp = icmp ne i32 %v3, -2
94  %or7 = or i1 %and6, %cmp
95  ret i1 %or7
96
97; CHECK-LABEL: @test5
98; CHECK-DAG: li [[NEG2:[0-9]+]], -2
99; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
100; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]]
101; CHECK-DAG: clrldi [[TRUNC:[0-9]+]], [[REG1]], 63
102; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]]
103; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5
104; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1
105; CHECK: or 3, [[TRUNC]], [[NE4]]
106; CHECK-NEXT: blr
107}
108
109; Function Attrs: nounwind readnone
110define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
111entry:
112  %cmp = icmp ne i32 %v3, -2
113  %or6 = or i1 %cmp, %v2
114  %and7 = and i1 %or6, %v1
115  ret i1 %and7
116
117; CHECK-LABEL: @test6
118; CHECK-DAG: li [[NEG2:[0-9]+]], -2
119; CHECK-DAG: clrldi [[CLR1:[0-9]+]], 4, 63
120; CHECK-DAG: clrldi [[CLR2:[0-9]+]], 3, 63
121; CHECK-DAG: xor [[NE1:[0-9]+]], 5, [[NEG2]]
122; CHECK-DAG: cntlzw [[NE2:[0-9]+]], [[NE1]]
123; CHECK: srwi [[NE3:[0-9]+]], [[NE2]], 5
124; CHECK: xori [[NE4:[0-9]+]], [[NE3]], 1
125; CHECK: or [[OR:[0-9]+]], [[NE4]], [[CLR1]]
126; CHECK: and 3, [[OR]], [[CLR2]]
127; CHECK-NEXT: blr
128}
129
130; Function Attrs: nounwind readnone
131define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
132entry:
133  %cond = select i1 %v2, i32 %i1, i32 %i2
134  ret i32 %cond
135
136; CHECK-LABEL: @test7
137; CHECK: andi. {{[0-9]+}}, 3, 1
138; CHECK: isel 3, 4, 5, 1
139; CHECK: blr
140}
141
142define signext i32 @exttest7(i32 signext %a) #0 {
143entry:
144  %cmp = icmp eq i32 %a, 5
145  %cond = select i1 %cmp, i32 7, i32 8
146  ret i32 %cond
147
148; CHECK-LABEL: @exttest7
149; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
150; CHECK-DAG: li [[REG1:[0-9]+]], 8
151; CHECK-DAG: li [[REG2:[0-9]+]], 7
152; CHECK: isel 3, [[REG2]], [[REG1]],
153; CHECK-NOT: rldicl
154; CHECK: blr
155}
156
157define zeroext i32 @exttest8() #0 {
158entry:
159  %v0 = load i64, i64* undef, align 8
160  %sub = sub i64 80, %v0
161  %div = lshr i64 %sub, 1
162  %conv13 = trunc i64 %div to i32
163  %cmp14 = icmp ugt i32 %conv13, 80
164  %.conv13 = select i1 %cmp14, i32 0, i32 %conv13
165  ret i32 %.conv13
166; CHECK-LABEL: @exttest8
167; This is a don't-crash test: %conv13 is both one of the possible select output
168; values and also an input to the conditional feeding it.
169}
170
171; Function Attrs: nounwind readnone
172define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 {
173entry:
174  %cond = select i1 %v2, float %v1, float %v3
175  ret float %cond
176
177; CHECK-LABEL: @test8
178; CHECK: andi. {{[0-9]+}}, 3, 1
179; CHECK: bclr 12, 1, 0
180; CHECK: fmr 1, 2
181; CHECK: blr
182}
183
184; Function Attrs: nounwind readnone
185define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 {
186entry:
187  %tobool = icmp ne i32 %v1, 0
188  %lnot = icmp eq i32 %v2, 0
189  %and3 = and i1 %tobool, %lnot
190  %and = zext i1 %and3 to i32
191  ret i32 %and
192
193; CHECK-LABEL: @test10
194; CHECK-DAG: cntlzw 3, 3
195; CHECK-DAG: cntlzw 4, 4
196; CHECK-DAG: srwi 3, 3, 5
197; CHECK-DAG: srwi 4, 4, 5
198; CHECK: xori 3, 3, 1
199; CHECK: and 3, 3, 4
200; CHECK-NEXT: blr
201}
202
203attributes #0 = { nounwind readnone }
204
205