1; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
3target datalayout = "E-m:e-i64:64-n32:64"
4target triple = "powerpc64-unknown-linux-gnu"
5
6; Function Attrs: nounwind readnone
7define zeroext i1 @test1(float %v1, float %v2) #0 {
8entry:
9  %cmp = fcmp oge float %v1, %v2
10  %cmp2 = fcmp ole float %v2, 0.000000e+00
11  %and5 = and i1 %cmp, %cmp2
12  ret i1 %and5
13
14; CHECK-LABEL: @test1
15; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
16; CHECK-DAG: li [[REG1:[0-9]+]], 1
17; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
18; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
19; CHECK: crnor
20; CHECK: crnor
21; CHECK: crnand [[REG4:[0-9]+]],
22; CHECK: isel 3, 0, [[REG1]], [[REG4]]
23; CHECK-NO-ISEL-LABEL: @test1
24; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
25; CHECK-NO-ISEL-NEXT: blr
26; CHECK-NO-ISEL-NEXT: [[TRUE]]
27; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
28; CHECK-NO-ISEL-NEXT: blr
29; CHECK: blr
30}
31
32; Function Attrs: nounwind readnone
33define zeroext i1 @test2(float %v1, float %v2) #0 {
34entry:
35  %cmp = fcmp oge float %v1, %v2
36  %cmp2 = fcmp ole float %v2, 0.000000e+00
37  %xor5 = xor i1 %cmp, %cmp2
38  ret i1 %xor5
39
40; CHECK-LABEL: @test2
41; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
42; CHECK-DAG: li [[REG1:[0-9]+]], 1
43; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
44; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
45; CHECK: crnor
46; CHECK: crnor
47; CHECK: creqv [[REG4:[0-9]+]],
48; CHECK: isel 3, 0, [[REG1]], [[REG4]]
49; CHECK: blr
50}
51
52; Function Attrs: nounwind readnone
53define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 {
54entry:
55  %cmp = fcmp oge float %v1, %v2
56  %cmp2 = fcmp ole float %v2, 0.000000e+00
57  %cmp4 = icmp ne i32 %x, -2
58  %and7 = and i1 %cmp2, %cmp4
59  %xor8 = xor i1 %cmp, %and7
60  ret i1 %xor8
61
62; CHECK-LABEL: @test3
63; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
64; CHECK-DAG: li [[REG1:[0-9]+]], 1
65; CHECK-DAG: xxlxor [[REG2:[0-9]+]], [[REG2]], [[REG2]]
66; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]]
67; CHECK: crnor
68; CHECK: crnor
69; CHECK: crandc
70; CHECK: creqv [[REG4:[0-9]+]],
71; CHECK: isel 3, 0, [[REG1]], [[REG4]]
72; CHECK: blr
73}
74
75; Function Attrs: nounwind readnone
76define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 {
77entry:
78  %and8 = and i1 %v1, %v2
79  %or9 = or i1 %and8, %v3
80  ret i1 %or9
81
82; CHECK-DAG: @test4
83; CHECK: and [[REG1:[0-9]+]], 3, 4
84; CHECK: or 3, [[REG1]], 5
85; CHECK: blr
86}
87
88; Function Attrs: nounwind readnone
89define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
90entry:
91  %and6 = and i1 %v1, %v2
92  %cmp = icmp ne i32 %v3, -2
93  %or7 = or i1 %and6, %cmp
94  ret i1 %or7
95
96; CHECK-LABEL: @test5
97; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
98; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
99; CHECK-DAG: li [[REG3:[0-9]+]], 1
100; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1
101; CHECK-DAG: crandc [[REG5:[0-9]+]],
102; CHECK: isel 3, 0, [[REG3]], [[REG5]]
103; CHECK: blr
104}
105
106; Function Attrs: nounwind readnone
107define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 {
108entry:
109  %cmp = icmp ne i32 %v3, -2
110  %or6 = or i1 %cmp, %v2
111  %and7 = and i1 %or6, %v1
112  ret i1 %and7
113
114; CHECK-LABEL: @test6
115; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
116; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2
117; CHECK-DAG: crmove [[REG1:[0-9]+]], 1
118; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
119; CHECK-DAG: li [[REG2:[0-9]+]], 1
120; CHECK-DAG: crorc [[REG4:[0-9]+]], 1,
121; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]]
122; CHECK: isel 3, 0, [[REG2]], [[REG5]]
123; CHECK: blr
124}
125
126; Function Attrs: nounwind readnone
127define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 {
128entry:
129  %cond = select i1 %v2, i32 %i1, i32 %i2
130  ret i32 %cond
131
132; CHECK-LABEL: @test7
133; CHECK: andi. {{[0-9]+}}, 3, 1
134; CHECK: isel 3, 4, 5, 1
135; CHECK: blr
136}
137
138define signext i32 @exttest7(i32 signext %a) #0 {
139entry:
140  %cmp = icmp eq i32 %a, 5
141  %cond = select i1 %cmp, i32 7, i32 8
142  ret i32 %cond
143
144; CHECK-LABEL: @exttest7
145; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5
146; CHECK-DAG: li [[REG1:[0-9]+]], 8
147; CHECK-DAG: li [[REG2:[0-9]+]], 7
148; CHECK: isel 3, [[REG2]], [[REG1]],
149; CHECK-NOT: rldicl
150; CHECK: blr
151}
152
153define zeroext i32 @exttest8() #0 {
154entry:
155  %v0 = load i64, i64* undef, align 8
156  %sub = sub i64 80, %v0
157  %div = lshr i64 %sub, 1
158  %conv13 = trunc i64 %div to i32
159  %cmp14 = icmp ugt i32 %conv13, 80
160  %.conv13 = select i1 %cmp14, i32 0, i32 %conv13
161  ret i32 %.conv13
162; CHECK-LABEL: @exttest8
163; This is a don't-crash test: %conv13 is both one of the possible select output
164; values and also an input to the conditional feeding it.
165}
166
167; Function Attrs: nounwind readnone
168define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 {
169entry:
170  %cond = select i1 %v2, float %v1, float %v3
171  ret float %cond
172
173; CHECK-LABEL: @test8
174; CHECK: andi. {{[0-9]+}}, 3, 1
175; CHECK: bclr 12, 1, 0
176; CHECK: fmr 1, 2
177; CHECK: blr
178}
179
180; Function Attrs: nounwind readnone
181define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 {
182entry:
183  %tobool = icmp ne i32 %v1, 0
184  %lnot = icmp eq i32 %v2, 0
185  %and3 = and i1 %tobool, %lnot
186  %and = zext i1 %and3 to i32
187  ret i32 %and
188
189; CHECK-LABEL: @test10
190; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0
191; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0
192; CHECK-DAG: li [[REG2:[0-9]+]], 1
193; CHECK-DAG: crorc [[REG3:[0-9]+]],
194; CHECK: isel 3, 0, [[REG2]], [[REG3]]
195; CHECK: blr
196}
197
198attributes #0 = { nounwind readnone }
199
200