1; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ 2; RUN: < %s | FileCheck %s -check-prefix=P9BE -implicit-check-not frsp 3; RUN: llc -mcpu=pwr9 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ 4; RUN: < %s | FileCheck %s -check-prefix=P9LE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown \ 6; RUN: < %s | FileCheck %s -check-prefix=P8BE -implicit-check-not frsp 7; RUN: llc -mcpu=pwr8 -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown \ 8; RUN: < %s | FileCheck %s -check-prefix=P8LE -implicit-check-not frsp 9 10; This test case comes from the following C test case (included as it may be 11; slightly more readable than the LLVM IR. 12 13;/* This test case provides various ways of building vectors to ensure we 14; produce optimal code for all cases. The cases are (for each type): 15; - All zeros 16; - All ones 17; - Splat of a constant 18; - From different values already in registers 19; - From different constants 20; - From different values in memory 21; - Splat of a value in register 22; - Splat of a value in memory 23; - Inserting element into existing vector 24; - Inserting element from existing vector into existing vector 25; 26; With conversions (float <-> int) 27; - Splat of a constant 28; - From different values already in registers 29; - From different constants 30; - From different values in memory 31; - Splat of a value in register 32; - Splat of a value in memory 33; - Inserting element into existing vector 34; - Inserting element from existing vector into existing vector 35;*/ 36; 37;/*=================================== int ===================================*/ 38;// P8: xxlxor // 39;// P9: xxlxor // 40;vector int allZeroi() { // 41; return (vector int)0; // 42;} // 43;// P8: vspltisb -1 // 44;// P9: xxspltisb 255 // 45;vector int allOnei() { // 46; return (vector int)-1; // 47;} // 48;// P8: vspltisw 1 // 49;// P9: vspltisw 1 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: lxsiwax, xxspltw // 109;// P9: lxvwsx // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 119;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvdpsxws // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 168;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 178;// xvcvspsxws // 179;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 180;// xvcvspsxws // 181;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 182; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 183;} // 184;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 185;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 186;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 187; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 188;} // 189;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 190;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 191;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 192; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 193;} // 194;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 195;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspsxws // 196;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 197; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 198;} // 199;// P8: xscvdpsxws, xxspltw // 200;// P9: xscvdpsxws, xxspltw // 201;vector int spltRegValConvdtoi(double val) { // 202; return (vector int) val; // 203;} // 204;// P8: lxsdx, xscvdpsxws, xxspltw // 205;// P9: lxssp, xscvdpsxws, xxspltw // 206;vector int spltMemValConvdtoi(double *ptr) { // 207; return (vector int)*ptr; // 208;} // 209;/*=================================== int ===================================*/ 210;/*=============================== unsigned int ==============================*/ 211;// P8: xxlxor // 212;// P9: xxlxor // 213;vector unsigned int allZeroui() { // 214; return (vector unsigned int)0; // 215;} // 216;// P8: vspltisb -1 // 217;// P9: xxspltisb 255 // 218;vector unsigned int allOneui() { // 219; return (vector unsigned int)-1; // 220;} // 221;// P8: vspltisw 1 // 222;// P9: vspltisw 1 // 223;vector unsigned int spltConst1ui() { // 224; return (vector unsigned int)1; // 225;} // 226;// P8: vspltisw -15; vsrw // 227;// P9: vspltisw -15; vsrw // 228;vector unsigned int spltConst16kui() { // 229; return (vector unsigned int)((1<<15) - 1); // 230;} // 231;// P8: vspltisw -16; vsrw // 232;// P9: vspltisw -16; vsrw // 233;vector unsigned int spltConst32kui() { // 234; return (vector unsigned int)((1<<16) - 1); // 235;} // 236;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 237;// P9: 2 x mtvsrdd, vmrgow // 238;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 239; unsigned int c, unsigned int d) { // 240; return (vector unsigned int){ a, b, c, d }; // 241;} // 242;// P8: lxvd2x, xxswapd // 243;// P9: lxvx (or even lxv) // 244;vector unsigned int fromDiffConstsui() { // 245; return (vector unsigned int) { 242, -113, 889, 19 }; // 246;} // 247;// P8: lxvd2x, xxswapd // 248;// P9: lxvx // 249;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 250; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 251;} // 252;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 253;// P9: 2 x lxvx, vperm // 254;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 255; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 256;} // 257;// P8: sldi 2, lxvd2x, xxswapd // 258;// P9: sldi 2, lxvx // 259;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 260; return (vector unsigned int) { arr[elem], arr[elem+1], // 261; arr[elem+2], arr[elem+3] }; // 262;} // 263;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 264;// P9: sldi 2, 2 x lxvx, vperm // 265;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 266; return (vector unsigned int) { arr[elem], arr[elem-1], // 267; arr[elem-2], arr[elem-3] }; // 268;} // 269;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 270;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 271;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 272; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 273;} // 274;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 275;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 276;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 277; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 278; arr[elem+2], arr[elem+8] }; // 279;} // 280;// P8: mtvsrwz, xxspltw // 281;// P9: mtvsrws // 282;vector unsigned int spltRegValui(unsigned int val) { // 283; return (vector unsigned int) val; // 284;} // 285;// P8: lxsiwax, xxspltw // 286;// P9: lxvwsx // 287;vector unsigned int spltMemValui(unsigned int *ptr) { // 288; return (vector unsigned int)*ptr; // 289;} // 290;// P8: vspltisw // 291;// P9: vspltisw // 292;vector unsigned int spltCnstConvftoui() { // 293; return (vector unsigned int) 4.74f; // 294;} // 295;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 296;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 297;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 298; return (vector unsigned int) { a, b, c, d }; // 299;} // 300;// P8: lxvd2x, xxswapd // 301;// P9: lxvx (even lxv) // 302;vector unsigned int fromDiffConstsConvftoui() { // 303; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 304;} // 305;// P8: lxvd2x, xxswapd, xvcvspuxws // 306;// P9: lxvx, xvcvspuxws // 307;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 308; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 309;} // 310;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 311;// P9: 2 x lxvx, vperm, xvcvspuxws // 312;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 313; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 314;} // 315;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 316;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 317;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 318;// sldi 2, load, xvcvspuxws // 319;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 320; return (vector unsigned int) { arr[elem], arr[elem+1], // 321; arr[elem+2], arr[elem+3] }; // 322;} // 323;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 324;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 325;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 326;// sldi 2, 2 x load, vperm, xvcvspuxws // 327;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 328; return (vector unsigned int) { arr[elem], arr[elem-1], // 329; arr[elem-2], arr[elem-3] }; // 330;} // 331;// P8: xscvdpuxws, xxspltw // 332;// P9: xscvdpuxws, xxspltw // 333;vector unsigned int spltRegValConvftoui(float val) { // 334; return (vector unsigned int) val; // 335;} // 336;// P8: lxsspx, xscvdpuxws, xxspltw // 337;// P9: lxvwsx, xvcvspuxws // 338;vector unsigned int spltMemValConvftoui(float *ptr) { // 339; return (vector unsigned int)*ptr; // 340;} // 341;// P8: vspltisw // 342;// P9: vspltisw // 343;vector unsigned int spltCnstConvdtoui() { // 344; return (vector unsigned int) 4.74; // 345;} // 346;// P8: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 347;// P9: 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 348;vector unsigned int fromRegsConvdtoui(double a, double b, // 349; double c, double d) { // 350; return (vector unsigned int) { a, b, c, d }; // 351;} // 352;// P8: lxvd2x, xxswapd // 353;// P9: lxvx (even lxv) // 354;vector unsigned int fromDiffConstsConvdtoui() { // 355; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 356;} // 357;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, // 358;// xvcvspuxws // 359;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 360;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 361; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 362;} // 363;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 364;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 365;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 366; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 367;} // 368;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 369;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 370;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 371; return (vector unsigned int) { arr[elem], arr[elem+1], // 372; arr[elem+2], arr[elem+3] }; // 373;} // 374;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 375;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvdpsp, vmrgew, xvcvspuxws // 376;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 377; return (vector unsigned int) { arr[elem], arr[elem-1], // 378; arr[elem-2], arr[elem-3] }; // 379;} // 380;// P8: xscvdpuxws, xxspltw // 381;// P9: xscvdpuxws, xxspltw // 382;vector unsigned int spltRegValConvdtoui(double val) { // 383; return (vector unsigned int) val; // 384;} // 385;// P8: lxsspx, xscvdpuxws, xxspltw // 386;// P9: lfd, xscvdpuxws, xxspltw // 387;vector unsigned int spltMemValConvdtoui(double *ptr) { // 388; return (vector unsigned int)*ptr; // 389;} // 390;/*=============================== unsigned int ==============================*/ 391;/*=============================== long long =================================*/ 392;// P8: xxlxor // 393;// P9: xxlxor // 394;vector long long allZeroll() { // 395; return (vector long long)0; // 396;} // 397;// P8: vspltisb -1 // 398;// P9: xxspltisb 255 // 399;vector long long allOnell() { // 400; return (vector long long)-1; // 401;} // 402;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 403;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 404;vector long long spltConst1ll() { // 405; return (vector long long)1; // 406;} // 407;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 408;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 409;vector long long spltConst16kll() { // 410; return (vector long long)((1<<15) - 1); // 411;} // 412;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 413;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 414;vector long long spltConst32kll() { // 415; return (vector long long)((1<<16) - 1); // 416;} // 417;// P8: 2 x mtvsrd, xxmrghd // 418;// P9: mtvsrdd // 419;vector long long fromRegsll(long long a, long long b) { // 420; return (vector long long){ a, b }; // 421;} // 422;// P8: lxvd2x, xxswapd // 423;// P9: lxvx (or even lxv) // 424;vector long long fromDiffConstsll() { // 425; return (vector long long) { 242, -113 }; // 426;} // 427;// P8: lxvd2x, xxswapd // 428;// P9: lxvx // 429;vector long long fromDiffMemConsAll(long long *arr) { // 430; return (vector long long) { arr[0], arr[1] }; // 431;} // 432;// P8: lxvd2x // 433;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 434;vector long long fromDiffMemConsDll(long long *arr) { // 435; return (vector long long) { arr[3], arr[2] }; // 436;} // 437;// P8: sldi 3, lxvd2x, xxswapd // 438;// P9: sldi 3, lxvx // 439;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 440; return (vector long long) { arr[elem], arr[elem+1] }; // 441;} // 442;// P8: sldi 3, lxvd2x // 443;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 444;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 445; return (vector long long) { arr[elem], arr[elem-1] }; // 446;} // 447;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 448;// P9: 2 x ld, mtvsrdd // 449;vector long long fromRandMemConsll(long long *arr) { // 450; return (vector long long) { arr[4], arr[18] }; // 451;} // 452;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 453;// P9: sldi 3, add, 2 x ld, mtvsrdd // 454;vector long long fromRandMemVarll(long long *arr, int elem) { // 455; return (vector long long) { arr[elem+4], arr[elem+1] }; // 456;} // 457;// P8: mtvsrd, xxspltd // 458;// P9: mtvsrdd // 459;vector long long spltRegValll(long long val) { // 460; return (vector long long) val; // 461;} // 462;// P8: lxvdsx // 463;// P9: lxvdsx // 464;vector long long spltMemValll(long long *ptr) { // 465; return (vector long long)*ptr; // 466;} // 467;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 468;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 469;vector long long spltCnstConvftoll() { // 470; return (vector long long) 4.74f; // 471;} // 472;// P8: xxmrghd, xvcvdpsxds // 473;// P9: xxmrghd, xvcvdpsxds // 474;vector long long fromRegsConvftoll(float a, float b) { // 475; return (vector long long) { a, b }; // 476;} // 477;// P8: lxvd2x, xxswapd // 478;// P9: lxvx (even lxv) // 479;vector long long fromDiffConstsConvftoll() { // 480; return (vector long long) { 24.46f, 234.f }; // 481;} // 482;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 483;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 484;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 485; return (vector long long) { ptr[0], ptr[1] }; // 486;} // 487;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 488;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 489;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 490; return (vector long long) { ptr[3], ptr[2] }; // 491;} // 492;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 493;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 494;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 495; return (vector long long) { arr[elem], arr[elem+1] }; // 496;} // 497;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 498;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 499;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 500; return (vector long long) { arr[elem], arr[elem-1] }; // 501;} // 502;// P8: xscvdpsxds, xxspltd // 503;// P9: xscvdpsxds, xxspltd // 504;vector long long spltRegValConvftoll(float val) { // 505; return (vector long long) val; // 506;} // 507;// P8: lxsspx, xscvdpsxds, xxspltd // 508;// P9: lfs, xscvdpsxds, xxspltd // 509;vector long long spltMemValConvftoll(float *ptr) { // 510; return (vector long long)*ptr; // 511;} // 512;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 513;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 514;vector long long spltCnstConvdtoll() { // 515; return (vector long long) 4.74; // 516;} // 517;// P8: xxmrghd, xvcvdpsxds // 518;// P9: xxmrghd, xvcvdpsxds // 519;vector long long fromRegsConvdtoll(double a, double b) { // 520; return (vector long long) { a, b }; // 521;} // 522;// P8: lxvd2x, xxswapd // 523;// P9: lxvx (even lxv) // 524;vector long long fromDiffConstsConvdtoll() { // 525; return (vector long long) { 24.46, 234. }; // 526;} // 527;// P8: lxvd2x, xxswapd, xvcvdpsxds // 528;// P9: lxvx, xvcvdpsxds // 529;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 530; return (vector long long) { ptr[0], ptr[1] }; // 531;} // 532;// P8: lxvd2x, xvcvdpsxds // 533;// P9: lxvx, xxswapd, xvcvdpsxds // 534;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 535; return (vector long long) { ptr[3], ptr[2] }; // 536;} // 537;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 538;// P9: sldi 3, lxvx, xvcvdpsxds // 539;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 540; return (vector long long) { arr[elem], arr[elem+1] }; // 541;} // 542;// P8: sldi 3, lxvd2x, xvcvdpsxds // 543;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 544;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 545; return (vector long long) { arr[elem], arr[elem-1] }; // 546;} // 547;// P8: xscvdpsxds, xxspltd // 548;// P9: xscvdpsxds, xxspltd // 549;vector long long spltRegValConvdtoll(double val) { // 550; return (vector long long) val; // 551;} // 552;// P8: lxvdsx, xvcvdpsxds // 553;// P9: lxvdsx, xvcvdpsxds // 554;vector long long spltMemValConvdtoll(double *ptr) { // 555; return (vector long long)*ptr; // 556;} // 557;/*=============================== long long =================================*/ 558;/*========================== unsigned long long =============================*/ 559;// P8: xxlxor // 560;// P9: xxlxor // 561;vector unsigned long long allZeroull() { // 562; return (vector unsigned long long)0; // 563;} // 564;// P8: vspltisb -1 // 565;// P9: xxspltisb 255 // 566;vector unsigned long long allOneull() { // 567; return (vector unsigned long long)-1; // 568;} // 569;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 570;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 571;vector unsigned long long spltConst1ull() { // 572; return (vector unsigned long long)1; // 573;} // 574;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 575;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 576;vector unsigned long long spltConst16kull() { // 577; return (vector unsigned long long)((1<<15) - 1); // 578;} // 579;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 580;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 581;vector unsigned long long spltConst32kull() { // 582; return (vector unsigned long long)((1<<16) - 1); // 583;} // 584;// P8: 2 x mtvsrd, xxmrghd // 585;// P9: mtvsrdd // 586;vector unsigned long long fromRegsull(unsigned long long a, // 587; unsigned long long b) { // 588; return (vector unsigned long long){ a, b }; // 589;} // 590;// P8: lxvd2x, xxswapd // 591;// P9: lxvx (or even lxv) // 592;vector unsigned long long fromDiffConstsull() { // 593; return (vector unsigned long long) { 242, -113 }; // 594;} // 595;// P8: lxvd2x, xxswapd // 596;// P9: lxvx // 597;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 598; return (vector unsigned long long) { arr[0], arr[1] }; // 599;} // 600;// P8: lxvd2x // 601;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 602;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 603; return (vector unsigned long long) { arr[3], arr[2] }; // 604;} // 605;// P8: sldi 3, lxvd2x, xxswapd // 606;// P9: sldi 3, lxvx // 607;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 608; int elem) { // 609; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 610;} // 611;// P8: sldi 3, lxvd2x // 612;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 613;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 614; int elem) { // 615; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 616;} // 617;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 618;// P9: 2 x ld, mtvsrdd // 619;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 620; return (vector unsigned long long) { arr[4], arr[18] }; // 621;} // 622;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 623;// P9: sldi 3, add, 2 x ld, mtvsrdd // 624;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 625; int elem) { // 626; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 627;} // 628;// P8: mtvsrd, xxspltd // 629;// P9: mtvsrdd // 630;vector unsigned long long spltRegValull(unsigned long long val) { // 631; return (vector unsigned long long) val; // 632;} // 633;// P8: lxvdsx // 634;// P9: lxvdsx // 635;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 636; return (vector unsigned long long)*ptr; // 637;} // 638;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 639;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 640;vector unsigned long long spltCnstConvftoull() { // 641; return (vector unsigned long long) 4.74f; // 642;} // 643;// P8: xxmrghd, xvcvdpuxds // 644;// P9: xxmrghd, xvcvdpuxds // 645;vector unsigned long long fromRegsConvftoull(float a, float b) { // 646; return (vector unsigned long long) { a, b }; // 647;} // 648;// P8: lxvd2x, xxswapd // 649;// P9: lxvx (even lxv) // 650;vector unsigned long long fromDiffConstsConvftoull() { // 651; return (vector unsigned long long) { 24.46f, 234.f }; // 652;} // 653;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 654;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 655;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 656; return (vector unsigned long long) { ptr[0], ptr[1] }; // 657;} // 658;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 659;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 660;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 661; return (vector unsigned long long) { ptr[3], ptr[2] }; // 662;} // 663;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 664;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 665;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 666; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 667;} // 668;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 669;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 670;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 671; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 672;} // 673;// P8: xscvdpuxds, xxspltd // 674;// P9: xscvdpuxds, xxspltd // 675;vector unsigned long long spltRegValConvftoull(float val) { // 676; return (vector unsigned long long) val; // 677;} // 678;// P8: lxsspx, xscvdpuxds, xxspltd // 679;// P9: lfs, xscvdpuxds, xxspltd // 680;vector unsigned long long spltMemValConvftoull(float *ptr) { // 681; return (vector unsigned long long)*ptr; // 682;} // 683;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 684;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 685;vector unsigned long long spltCnstConvdtoull() { // 686; return (vector unsigned long long) 4.74; // 687;} // 688;// P8: xxmrghd, xvcvdpuxds // 689;// P9: xxmrghd, xvcvdpuxds // 690;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 691; return (vector unsigned long long) { a, b }; // 692;} // 693;// P8: lxvd2x, xxswapd // 694;// P9: lxvx (even lxv) // 695;vector unsigned long long fromDiffConstsConvdtoull() { // 696; return (vector unsigned long long) { 24.46, 234. }; // 697;} // 698;// P8: lxvd2x, xxswapd, xvcvdpuxds // 699;// P9: lxvx, xvcvdpuxds // 700;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 701; return (vector unsigned long long) { ptr[0], ptr[1] }; // 702;} // 703;// P8: lxvd2x, xvcvdpuxds // 704;// P9: lxvx, xxswapd, xvcvdpuxds // 705;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 706; return (vector unsigned long long) { ptr[3], ptr[2] }; // 707;} // 708;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 709;// P9: sldi 3, lxvx, xvcvdpuxds // 710;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 711; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 712;} // 713;// P8: sldi 3, lxvd2x, xvcvdpuxds // 714;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 715;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 716; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 717;} // 718;// P8: xscvdpuxds, xxspltd // 719;// P9: xscvdpuxds, xxspltd // 720;vector unsigned long long spltRegValConvdtoull(double val) { // 721; return (vector unsigned long long) val; // 722;} // 723;// P8: lxvdsx, xvcvdpuxds // 724;// P9: lxvdsx, xvcvdpuxds // 725;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 726; return (vector unsigned long long)*ptr; // 727;} // 728;/*========================== unsigned long long ==============================*/ 729 730; Function Attrs: norecurse nounwind readnone 731define <4 x i32> @allZeroi() { 732entry: 733 ret <4 x i32> zeroinitializer 734; P9BE-LABEL: allZeroi 735; P9LE-LABEL: allZeroi 736; P8BE-LABEL: allZeroi 737; P8LE-LABEL: allZeroi 738; P9BE: xxlxor v2, v2, v2 739; P9BE: blr 740; P9LE: xxlxor v2, v2, v2 741; P9LE: blr 742; P8BE: xxlxor v2, v2, v2 743; P8BE: blr 744; P8LE: xxlxor v2, v2, v2 745; P8LE: blr 746} 747 748; Function Attrs: norecurse nounwind readnone 749define <4 x i32> @allOnei() { 750entry: 751 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 752; P9BE-LABEL: allOnei 753; P9LE-LABEL: allOnei 754; P8BE-LABEL: allOnei 755; P8LE-LABEL: allOnei 756; P9BE: xxspltib v2, 255 757; P9BE: blr 758; P9LE: xxspltib v2, 255 759; P9LE: blr 760; P8BE: vspltisb v2, -1 761; P8BE: blr 762; P8LE: vspltisb v2, -1 763; P8LE: blr 764} 765 766; Function Attrs: norecurse nounwind readnone 767define <4 x i32> @spltConst1i() { 768entry: 769 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 770; P9BE-LABEL: spltConst1i 771; P9LE-LABEL: spltConst1i 772; P8BE-LABEL: spltConst1i 773; P8LE-LABEL: spltConst1i 774; P9BE: vspltisw v2, 1 775; P9BE: blr 776; P9LE: vspltisw v2, 1 777; P9LE: blr 778; P8BE: vspltisw v2, 1 779; P8BE: blr 780; P8LE: vspltisw v2, 1 781; P8LE: blr 782} 783 784; Function Attrs: norecurse nounwind readnone 785define <4 x i32> @spltConst16ki() { 786entry: 787 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 788; P9BE-LABEL: spltConst16ki 789; P9LE-LABEL: spltConst16ki 790; P8BE-LABEL: spltConst16ki 791; P8LE-LABEL: spltConst16ki 792; P9BE: vspltisw v2, -15 793; P9BE: vsrw v2, v2, v2 794; P9BE: blr 795; P9LE: vspltisw v2, -15 796; P9LE: vsrw v2, v2, v2 797; P9LE: blr 798; P8BE: vspltisw v2, -15 799; P8BE: vsrw v2, v2, v2 800; P8BE: blr 801; P8LE: vspltisw v2, -15 802; P8LE: vsrw v2, v2, v2 803; P8LE: blr 804} 805 806; Function Attrs: norecurse nounwind readnone 807define <4 x i32> @spltConst32ki() { 808entry: 809 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 810; P9BE-LABEL: spltConst32ki 811; P9LE-LABEL: spltConst32ki 812; P8BE-LABEL: spltConst32ki 813; P8LE-LABEL: spltConst32ki 814; P9BE: vspltisw v2, -16 815; P9BE: vsrw v2, v2, v2 816; P9BE: blr 817; P9LE: vspltisw v2, -16 818; P9LE: vsrw v2, v2, v2 819; P9LE: blr 820; P8BE: vspltisw v2, -16 821; P8BE: vsrw v2, v2, v2 822; P8BE: blr 823; P8LE: vspltisw v2, -16 824; P8LE: vsrw v2, v2, v2 825; P8LE: blr 826} 827 828; Function Attrs: norecurse nounwind readnone 829define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 830entry: 831 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 832 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 833 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 834 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 835 ret <4 x i32> %vecinit3 836; P9BE-LABEL: fromRegsi 837; P9LE-LABEL: fromRegsi 838; P8BE-LABEL: fromRegsi 839; P8LE-LABEL: fromRegsi 840; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 841; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 842; P9BE: vmrgow v2, [[REG1]], [[REG2]] 843; P9BE: blr 844; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 845; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 846; P9LE: vmrgow v2, [[REG2]], [[REG1]] 847; P9LE: blr 848; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 849; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 850; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 851; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 852; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 853; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 854; P8BE: vmrgow v2, [[REG5]], [[REG6]] 855; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 856; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 857; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 858; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 859; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 860; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 861; P8LE: vmrgow v2, [[REG6]], [[REG5]] 862} 863 864; Function Attrs: norecurse nounwind readnone 865define <4 x i32> @fromDiffConstsi() { 866entry: 867 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 868; P9BE-LABEL: fromDiffConstsi 869; P9LE-LABEL: fromDiffConstsi 870; P8BE-LABEL: fromDiffConstsi 871; P8LE-LABEL: fromDiffConstsi 872; P9BE: lxv 873; P9BE: blr 874; P9LE: lxv 875; P9LE: blr 876; P8BE: lxvw4x 877; P8BE: blr 878; P8LE: lvx 879; P8LE-NOT: xxswapd 880; P8LE: blr 881} 882 883; Function Attrs: norecurse nounwind readonly 884define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 885entry: 886 %0 = load i32, i32* %arr, align 4 887 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 888 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 889 %1 = load i32, i32* %arrayidx1, align 4 890 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 891 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 892 %2 = load i32, i32* %arrayidx3, align 4 893 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 894 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 895 %3 = load i32, i32* %arrayidx5, align 4 896 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 897 ret <4 x i32> %vecinit6 898; P9BE-LABEL: fromDiffMemConsAi 899; P9LE-LABEL: fromDiffMemConsAi 900; P8BE-LABEL: fromDiffMemConsAi 901; P8LE-LABEL: fromDiffMemConsAi 902; P9BE: lxv 903; P9BE: blr 904; P9LE: lxv 905; P9LE: blr 906; P8BE: lxvw4x 907; P8BE: blr 908; P8LE: lxvd2x 909; P8LE: xxswapd 910; P8LE: blr 911} 912 913; Function Attrs: norecurse nounwind readonly 914define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 915entry: 916 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 917 %0 = load i32, i32* %arrayidx, align 4 918 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 919 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 920 %1 = load i32, i32* %arrayidx1, align 4 921 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 922 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 923 %2 = load i32, i32* %arrayidx3, align 4 924 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 925 %3 = load i32, i32* %arr, align 4 926 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 927 ret <4 x i32> %vecinit6 928; P9BE-LABEL: fromDiffMemConsDi 929; P9LE-LABEL: fromDiffMemConsDi 930; P8BE-LABEL: fromDiffMemConsDi 931; P8LE-LABEL: fromDiffMemConsDi 932; P9BE: lxv 933; P9BE: lxv 934; P9BE: vperm 935; P9BE: blr 936; P9LE: lxv 937; P9LE: lxv 938; P9LE: vperm 939; P9LE: blr 940; P8BE: lxvw4x 941; P8BE: lxvw4x 942; P8BE: vperm 943; P8BE: blr 944; P8LE: lxvd2x 945; P8LE-DAG: lvx 946; P8LE: xxswapd 947; P8LE: vperm 948; P8LE: blr 949} 950 951; Function Attrs: norecurse nounwind readonly 952define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 953entry: 954 %idxprom = sext i32 %elem to i64 955 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 956 %0 = load i32, i32* %arrayidx, align 4 957 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 958 %add = add nsw i32 %elem, 1 959 %idxprom1 = sext i32 %add to i64 960 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 961 %1 = load i32, i32* %arrayidx2, align 4 962 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 963 %add4 = add nsw i32 %elem, 2 964 %idxprom5 = sext i32 %add4 to i64 965 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 966 %2 = load i32, i32* %arrayidx6, align 4 967 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 968 %add8 = add nsw i32 %elem, 3 969 %idxprom9 = sext i32 %add8 to i64 970 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 971 %3 = load i32, i32* %arrayidx10, align 4 972 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 973 ret <4 x i32> %vecinit11 974; P9BE-LABEL: fromDiffMemVarAi 975; P9LE-LABEL: fromDiffMemVarAi 976; P8BE-LABEL: fromDiffMemVarAi 977; P8LE-LABEL: fromDiffMemVarAi 978; P9BE: sldi r4, r4, 2 979; P9BE: lxvx v2, r3, r4 980; P9BE: blr 981; P9LE: sldi r4, r4, 2 982; P9LE: lxvx v2, r3, r4 983; P9LE: blr 984; P8BE: sldi r4, r4, 2 985; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 986; P8BE: blr 987; P8LE: sldi r4, r4, 2 988; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 989; P8LE: xxswapd 990; P8LE: blr 991} 992 993; Function Attrs: norecurse nounwind readonly 994define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 995entry: 996 %idxprom = sext i32 %elem to i64 997 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 998 %0 = load i32, i32* %arrayidx, align 4 999 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1000 %sub = add nsw i32 %elem, -1 1001 %idxprom1 = sext i32 %sub to i64 1002 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1003 %1 = load i32, i32* %arrayidx2, align 4 1004 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1005 %sub4 = add nsw i32 %elem, -2 1006 %idxprom5 = sext i32 %sub4 to i64 1007 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1008 %2 = load i32, i32* %arrayidx6, align 4 1009 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1010 %sub8 = add nsw i32 %elem, -3 1011 %idxprom9 = sext i32 %sub8 to i64 1012 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1013 %3 = load i32, i32* %arrayidx10, align 4 1014 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1015 ret <4 x i32> %vecinit11 1016; P9BE-LABEL: fromDiffMemVarDi 1017; P9LE-LABEL: fromDiffMemVarDi 1018; P8BE-LABEL: fromDiffMemVarDi 1019; P8LE-LABEL: fromDiffMemVarDi 1020; P9BE: sldi {{r[0-9]+}}, r4, 2 1021; P9BE-DAG: lxv {{v[0-9]+}} 1022; P9BE-DAG: lxv 1023; P9BE: vperm 1024; P9BE: blr 1025; P9LE: sldi {{r[0-9]+}}, r4, 2 1026; P9LE-DAG: lxv {{v[0-9]+}} 1027; P9LE-DAG: lxv 1028; P9LE: vperm 1029; P9LE: blr 1030; P8BE: sldi {{r[0-9]+}}, r4, 2 1031; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3, 1032; P8BE-DAG: lxvw4x 1033; P8BE: vperm 1034; P8BE: blr 1035; P8LE: sldi {{r[0-9]+}}, r4, 2 1036; P8LE-DAG: lxvd2x 1037; P8LE-DAG: lxvd2x 1038; P8LE: xxswapd 1039; P8LE: vperm 1040; P8LE: blr 1041} 1042 1043; Function Attrs: norecurse nounwind readonly 1044define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1045entry: 1046 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1047 %0 = load i32, i32* %arrayidx, align 4 1048 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1049 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1050 %1 = load i32, i32* %arrayidx1, align 4 1051 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1052 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1053 %2 = load i32, i32* %arrayidx3, align 4 1054 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1055 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1056 %3 = load i32, i32* %arrayidx5, align 4 1057 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1058 ret <4 x i32> %vecinit6 1059; P9BE-LABEL: fromRandMemConsi 1060; P9LE-LABEL: fromRandMemConsi 1061; P8BE-LABEL: fromRandMemConsi 1062; P8LE-LABEL: fromRandMemConsi 1063; P9BE: lwz 1064; P9BE: lwz 1065; P9BE: lwz 1066; P9BE: lwz 1067; P9BE: mtvsrdd 1068; P9BE: mtvsrdd 1069; P9BE: vmrgow 1070; P9LE: lwz 1071; P9LE: lwz 1072; P9LE: lwz 1073; P9LE: lwz 1074; P9LE: mtvsrdd 1075; P9LE: mtvsrdd 1076; P9LE: vmrgow 1077; P8BE: lwz 1078; P8BE: lwz 1079; P8BE: lwz 1080; P8BE: lwz 1081; P8BE: mtvsrwz 1082; P8BE: mtvsrwz 1083; P8BE: mtvsrwz 1084; P8BE: mtvsrwz 1085; P8BE: xxmrghd 1086; P8BE: xxmrghd 1087; P8BE: vmrgow 1088; P8LE: lwz 1089; P8LE: lwz 1090; P8LE: lwz 1091; P8LE: lwz 1092; P8LE: mtvsrwz 1093; P8LE: mtvsrwz 1094; P8LE: mtvsrwz 1095; P8LE: mtvsrwz 1096; P8LE: xxmrghd 1097; P8LE: xxmrghd 1098; P8LE: vmrgow 1099} 1100 1101; Function Attrs: norecurse nounwind readonly 1102define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1103entry: 1104 %add = add nsw i32 %elem, 4 1105 %idxprom = sext i32 %add to i64 1106 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1107 %0 = load i32, i32* %arrayidx, align 4 1108 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1109 %add1 = add nsw i32 %elem, 1 1110 %idxprom2 = sext i32 %add1 to i64 1111 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1112 %1 = load i32, i32* %arrayidx3, align 4 1113 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1114 %add5 = add nsw i32 %elem, 2 1115 %idxprom6 = sext i32 %add5 to i64 1116 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1117 %2 = load i32, i32* %arrayidx7, align 4 1118 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1119 %add9 = add nsw i32 %elem, 8 1120 %idxprom10 = sext i32 %add9 to i64 1121 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1122 %3 = load i32, i32* %arrayidx11, align 4 1123 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1124 ret <4 x i32> %vecinit12 1125; P9BE-LABEL: fromRandMemVari 1126; P9LE-LABEL: fromRandMemVari 1127; P8BE-LABEL: fromRandMemVari 1128; P8LE-LABEL: fromRandMemVari 1129; P9BE: sldi r4, r4, 2 1130; P9BE: lwz 1131; P9BE: lwz 1132; P9BE: lwz 1133; P9BE: lwz 1134; P9BE: mtvsrdd 1135; P9BE: mtvsrdd 1136; P9BE: vmrgow 1137; P9LE: sldi r4, r4, 2 1138; P9LE: lwz 1139; P9LE: lwz 1140; P9LE: lwz 1141; P9LE: lwz 1142; P9LE: mtvsrdd 1143; P9LE: mtvsrdd 1144; P9LE: vmrgow 1145; P8BE: sldi r4, r4, 2 1146; P8BE: lwz 1147; P8BE: lwz 1148; P8BE: lwz 1149; P8BE: lwz 1150; P8BE: mtvsrwz 1151; P8BE: mtvsrwz 1152; P8BE: mtvsrwz 1153; P8BE: mtvsrwz 1154; P8BE: xxmrghd 1155; P8BE: xxmrghd 1156; P8BE: vmrgow 1157; P8LE: sldi r4, r4, 2 1158; P8LE: lwz 1159; P8LE: lwz 1160; P8LE: lwz 1161; P8LE: lwz 1162; P8LE: mtvsrwz 1163; P8LE: mtvsrwz 1164; P8LE: mtvsrwz 1165; P8LE: mtvsrwz 1166; P8LE: xxmrghd 1167; P8LE: xxmrghd 1168; P8LE: vmrgow 1169} 1170 1171; Function Attrs: norecurse nounwind readnone 1172define <4 x i32> @spltRegVali(i32 signext %val) { 1173entry: 1174 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1175 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1176 ret <4 x i32> %splat.splat 1177; P9BE-LABEL: spltRegVali 1178; P9LE-LABEL: spltRegVali 1179; P8BE-LABEL: spltRegVali 1180; P8LE-LABEL: spltRegVali 1181; P9BE: mtvsrws v2, r3 1182; P9BE: blr 1183; P9LE: mtvsrws v2, r3 1184; P9LE: blr 1185; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 1186; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1187; P8BE: blr 1188; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 1189; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1190; P8LE: blr 1191} 1192 1193; Function Attrs: norecurse nounwind readonly 1194define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1195entry: 1196 %0 = load i32, i32* %ptr, align 4 1197 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1198 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1199 ret <4 x i32> %splat.splat 1200; P9BE-LABEL: spltMemVali 1201; P9LE-LABEL: spltMemVali 1202; P8BE-LABEL: spltMemVali 1203; P8LE-LABEL: spltMemVali 1204; P9BE: lxvwsx v2, 0, r3 1205; P9BE: blr 1206; P9LE: lxvwsx v2, 0, r3 1207; P9LE: blr 1208; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 1209; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1210; P8BE: blr 1211; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 1212; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1213; P8LE: blr 1214} 1215 1216; Function Attrs: norecurse nounwind readnone 1217define <4 x i32> @spltCnstConvftoi() { 1218entry: 1219 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1220; P9BE-LABEL: spltCnstConvftoi 1221; P9LE-LABEL: spltCnstConvftoi 1222; P8BE-LABEL: spltCnstConvftoi 1223; P8LE-LABEL: spltCnstConvftoi 1224; P9BE: vspltisw v2, 4 1225; P9BE: blr 1226; P9LE: vspltisw v2, 4 1227; P9LE: blr 1228; P8BE: vspltisw v2, 4 1229; P8BE: blr 1230; P8LE: vspltisw v2, 4 1231; P8LE: blr 1232} 1233 1234; Function Attrs: norecurse nounwind readnone 1235define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1236entry: 1237 %conv = fptosi float %a to i32 1238 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1239 %conv1 = fptosi float %b to i32 1240 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1241 %conv3 = fptosi float %c to i32 1242 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1243 %conv5 = fptosi float %d to i32 1244 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1245 ret <4 x i32> %vecinit6 1246; P9BE-LABEL: fromRegsConvftoi 1247; P9LE-LABEL: fromRegsConvftoi 1248; P8BE-LABEL: fromRegsConvftoi 1249; P8LE-LABEL: fromRegsConvftoi 1250; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1251; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1252; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1253; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1254; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1255; P9BE: xvcvspsxws v2, v2 1256; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1257; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1258; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1259; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1260; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1261; P9LE: xvcvspsxws v2, v2 1262; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1263; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1264; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1265; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1266; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1267; P8BE: xvcvspsxws v2, v2 1268; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1269; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1270; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1271; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1272; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1273; P8LE: xvcvspsxws v2, v2 1274} 1275 1276; Function Attrs: norecurse nounwind readnone 1277define <4 x i32> @fromDiffConstsConvftoi() { 1278entry: 1279 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1280; P9BE-LABEL: fromDiffConstsConvftoi 1281; P9LE-LABEL: fromDiffConstsConvftoi 1282; P8BE-LABEL: fromDiffConstsConvftoi 1283; P8LE-LABEL: fromDiffConstsConvftoi 1284; P9BE: lxv 1285; P9BE: blr 1286; P9LE: lxv 1287; P9LE: blr 1288; P8BE: lxvw4x 1289; P8BE: blr 1290; P8LE: lvx 1291; P8LE-NOT: xxswapd 1292; P8LE: blr 1293} 1294 1295; Function Attrs: norecurse nounwind readonly 1296define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1297entry: 1298 %0 = bitcast float* %ptr to <4 x float>* 1299 %1 = load <4 x float>, <4 x float>* %0, align 4 1300 %2 = fptosi <4 x float> %1 to <4 x i32> 1301 ret <4 x i32> %2 1302; P9BE-LABEL: fromDiffMemConsAConvftoi 1303; P9LE-LABEL: fromDiffMemConsAConvftoi 1304; P8BE-LABEL: fromDiffMemConsAConvftoi 1305; P8LE-LABEL: fromDiffMemConsAConvftoi 1306; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 1307; P9BE: xvcvspsxws v2, [[REG1]] 1308; P9BE: blr 1309; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 1310; P9LE: xvcvspsxws v2, [[REG1]] 1311; P9LE: blr 1312; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 1313; P8BE: xvcvspsxws v2, [[REG1]] 1314; P8BE: blr 1315; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1316; P8LE: xxswapd 1317; P8LE: xvcvspsxws v2, v2 1318; P8LE: blr 1319} 1320 1321; Function Attrs: norecurse nounwind readonly 1322define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1323entry: 1324 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1325 %0 = load float, float* %arrayidx, align 4 1326 %conv = fptosi float %0 to i32 1327 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1328 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1329 %1 = load float, float* %arrayidx1, align 4 1330 %conv2 = fptosi float %1 to i32 1331 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1332 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1333 %2 = load float, float* %arrayidx4, align 4 1334 %conv5 = fptosi float %2 to i32 1335 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1336 %3 = load float, float* %ptr, align 4 1337 %conv8 = fptosi float %3 to i32 1338 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1339 ret <4 x i32> %vecinit9 1340; P9BE-LABEL: fromDiffMemConsDConvftoi 1341; P9LE-LABEL: fromDiffMemConsDConvftoi 1342; P8BE-LABEL: fromDiffMemConsDConvftoi 1343; P8LE-LABEL: fromDiffMemConsDConvftoi 1344; P9BE: lxv 1345; P9BE: lxv 1346; P9BE: vperm 1347; P9BE: xvcvspsxws 1348; P9BE: blr 1349; P9LE: lxv 1350; P9LE: lxv 1351; P9LE: vperm 1352; P9LE: xvcvspsxws 1353; P9LE: blr 1354; P8BE: lxvw4x 1355; P8BE: lxvw4x 1356; P8BE: vperm 1357; P8BE: xvcvspsxws 1358; P8BE: blr 1359; P8LE: lxvd2x 1360; P8LE-DAG: lvx 1361; P8LE: xxswapd 1362; P8LE: vperm 1363; P8LE: xvcvspsxws 1364; P8LE: blr 1365} 1366 1367; Function Attrs: norecurse nounwind readonly 1368define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1369entry: 1370 %idxprom = sext i32 %elem to i64 1371 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1372 %0 = load float, float* %arrayidx, align 4 1373 %conv = fptosi float %0 to i32 1374 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1375 %add = add nsw i32 %elem, 1 1376 %idxprom1 = sext i32 %add to i64 1377 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1378 %1 = load float, float* %arrayidx2, align 4 1379 %conv3 = fptosi float %1 to i32 1380 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1381 %add5 = add nsw i32 %elem, 2 1382 %idxprom6 = sext i32 %add5 to i64 1383 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1384 %2 = load float, float* %arrayidx7, align 4 1385 %conv8 = fptosi float %2 to i32 1386 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1387 %add10 = add nsw i32 %elem, 3 1388 %idxprom11 = sext i32 %add10 to i64 1389 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1390 %3 = load float, float* %arrayidx12, align 4 1391 %conv13 = fptosi float %3 to i32 1392 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1393 ret <4 x i32> %vecinit14 1394; P9BE-LABEL: fromDiffMemVarAConvftoi 1395; P9LE-LABEL: fromDiffMemVarAConvftoi 1396; P8BE-LABEL: fromDiffMemVarAConvftoi 1397; P8LE-LABEL: fromDiffMemVarAConvftoi 1398; FIXME: implement finding consecutive loads with pre-inc 1399; P9BE: lfsux 1400; P9LE: lfsux 1401; P8BE: lfsux 1402; P8LE: lfsux 1403} 1404 1405; Function Attrs: norecurse nounwind readonly 1406define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1407entry: 1408 %idxprom = sext i32 %elem to i64 1409 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1410 %0 = load float, float* %arrayidx, align 4 1411 %conv = fptosi float %0 to i32 1412 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1413 %sub = add nsw i32 %elem, -1 1414 %idxprom1 = sext i32 %sub to i64 1415 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1416 %1 = load float, float* %arrayidx2, align 4 1417 %conv3 = fptosi float %1 to i32 1418 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1419 %sub5 = add nsw i32 %elem, -2 1420 %idxprom6 = sext i32 %sub5 to i64 1421 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1422 %2 = load float, float* %arrayidx7, align 4 1423 %conv8 = fptosi float %2 to i32 1424 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1425 %sub10 = add nsw i32 %elem, -3 1426 %idxprom11 = sext i32 %sub10 to i64 1427 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1428 %3 = load float, float* %arrayidx12, align 4 1429 %conv13 = fptosi float %3 to i32 1430 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1431 ret <4 x i32> %vecinit14 1432; P9BE-LABEL: fromDiffMemVarDConvftoi 1433; P9LE-LABEL: fromDiffMemVarDConvftoi 1434; P8BE-LABEL: fromDiffMemVarDConvftoi 1435; P8LE-LABEL: fromDiffMemVarDConvftoi 1436; FIXME: implement finding consecutive loads with pre-inc 1437; P9BE: lfsux 1438; P9LE: lfsux 1439; P8BE: lfsux 1440; P8LE: lfsux 1441} 1442 1443; Function Attrs: norecurse nounwind readnone 1444define <4 x i32> @spltRegValConvftoi(float %val) { 1445entry: 1446 %conv = fptosi float %val to i32 1447 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1448 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1449 ret <4 x i32> %splat.splat 1450; P9BE-LABEL: spltRegValConvftoi 1451; P9LE-LABEL: spltRegValConvftoi 1452; P8BE-LABEL: spltRegValConvftoi 1453; P8LE-LABEL: spltRegValConvftoi 1454; P9BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1455; P9BE: xxspltw v2, vs[[REG1]], 1 1456; P9BE: blr 1457; P9LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1458; P9LE: xxspltw v2, vs[[REG1]], 1 1459; P9LE: blr 1460; P8BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1461; P8BE: xxspltw v2, vs[[REG1]], 1 1462; P8BE: blr 1463; P8LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1464; P8LE: xxspltw v2, vs[[REG1]], 1 1465; P8LE: blr 1466} 1467 1468; Function Attrs: norecurse nounwind readonly 1469define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1470entry: 1471 %0 = load float, float* %ptr, align 4 1472 %conv = fptosi float %0 to i32 1473 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1474 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1475 ret <4 x i32> %splat.splat 1476; P9BE-LABEL: spltMemValConvftoi 1477; P9LE-LABEL: spltMemValConvftoi 1478; P8BE-LABEL: spltMemValConvftoi 1479; P8LE-LABEL: spltMemValConvftoi 1480; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 1481; P9BE: xvcvspsxws v2, [[REG1]] 1482; P9LE: [[REG1:[vs0-9]+]], 0, r3 1483; P9LE: xvcvspsxws v2, [[REG1]] 1484; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 1485; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]] 1486; P8BE: xxspltw v2, vs[[REG2]], 1 1487; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 1488; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]] 1489; P8LE: xxspltw v2, vs[[REG2]], 1 1490} 1491 1492; Function Attrs: norecurse nounwind readnone 1493define <4 x i32> @spltCnstConvdtoi() { 1494entry: 1495 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1496; P9BE-LABEL: spltCnstConvdtoi 1497; P9LE-LABEL: spltCnstConvdtoi 1498; P8BE-LABEL: spltCnstConvdtoi 1499; P8LE-LABEL: spltCnstConvdtoi 1500; P9BE: vspltisw v2, 4 1501; P9BE: blr 1502; P9LE: vspltisw v2, 4 1503; P9LE: blr 1504; P8BE: vspltisw v2, 4 1505; P8BE: blr 1506; P8LE: vspltisw v2, 4 1507; P8LE: blr 1508} 1509 1510; Function Attrs: norecurse nounwind readnone 1511define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1512entry: 1513 %conv = fptosi double %a to i32 1514 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1515 %conv1 = fptosi double %b to i32 1516 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1517 %conv3 = fptosi double %c to i32 1518 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1519 %conv5 = fptosi double %d to i32 1520 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1521 ret <4 x i32> %vecinit6 1522; P9BE-LABEL: fromRegsConvdtoi 1523; P9LE-LABEL: fromRegsConvdtoi 1524; P8BE-LABEL: fromRegsConvdtoi 1525; P8LE-LABEL: fromRegsConvdtoi 1526; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1527; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1528; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1529; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1530; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1531; P9BE: xvcvspsxws v2, v2 1532; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1533; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1534; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1535; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1536; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1537; P9LE: xvcvspsxws v2, v2 1538; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1539; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1540; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1541; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1542; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1543; P8BE: xvcvspsxws v2, v2 1544; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1545; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1546; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1547; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1548; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1549; P8LE: xvcvspsxws v2, v2 1550} 1551 1552; Function Attrs: norecurse nounwind readnone 1553define <4 x i32> @fromDiffConstsConvdtoi() { 1554entry: 1555 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1556; P9BE-LABEL: fromDiffConstsConvdtoi 1557; P9LE-LABEL: fromDiffConstsConvdtoi 1558; P8BE-LABEL: fromDiffConstsConvdtoi 1559; P8LE-LABEL: fromDiffConstsConvdtoi 1560; P9BE: lxv 1561; P9BE: blr 1562; P9LE: lxv 1563; P9LE: blr 1564; P8BE: lxvw4x 1565; P8BE: blr 1566; P8LE: lvx 1567; P8LE-NOT: xxswapd 1568; P8LE: blr 1569} 1570 1571; Function Attrs: norecurse nounwind readonly 1572define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1573entry: 1574 %0 = bitcast double* %ptr to <2 x double>* 1575 %1 = load <2 x double>, <2 x double>* %0, align 8 1576 %2 = fptosi <2 x double> %1 to <2 x i32> 1577 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1578 %3 = bitcast double* %arrayidx4 to <2 x double>* 1579 %4 = load <2 x double>, <2 x double>* %3, align 8 1580 %5 = fptosi <2 x double> %4 to <2 x i32> 1581 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1582 ret <4 x i32> %vecinit9 1583; P9BE-LABEL: fromDiffMemConsAConvdtoi 1584; P9LE-LABEL: fromDiffMemConsAConvdtoi 1585; P8BE-LABEL: fromDiffMemConsAConvdtoi 1586; P8LE-LABEL: fromDiffMemConsAConvdtoi 1587; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 1588; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3) 1589; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1590; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1591; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1592; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1593; P9BE: vmrgew v2, [[REG6]], [[REG5]] 1594; P9BE: xvcvspsxws v2, v2 1595; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 1596; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3) 1597; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 1598; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 1599; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1600; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1601; P9LE: vmrgew v2, [[REG6]], [[REG5]] 1602; P9LE: xvcvspsxws v2, v2 1603; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1604; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1605; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1606; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1607; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 1608; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 1609; P8BE: vmrgew v2, [[REG6]], [[REG5]] 1610; P8BE: xvcvspsxws v2, v2 1611; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1612; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1613; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 1614; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 1615; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 1616; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 1617; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]] 1618; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]] 1619; P8LE: vmrgew v2, [[REG8]], [[REG7]] 1620; P8LE: xvcvspsxws v2, v2 1621} 1622 1623; Function Attrs: norecurse nounwind readonly 1624define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1625entry: 1626 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1627 %0 = load double, double* %arrayidx, align 8 1628 %conv = fptosi double %0 to i32 1629 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1630 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1631 %1 = load double, double* %arrayidx1, align 8 1632 %conv2 = fptosi double %1 to i32 1633 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1634 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1635 %2 = load double, double* %arrayidx4, align 8 1636 %conv5 = fptosi double %2 to i32 1637 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1638 %3 = load double, double* %ptr, align 8 1639 %conv8 = fptosi double %3 to i32 1640 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1641 ret <4 x i32> %vecinit9 1642; P9BE-LABEL: fromDiffMemConsDConvdtoi 1643; P9LE-LABEL: fromDiffMemConsDConvdtoi 1644; P8BE-LABEL: fromDiffMemConsDConvdtoi 1645; P8LE-LABEL: fromDiffMemConsDConvdtoi 1646; P9BE: lfd 1647; P9BE: lfd 1648; P9BE: lfd 1649; P9BE: lfd 1650; P9BE: xxmrghd 1651; P9BE: xxmrghd 1652; P9BE: xvcvdpsp 1653; P9BE: xvcvdpsp 1654; P9BE: vmrgew 1655; P9BE: xvcvspsxws v2 1656; P9LE: lfd 1657; P9LE: lfd 1658; P9LE: lfd 1659; P9LE: lfd 1660; P9LE: xxmrghd 1661; P9LE: xxmrghd 1662; P9LE: xvcvdpsp 1663; P9LE: xvcvdpsp 1664; P9LE: vmrgew 1665; P9LE: xvcvspsxws v2 1666; P8BE: lxsdx 1667; P8BE: lxsdx 1668; P8BE: lxsdx 1669; P8BE: lxsdx 1670; P8BE: xxmrghd 1671; P8BE: xxmrghd 1672; P8BE: xvcvdpsp 1673; P8BE: xvcvdpsp 1674; P8BE: vmrgew 1675; P8BE: xvcvspsxws v2 1676; P8LE: lxsdx 1677; P8LE: lxsdx 1678; P8LE: lxsdx 1679; P8LE: lxsdx 1680; P8LE: xxmrghd 1681; P8LE: xxmrghd 1682; P8LE: xvcvdpsp 1683; P8LE: xvcvdpsp 1684; P8LE: vmrgew 1685; P8LE: xvcvspsxws v2 1686} 1687 1688; Function Attrs: norecurse nounwind readonly 1689define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1690entry: 1691 %idxprom = sext i32 %elem to i64 1692 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1693 %0 = load double, double* %arrayidx, align 8 1694 %conv = fptosi double %0 to i32 1695 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1696 %add = add nsw i32 %elem, 1 1697 %idxprom1 = sext i32 %add to i64 1698 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1699 %1 = load double, double* %arrayidx2, align 8 1700 %conv3 = fptosi double %1 to i32 1701 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1702 %add5 = add nsw i32 %elem, 2 1703 %idxprom6 = sext i32 %add5 to i64 1704 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1705 %2 = load double, double* %arrayidx7, align 8 1706 %conv8 = fptosi double %2 to i32 1707 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1708 %add10 = add nsw i32 %elem, 3 1709 %idxprom11 = sext i32 %add10 to i64 1710 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1711 %3 = load double, double* %arrayidx12, align 8 1712 %conv13 = fptosi double %3 to i32 1713 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1714 ret <4 x i32> %vecinit14 1715; P9BE-LABEL: fromDiffMemVarAConvdtoi 1716; P9LE-LABEL: fromDiffMemVarAConvdtoi 1717; P8BE-LABEL: fromDiffMemVarAConvdtoi 1718; P8LE-LABEL: fromDiffMemVarAConvdtoi 1719; P9BE: lfdux 1720; P9BE: lfd 1721; P9BE: lfd 1722; P9BE: lfd 1723; P9BE: xxmrghd 1724; P9BE: xxmrghd 1725; P9BE: xvcvdpsp 1726; P9BE: xvcvdpsp 1727; P9BE: vmrgew 1728; P9BE: xvcvspsxws v2 1729; P9LE: lfdux 1730; P9LE: lfd 1731; P9LE: lfd 1732; P9LE: lfd 1733; P9LE: xxmrghd 1734; P9LE: xxmrghd 1735; P9LE: xvcvdpsp 1736; P9LE: xvcvdpsp 1737; P9LE: vmrgew 1738; P9LE: xvcvspsxws v2 1739; P8BE: lfdux 1740; P8BE: lxsdx 1741; P8BE: lxsdx 1742; P8BE: lxsdx 1743; P8BE: xxmrghd 1744; P8BE: xxmrghd 1745; P8BE: xvcvdpsp 1746; P8BE: xvcvdpsp 1747; P8BE: vmrgew 1748; P8BE: xvcvspsxws v2 1749; P8LE: lfdux 1750; P8LE: lxsdx 1751; P8LE: lxsdx 1752; P8LE: lxsdx 1753; P8LE: xxmrghd 1754; P8LE: xxmrghd 1755; P8LE: xvcvdpsp 1756; P8LE: xvcvdpsp 1757; P8LE: vmrgew 1758; P8LE: xvcvspsxws v2 1759} 1760 1761; Function Attrs: norecurse nounwind readonly 1762define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1763entry: 1764 %idxprom = sext i32 %elem to i64 1765 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1766 %0 = load double, double* %arrayidx, align 8 1767 %conv = fptosi double %0 to i32 1768 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1769 %sub = add nsw i32 %elem, -1 1770 %idxprom1 = sext i32 %sub to i64 1771 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1772 %1 = load double, double* %arrayidx2, align 8 1773 %conv3 = fptosi double %1 to i32 1774 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1775 %sub5 = add nsw i32 %elem, -2 1776 %idxprom6 = sext i32 %sub5 to i64 1777 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1778 %2 = load double, double* %arrayidx7, align 8 1779 %conv8 = fptosi double %2 to i32 1780 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1781 %sub10 = add nsw i32 %elem, -3 1782 %idxprom11 = sext i32 %sub10 to i64 1783 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1784 %3 = load double, double* %arrayidx12, align 8 1785 %conv13 = fptosi double %3 to i32 1786 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1787 ret <4 x i32> %vecinit14 1788; P9BE-LABEL: fromDiffMemVarDConvdtoi 1789; P9LE-LABEL: fromDiffMemVarDConvdtoi 1790; P8BE-LABEL: fromDiffMemVarDConvdtoi 1791; P8LE-LABEL: fromDiffMemVarDConvdtoi 1792; P9BE: lfdux 1793; P9BE: lfd 1794; P9BE: lfd 1795; P9BE: lfd 1796; P9BE: xxmrghd 1797; P9BE: xxmrghd 1798; P9BE: xvcvdpsp 1799; P9BE: xvcvdpsp 1800; P9BE: vmrgew 1801; P9BE: xvcvspsxws v2 1802; P9LE: lfdux 1803; P9LE: lfd 1804; P9LE: lfd 1805; P9LE: lfd 1806; P9LE: xxmrghd 1807; P9LE: xxmrghd 1808; P9LE: xvcvdpsp 1809; P9LE: xvcvdpsp 1810; P9LE: vmrgew 1811; P9LE: xvcvspsxws v2 1812; P8BE: lfdux 1813; P8BE: lxsdx 1814; P8BE: lxsdx 1815; P8BE: lxsdx 1816; P8BE: xxmrghd 1817; P8BE: xxmrghd 1818; P8BE: xvcvdpsp 1819; P8BE: xvcvdpsp 1820; P8BE: vmrgew 1821; P8BE: xvcvspsxws v2 1822; P8LE: lfdux 1823; P8LE: lxsdx 1824; P8LE: lxsdx 1825; P8LE: lxsdx 1826; P8LE: xxmrghd 1827; P8LE: xxmrghd 1828; P8LE: xvcvdpsp 1829; P8LE: xvcvdpsp 1830; P8LE: vmrgew 1831; P8LE: xvcvspsxws v2 1832} 1833 1834; Function Attrs: norecurse nounwind readnone 1835define <4 x i32> @spltRegValConvdtoi(double %val) { 1836entry: 1837 %conv = fptosi double %val to i32 1838 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1839 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1840 ret <4 x i32> %splat.splat 1841; P9BE-LABEL: spltRegValConvdtoi 1842; P9LE-LABEL: spltRegValConvdtoi 1843; P8BE-LABEL: spltRegValConvdtoi 1844; P8LE-LABEL: spltRegValConvdtoi 1845; P9BE: xscvdpsxws 1846; P9BE: xxspltw 1847; P9BE: blr 1848; P9LE: xscvdpsxws 1849; P9LE: xxspltw 1850; P9LE: blr 1851; P8BE: xscvdpsxws 1852; P8BE: xxspltw 1853; P8BE: blr 1854; P8LE: xscvdpsxws 1855; P8LE: xxspltw 1856; P8LE: blr 1857} 1858 1859; Function Attrs: norecurse nounwind readonly 1860define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 1861entry: 1862 %0 = load double, double* %ptr, align 8 1863 %conv = fptosi double %0 to i32 1864 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1865 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1866 ret <4 x i32> %splat.splat 1867; P9BE-LABEL: spltMemValConvdtoi 1868; P9LE-LABEL: spltMemValConvdtoi 1869; P8BE-LABEL: spltMemValConvdtoi 1870; P8LE-LABEL: spltMemValConvdtoi 1871; P9BE: lfd 1872; P9BE: xscvdpsxws 1873; P9BE: xxspltw 1874; P9BE: blr 1875; P9LE: lfd 1876; P9LE: xscvdpsxws 1877; P9LE: xxspltw 1878; P9LE: blr 1879; P8BE: lxsdx 1880; P8BE: xscvdpsxws 1881; P8BE: xxspltw 1882; P8BE: blr 1883; P8LE: lxsdx 1884; P8LE: xscvdpsxws 1885; P8LE: xxspltw 1886; P8LE: blr 1887} 1888; Function Attrs: norecurse nounwind readnone 1889define <4 x i32> @allZeroui() { 1890entry: 1891 ret <4 x i32> zeroinitializer 1892; P9BE-LABEL: allZeroui 1893; P9LE-LABEL: allZeroui 1894; P8BE-LABEL: allZeroui 1895; P8LE-LABEL: allZeroui 1896; P9BE: xxlxor v2, v2, v2 1897; P9BE: blr 1898; P9LE: xxlxor v2, v2, v2 1899; P9LE: blr 1900; P8BE: xxlxor v2, v2, v2 1901; P8BE: blr 1902; P8LE: xxlxor v2, v2, v2 1903; P8LE: blr 1904} 1905 1906; Function Attrs: norecurse nounwind readnone 1907define <4 x i32> @allOneui() { 1908entry: 1909 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 1910; P9BE-LABEL: allOneui 1911; P9LE-LABEL: allOneui 1912; P8BE-LABEL: allOneui 1913; P8LE-LABEL: allOneui 1914; P9BE: xxspltib v2, 255 1915; P9BE: blr 1916; P9LE: xxspltib v2, 255 1917; P9LE: blr 1918; P8BE: vspltisb v2, -1 1919; P8BE: blr 1920; P8LE: vspltisb v2, -1 1921; P8LE: blr 1922} 1923 1924; Function Attrs: norecurse nounwind readnone 1925define <4 x i32> @spltConst1ui() { 1926entry: 1927 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1928; P9BE-LABEL: spltConst1ui 1929; P9LE-LABEL: spltConst1ui 1930; P8BE-LABEL: spltConst1ui 1931; P8LE-LABEL: spltConst1ui 1932; P9BE: vspltisw v2, 1 1933; P9BE: blr 1934; P9LE: vspltisw v2, 1 1935; P9LE: blr 1936; P8BE: vspltisw v2, 1 1937; P8BE: blr 1938; P8LE: vspltisw v2, 1 1939; P8LE: blr 1940} 1941 1942; Function Attrs: norecurse nounwind readnone 1943define <4 x i32> @spltConst16kui() { 1944entry: 1945 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 1946; P9BE-LABEL: spltConst16kui 1947; P9LE-LABEL: spltConst16kui 1948; P8BE-LABEL: spltConst16kui 1949; P8LE-LABEL: spltConst16kui 1950; P9BE: vspltisw v2, -15 1951; P9BE: vsrw v2, v2, v2 1952; P9BE: blr 1953; P9LE: vspltisw v2, -15 1954; P9LE: vsrw v2, v2, v2 1955; P9LE: blr 1956; P8BE: vspltisw v2, -15 1957; P8BE: vsrw v2, v2, v2 1958; P8BE: blr 1959; P8LE: vspltisw v2, -15 1960; P8LE: vsrw v2, v2, v2 1961; P8LE: blr 1962} 1963 1964; Function Attrs: norecurse nounwind readnone 1965define <4 x i32> @spltConst32kui() { 1966entry: 1967 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1968; P9BE-LABEL: spltConst32kui 1969; P9LE-LABEL: spltConst32kui 1970; P8BE-LABEL: spltConst32kui 1971; P8LE-LABEL: spltConst32kui 1972; P9BE: vspltisw v2, -16 1973; P9BE: vsrw v2, v2, v2 1974; P9BE: blr 1975; P9LE: vspltisw v2, -16 1976; P9LE: vsrw v2, v2, v2 1977; P9LE: blr 1978; P8BE: vspltisw v2, -16 1979; P8BE: vsrw v2, v2, v2 1980; P8BE: blr 1981; P8LE: vspltisw v2, -16 1982; P8LE: vsrw v2, v2, v2 1983; P8LE: blr 1984} 1985 1986; Function Attrs: norecurse nounwind readnone 1987define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 1988entry: 1989 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 1990 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 1991 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 1992 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 1993 ret <4 x i32> %vecinit3 1994; P9BE-LABEL: fromRegsui 1995; P9LE-LABEL: fromRegsui 1996; P8BE-LABEL: fromRegsui 1997; P8LE-LABEL: fromRegsui 1998; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 1999; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 2000; P9BE: vmrgow v2, [[REG1]], [[REG2]] 2001; P9BE: blr 2002; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 2003; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 2004; P9LE: vmrgow v2, [[REG2]], [[REG1]] 2005; P9LE: blr 2006; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 2007; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 2008; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 2009; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 2010; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 2011; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 2012; P8BE: vmrgow v2, [[REG5]], [[REG6]] 2013; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 2014; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 2015; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 2016; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 2017; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 2018; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 2019; P8LE: vmrgow v2, [[REG6]], [[REG5]] 2020} 2021 2022; Function Attrs: norecurse nounwind readnone 2023define <4 x i32> @fromDiffConstsui() { 2024entry: 2025 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2026; P9BE-LABEL: fromDiffConstsui 2027; P9LE-LABEL: fromDiffConstsui 2028; P8BE-LABEL: fromDiffConstsui 2029; P8LE-LABEL: fromDiffConstsui 2030; P9BE: lxv 2031; P9BE: blr 2032; P9LE: lxv 2033; P9LE: blr 2034; P8BE: lxvw4x 2035; P8BE: blr 2036; P8LE: lvx 2037; P8LE-NOT: xxswapd 2038; P8LE: blr 2039} 2040 2041; Function Attrs: norecurse nounwind readonly 2042define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2043entry: 2044 %0 = load i32, i32* %arr, align 4 2045 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2046 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2047 %1 = load i32, i32* %arrayidx1, align 4 2048 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2049 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2050 %2 = load i32, i32* %arrayidx3, align 4 2051 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2052 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2053 %3 = load i32, i32* %arrayidx5, align 4 2054 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2055 ret <4 x i32> %vecinit6 2056; P9BE-LABEL: fromDiffMemConsAui 2057; P9LE-LABEL: fromDiffMemConsAui 2058; P8BE-LABEL: fromDiffMemConsAui 2059; P8LE-LABEL: fromDiffMemConsAui 2060; P9BE: lxv 2061; P9BE: blr 2062; P9LE: lxv 2063; P9LE: blr 2064; P8BE: lxvw4x 2065; P8BE: blr 2066; P8LE: lxvd2x 2067; P8LE: xxswapd 2068; P8LE: blr 2069} 2070 2071; Function Attrs: norecurse nounwind readonly 2072define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2073entry: 2074 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2075 %0 = load i32, i32* %arrayidx, align 4 2076 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2077 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2078 %1 = load i32, i32* %arrayidx1, align 4 2079 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2080 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2081 %2 = load i32, i32* %arrayidx3, align 4 2082 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2083 %3 = load i32, i32* %arr, align 4 2084 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2085 ret <4 x i32> %vecinit6 2086; P9BE-LABEL: fromDiffMemConsDui 2087; P9LE-LABEL: fromDiffMemConsDui 2088; P8BE-LABEL: fromDiffMemConsDui 2089; P8LE-LABEL: fromDiffMemConsDui 2090; P9BE: lxv 2091; P9BE: lxv 2092; P9BE: vperm 2093; P9BE: blr 2094; P9LE: lxv 2095; P9LE: lxv 2096; P9LE: vperm 2097; P9LE: blr 2098; P8BE: lxvw4x 2099; P8BE: lxvw4x 2100; P8BE: vperm 2101; P8BE: blr 2102; P8LE: lxvd2x 2103; P8LE-DAG: lvx 2104; P8LE-NOT: xxswapd 2105; P8LE: xxswapd 2106; P8LE: vperm 2107; P8LE: blr 2108} 2109 2110; Function Attrs: norecurse nounwind readonly 2111define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2112entry: 2113 %idxprom = sext i32 %elem to i64 2114 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2115 %0 = load i32, i32* %arrayidx, align 4 2116 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2117 %add = add nsw i32 %elem, 1 2118 %idxprom1 = sext i32 %add to i64 2119 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2120 %1 = load i32, i32* %arrayidx2, align 4 2121 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2122 %add4 = add nsw i32 %elem, 2 2123 %idxprom5 = sext i32 %add4 to i64 2124 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2125 %2 = load i32, i32* %arrayidx6, align 4 2126 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2127 %add8 = add nsw i32 %elem, 3 2128 %idxprom9 = sext i32 %add8 to i64 2129 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2130 %3 = load i32, i32* %arrayidx10, align 4 2131 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2132 ret <4 x i32> %vecinit11 2133; P9BE-LABEL: fromDiffMemVarAui 2134; P9LE-LABEL: fromDiffMemVarAui 2135; P8BE-LABEL: fromDiffMemVarAui 2136; P8LE-LABEL: fromDiffMemVarAui 2137; P9BE: sldi r4, r4, 2 2138; P9BE: lxvx v2, r3, r4 2139; P9BE: blr 2140; P9LE: sldi r4, r4, 2 2141; P9LE: lxvx v2, r3, r4 2142; P9LE: blr 2143; P8BE: sldi r4, r4, 2 2144; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 2145; P8BE: blr 2146; P8LE: sldi r4, r4, 2 2147; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 2148; P8LE: xxswapd 2149; P8LE: blr 2150} 2151 2152; Function Attrs: norecurse nounwind readonly 2153define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2154entry: 2155 %idxprom = sext i32 %elem to i64 2156 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2157 %0 = load i32, i32* %arrayidx, align 4 2158 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2159 %sub = add nsw i32 %elem, -1 2160 %idxprom1 = sext i32 %sub to i64 2161 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2162 %1 = load i32, i32* %arrayidx2, align 4 2163 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2164 %sub4 = add nsw i32 %elem, -2 2165 %idxprom5 = sext i32 %sub4 to i64 2166 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2167 %2 = load i32, i32* %arrayidx6, align 4 2168 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2169 %sub8 = add nsw i32 %elem, -3 2170 %idxprom9 = sext i32 %sub8 to i64 2171 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2172 %3 = load i32, i32* %arrayidx10, align 4 2173 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2174 ret <4 x i32> %vecinit11 2175; P9BE-LABEL: fromDiffMemVarDui 2176; P9LE-LABEL: fromDiffMemVarDui 2177; P8BE-LABEL: fromDiffMemVarDui 2178; P8LE-LABEL: fromDiffMemVarDui 2179; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2 2180; P9BE-DAG: lxv {{v[0-9]+}}, -12(r3) 2181; P9BE-DAG: lxv 2182; P9BE: vperm 2183; P9BE: blr 2184; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2 2185; P9LE-DAG: lxv {{v[0-9]+}}, -12(r3) 2186; P9LE-DAG: lxv 2187; P9LE: vperm 2188; P9LE: blr 2189; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 2190; P8BE-DAG: lxvw4x {{v[0-9]+}}, r3 2191; P8BE-DAG: lxvw4x 2192; P8BE: vperm 2193; P8BE: blr 2194; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 2195; P8LE-DAG: lvx 2196; P8LE-DAG: lvx 2197; P8LE: vperm 2198; P8LE: blr 2199} 2200 2201; Function Attrs: norecurse nounwind readonly 2202define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2203entry: 2204 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2205 %0 = load i32, i32* %arrayidx, align 4 2206 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2207 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2208 %1 = load i32, i32* %arrayidx1, align 4 2209 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2210 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2211 %2 = load i32, i32* %arrayidx3, align 4 2212 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2213 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2214 %3 = load i32, i32* %arrayidx5, align 4 2215 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2216 ret <4 x i32> %vecinit6 2217; P9BE-LABEL: fromRandMemConsui 2218; P9LE-LABEL: fromRandMemConsui 2219; P8BE-LABEL: fromRandMemConsui 2220; P8LE-LABEL: fromRandMemConsui 2221; P9BE: lwz 2222; P9BE: lwz 2223; P9BE: lwz 2224; P9BE: lwz 2225; P9BE: mtvsrdd 2226; P9BE: mtvsrdd 2227; P9BE: vmrgow 2228; P9LE: lwz 2229; P9LE: lwz 2230; P9LE: lwz 2231; P9LE: lwz 2232; P9LE: mtvsrdd 2233; P9LE: mtvsrdd 2234; P9LE: vmrgow 2235; P8BE: lwz 2236; P8BE: lwz 2237; P8BE: lwz 2238; P8BE: lwz 2239; P8BE: mtvsrwz 2240; P8BE: mtvsrwz 2241; P8BE: mtvsrwz 2242; P8BE: mtvsrwz 2243; P8BE: xxmrghd 2244; P8BE: xxmrghd 2245; P8BE: vmrgow 2246; P8LE: lwz 2247; P8LE: lwz 2248; P8LE: lwz 2249; P8LE: lwz 2250; P8LE: mtvsrwz 2251; P8LE: mtvsrwz 2252; P8LE: mtvsrwz 2253; P8LE: mtvsrwz 2254; P8LE: xxmrghd 2255; P8LE: xxmrghd 2256; P8LE: vmrgow 2257} 2258 2259; Function Attrs: norecurse nounwind readonly 2260define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2261entry: 2262 %add = add nsw i32 %elem, 4 2263 %idxprom = sext i32 %add to i64 2264 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2265 %0 = load i32, i32* %arrayidx, align 4 2266 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2267 %add1 = add nsw i32 %elem, 1 2268 %idxprom2 = sext i32 %add1 to i64 2269 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2270 %1 = load i32, i32* %arrayidx3, align 4 2271 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2272 %add5 = add nsw i32 %elem, 2 2273 %idxprom6 = sext i32 %add5 to i64 2274 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2275 %2 = load i32, i32* %arrayidx7, align 4 2276 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2277 %add9 = add nsw i32 %elem, 8 2278 %idxprom10 = sext i32 %add9 to i64 2279 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2280 %3 = load i32, i32* %arrayidx11, align 4 2281 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2282 ret <4 x i32> %vecinit12 2283; P9BE-LABEL: fromRandMemVarui 2284; P9LE-LABEL: fromRandMemVarui 2285; P8BE-LABEL: fromRandMemVarui 2286; P8LE-LABEL: fromRandMemVarui 2287; P9BE: sldi r4, r4, 2 2288; P9BE: lwz 2289; P9BE: lwz 2290; P9BE: lwz 2291; P9BE: lwz 2292; P9BE: mtvsrdd 2293; P9BE: mtvsrdd 2294; P9BE: vmrgow 2295; P9LE: sldi r4, r4, 2 2296; P9LE: lwz 2297; P9LE: lwz 2298; P9LE: lwz 2299; P9LE: lwz 2300; P9LE: mtvsrdd 2301; P9LE: mtvsrdd 2302; P9LE: vmrgow 2303; P8BE: sldi r4, r4, 2 2304; P8BE: lwz 2305; P8BE: lwz 2306; P8BE: lwz 2307; P8BE: lwz 2308; P8BE: mtvsrwz 2309; P8BE: mtvsrwz 2310; P8BE: mtvsrwz 2311; P8BE: mtvsrwz 2312; P8BE: xxmrghd 2313; P8BE: xxmrghd 2314; P8BE: vmrgow 2315; P8LE: sldi r4, r4, 2 2316; P8LE: lwz 2317; P8LE: lwz 2318; P8LE: lwz 2319; P8LE: lwz 2320; P8LE: mtvsrwz 2321; P8LE: mtvsrwz 2322; P8LE: mtvsrwz 2323; P8LE: mtvsrwz 2324; P8LE: xxmrghd 2325; P8LE: xxmrghd 2326; P8LE: vmrgow 2327} 2328 2329; Function Attrs: norecurse nounwind readnone 2330define <4 x i32> @spltRegValui(i32 zeroext %val) { 2331entry: 2332 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2333 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2334 ret <4 x i32> %splat.splat 2335; P9BE-LABEL: spltRegValui 2336; P9LE-LABEL: spltRegValui 2337; P8BE-LABEL: spltRegValui 2338; P8LE-LABEL: spltRegValui 2339; P9BE: mtvsrws v2, r3 2340; P9BE: blr 2341; P9LE: mtvsrws v2, r3 2342; P9LE: blr 2343; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 2344; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2345; P8BE: blr 2346; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 2347; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2348; P8LE: blr 2349} 2350 2351; Function Attrs: norecurse nounwind readonly 2352define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2353entry: 2354 %0 = load i32, i32* %ptr, align 4 2355 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2356 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2357 ret <4 x i32> %splat.splat 2358; P9BE-LABEL: spltMemValui 2359; P9LE-LABEL: spltMemValui 2360; P8BE-LABEL: spltMemValui 2361; P8LE-LABEL: spltMemValui 2362; P9BE: lxvwsx v2, 0, r3 2363; P9BE: blr 2364; P9LE: lxvwsx v2, 0, r3 2365; P9LE: blr 2366; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 2367; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2368; P8BE: blr 2369; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 2370; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2371; P8LE: blr 2372} 2373 2374; Function Attrs: norecurse nounwind readnone 2375define <4 x i32> @spltCnstConvftoui() { 2376entry: 2377 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2378; P9BE-LABEL: spltCnstConvftoui 2379; P9LE-LABEL: spltCnstConvftoui 2380; P8BE-LABEL: spltCnstConvftoui 2381; P8LE-LABEL: spltCnstConvftoui 2382; P9BE: vspltisw v2, 4 2383; P9BE: blr 2384; P9LE: vspltisw v2, 4 2385; P9LE: blr 2386; P8BE: vspltisw v2, 4 2387; P8BE: blr 2388; P8LE: vspltisw v2, 4 2389; P8LE: blr 2390} 2391 2392; Function Attrs: norecurse nounwind readnone 2393define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2394entry: 2395 %conv = fptoui float %a to i32 2396 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2397 %conv1 = fptoui float %b to i32 2398 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2399 %conv3 = fptoui float %c to i32 2400 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2401 %conv5 = fptoui float %d to i32 2402 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2403 ret <4 x i32> %vecinit6 2404; P9BE-LABEL: fromRegsConvftoui 2405; P9LE-LABEL: fromRegsConvftoui 2406; P8BE-LABEL: fromRegsConvftoui 2407; P8LE-LABEL: fromRegsConvftoui 2408; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2409; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2410; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2411; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2412; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2413; P9BE: xvcvspuxws v2, v2 2414; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2415; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2416; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2417; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2418; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2419; P9LE: xvcvspuxws v2, v2 2420; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2421; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2422; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2423; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2424; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2425; P8BE: xvcvspuxws v2, v2 2426; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2427; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2428; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2429; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2430; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2431; P8LE: xvcvspuxws v2, v2 2432} 2433 2434; Function Attrs: norecurse nounwind readnone 2435define <4 x i32> @fromDiffConstsConvftoui() { 2436entry: 2437 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2438; P9BE-LABEL: fromDiffConstsConvftoui 2439; P9LE-LABEL: fromDiffConstsConvftoui 2440; P8BE-LABEL: fromDiffConstsConvftoui 2441; P8LE-LABEL: fromDiffConstsConvftoui 2442; P9BE: lxv 2443; P9BE: blr 2444; P9LE: lxv 2445; P9LE: blr 2446; P8BE: lxvw4x 2447; P8BE: blr 2448; P8LE: lvx 2449; P8LE-NOT: xxswapd 2450; P8LE: blr 2451} 2452 2453; Function Attrs: norecurse nounwind readonly 2454define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2455entry: 2456 %0 = bitcast float* %ptr to <4 x float>* 2457 %1 = load <4 x float>, <4 x float>* %0, align 4 2458 %2 = fptoui <4 x float> %1 to <4 x i32> 2459 ret <4 x i32> %2 2460; P9BE-LABEL: fromDiffMemConsAConvftoui 2461; P9LE-LABEL: fromDiffMemConsAConvftoui 2462; P8BE-LABEL: fromDiffMemConsAConvftoui 2463; P8LE-LABEL: fromDiffMemConsAConvftoui 2464; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 2465; P9BE: xvcvspuxws v2, [[REG1]] 2466; P9BE: blr 2467; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 2468; P9LE: xvcvspuxws v2, [[REG1]] 2469; P9LE: blr 2470; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 2471; P8BE: xvcvspuxws v2, [[REG1]] 2472; P8BE: blr 2473; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2474; P8LE: xxswapd v2, [[REG1]] 2475; P8LE: xvcvspuxws v2, v2 2476; P8LE: blr 2477} 2478 2479; Function Attrs: norecurse nounwind readonly 2480define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2481entry: 2482 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 2483 %0 = load float, float* %arrayidx, align 4 2484 %conv = fptoui float %0 to i32 2485 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2486 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 2487 %1 = load float, float* %arrayidx1, align 4 2488 %conv2 = fptoui float %1 to i32 2489 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2490 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 2491 %2 = load float, float* %arrayidx4, align 4 2492 %conv5 = fptoui float %2 to i32 2493 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2494 %3 = load float, float* %ptr, align 4 2495 %conv8 = fptoui float %3 to i32 2496 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2497 ret <4 x i32> %vecinit9 2498; P9BE-LABEL: fromDiffMemConsDConvftoui 2499; P9LE-LABEL: fromDiffMemConsDConvftoui 2500; P8BE-LABEL: fromDiffMemConsDConvftoui 2501; P8LE-LABEL: fromDiffMemConsDConvftoui 2502; P9BE: lxv 2503; P9BE: lxv 2504; P9BE: vperm 2505; P9BE: xvcvspuxws 2506; P9BE: blr 2507; P9LE: lxv 2508; P9LE: lxv 2509; P9LE: vperm 2510; P9LE: xvcvspuxws 2511; P9LE: blr 2512; P8BE: lxvw4x 2513; P8BE: lxvw4x 2514; P8BE: vperm 2515; P8BE: xvcvspuxws 2516; P8BE: blr 2517; P8LE-DAG: lxvd2x 2518; P8LE-DAG: lvx 2519; P8LE: xxswapd 2520; P8LE: vperm 2521; P8LE: xvcvspuxws 2522; P8LE: blr 2523} 2524 2525; Function Attrs: norecurse nounwind readonly 2526define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2527entry: 2528 %idxprom = sext i32 %elem to i64 2529 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2530 %0 = load float, float* %arrayidx, align 4 2531 %conv = fptoui float %0 to i32 2532 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2533 %add = add nsw i32 %elem, 1 2534 %idxprom1 = sext i32 %add to i64 2535 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2536 %1 = load float, float* %arrayidx2, align 4 2537 %conv3 = fptoui float %1 to i32 2538 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2539 %add5 = add nsw i32 %elem, 2 2540 %idxprom6 = sext i32 %add5 to i64 2541 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2542 %2 = load float, float* %arrayidx7, align 4 2543 %conv8 = fptoui float %2 to i32 2544 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2545 %add10 = add nsw i32 %elem, 3 2546 %idxprom11 = sext i32 %add10 to i64 2547 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2548 %3 = load float, float* %arrayidx12, align 4 2549 %conv13 = fptoui float %3 to i32 2550 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2551 ret <4 x i32> %vecinit14 2552; P9BE-LABEL: fromDiffMemVarAConvftoui 2553; P9LE-LABEL: fromDiffMemVarAConvftoui 2554; P8BE-LABEL: fromDiffMemVarAConvftoui 2555; P8LE-LABEL: fromDiffMemVarAConvftoui 2556; FIXME: implement finding consecutive loads with pre-inc 2557; P9BE: lfsux 2558; P9LE: lfsux 2559; P8BE: lfsux 2560; P8LE: lfsux 2561} 2562 2563; Function Attrs: norecurse nounwind readonly 2564define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2565entry: 2566 %idxprom = sext i32 %elem to i64 2567 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2568 %0 = load float, float* %arrayidx, align 4 2569 %conv = fptoui float %0 to i32 2570 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2571 %sub = add nsw i32 %elem, -1 2572 %idxprom1 = sext i32 %sub to i64 2573 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2574 %1 = load float, float* %arrayidx2, align 4 2575 %conv3 = fptoui float %1 to i32 2576 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2577 %sub5 = add nsw i32 %elem, -2 2578 %idxprom6 = sext i32 %sub5 to i64 2579 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2580 %2 = load float, float* %arrayidx7, align 4 2581 %conv8 = fptoui float %2 to i32 2582 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2583 %sub10 = add nsw i32 %elem, -3 2584 %idxprom11 = sext i32 %sub10 to i64 2585 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2586 %3 = load float, float* %arrayidx12, align 4 2587 %conv13 = fptoui float %3 to i32 2588 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2589 ret <4 x i32> %vecinit14 2590; P9BE-LABEL: fromDiffMemVarDConvftoui 2591; P9LE-LABEL: fromDiffMemVarDConvftoui 2592; P8BE-LABEL: fromDiffMemVarDConvftoui 2593; P8LE-LABEL: fromDiffMemVarDConvftoui 2594; FIXME: implement finding consecutive loads with pre-inc 2595; P9BE: lfsux 2596; P9LE: lfsux 2597; P8BE: lfsux 2598; P8LE: lfsux 2599} 2600 2601; Function Attrs: norecurse nounwind readnone 2602define <4 x i32> @spltRegValConvftoui(float %val) { 2603entry: 2604 %conv = fptoui float %val to i32 2605 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2606 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2607 ret <4 x i32> %splat.splat 2608; P9BE-LABEL: spltRegValConvftoui 2609; P9LE-LABEL: spltRegValConvftoui 2610; P8BE-LABEL: spltRegValConvftoui 2611; P8LE-LABEL: spltRegValConvftoui 2612; P9BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2613; P9BE: xxspltw v2, vs[[REG1]], 1 2614; P9BE: blr 2615; P9LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2616; P9LE: xxspltw v2, vs[[REG1]], 1 2617; P9LE: blr 2618; P8BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2619; P8BE: xxspltw v2, vs[[REG1]], 1 2620; P8BE: blr 2621; P8LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2622; P8LE: xxspltw v2, vs[[REG1]], 1 2623; P8LE: blr 2624} 2625 2626; Function Attrs: norecurse nounwind readonly 2627define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 2628entry: 2629 %0 = load float, float* %ptr, align 4 2630 %conv = fptoui float %0 to i32 2631 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2632 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2633 ret <4 x i32> %splat.splat 2634; P9BE-LABEL: spltMemValConvftoui 2635; P9LE-LABEL: spltMemValConvftoui 2636; P8BE-LABEL: spltMemValConvftoui 2637; P8LE-LABEL: spltMemValConvftoui 2638; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 2639; P9BE: xvcvspuxws v2, [[REG1]] 2640; P9LE: [[REG1:[vs0-9]+]], 0, r3 2641; P9LE: xvcvspuxws v2, [[REG1]] 2642; P8BE: lxsspx [[REG1:f[0-9]+]], 0, r3 2643; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]] 2644; P8BE: xxspltw v2, vs[[REG2]], 1 2645; P8LE: lxsspx [[REG1:f[0-9]+]], 0, r3 2646; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]] 2647; P8LE: xxspltw v2, vs[[REG2]], 1 2648} 2649 2650; Function Attrs: norecurse nounwind readnone 2651define <4 x i32> @spltCnstConvdtoui() { 2652entry: 2653 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2654; P9BE-LABEL: spltCnstConvdtoui 2655; P9LE-LABEL: spltCnstConvdtoui 2656; P8BE-LABEL: spltCnstConvdtoui 2657; P8LE-LABEL: spltCnstConvdtoui 2658; P9BE: vspltisw v2, 4 2659; P9BE: blr 2660; P9LE: vspltisw v2, 4 2661; P9LE: blr 2662; P8BE: vspltisw v2, 4 2663; P8BE: blr 2664; P8LE: vspltisw v2, 4 2665; P8LE: blr 2666} 2667 2668; Function Attrs: norecurse nounwind readnone 2669define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 2670entry: 2671 %conv = fptoui double %a to i32 2672 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2673 %conv1 = fptoui double %b to i32 2674 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2675 %conv3 = fptoui double %c to i32 2676 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2677 %conv5 = fptoui double %d to i32 2678 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2679 ret <4 x i32> %vecinit6 2680; P9BE-LABEL: fromRegsConvdtoui 2681; P9LE-LABEL: fromRegsConvdtoui 2682; P8BE-LABEL: fromRegsConvdtoui 2683; P8LE-LABEL: fromRegsConvdtoui 2684; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2685; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2686; P9BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2687; P9BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2688; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2689; P9BE: xvcvspuxws v2, v2 2690; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2691; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2692; P9LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2693; P9LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2694; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2695; P9LE: xvcvspuxws v2, v2 2696; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2697; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2698; P8BE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2699; P8BE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2700; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2701; P8BE: xvcvspuxws v2, v2 2702; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2703; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2704; P8LE-DAG: xvcvdpsp [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2705; P8LE-DAG: xvcvdpsp [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2706; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2707; P8LE: xvcvspuxws v2, v2 2708} 2709 2710; Function Attrs: norecurse nounwind readnone 2711define <4 x i32> @fromDiffConstsConvdtoui() { 2712entry: 2713 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2714; P9BE-LABEL: fromDiffConstsConvdtoui 2715; P9LE-LABEL: fromDiffConstsConvdtoui 2716; P8BE-LABEL: fromDiffConstsConvdtoui 2717; P8LE-LABEL: fromDiffConstsConvdtoui 2718; P9BE: lxv 2719; P9BE: blr 2720; P9LE: lxv 2721; P9LE: blr 2722; P8BE: lxvw4x 2723; P8BE: blr 2724; P8LE: lvx 2725; P8LE-NOT: xxswapd 2726; P8LE: blr 2727} 2728 2729; Function Attrs: norecurse nounwind readonly 2730define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 2731entry: 2732 %0 = bitcast double* %ptr to <2 x double>* 2733 %1 = load <2 x double>, <2 x double>* %0, align 8 2734 %2 = fptoui <2 x double> %1 to <2 x i32> 2735 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 2736 %3 = bitcast double* %arrayidx4 to <2 x double>* 2737 %4 = load <2 x double>, <2 x double>* %3, align 8 2738 %5 = fptoui <2 x double> %4 to <2 x i32> 2739 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2740 ret <4 x i32> %vecinit9 2741; P9BE-LABEL: fromDiffMemConsAConvdtoui 2742; P9LE-LABEL: fromDiffMemConsAConvdtoui 2743; P8BE-LABEL: fromDiffMemConsAConvdtoui 2744; P8LE-LABEL: fromDiffMemConsAConvdtoui 2745; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 2746; P9BE: lxv [[REG2:[vs0-9]+]], 16(r3) 2747; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2748; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2749; P9BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2750; P9BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2751; P9BE: vmrgew v2, [[REG6]], [[REG5]] 2752; P9BE: xvcvspuxws v2, v2 2753; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 2754; P9LE: lxv [[REG2:[vs0-9]+]], 16(r3) 2755; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 2756; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 2757; P9LE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2758; P9LE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2759; P9LE: vmrgew v2, [[REG6]], [[REG5]] 2760; P9LE: xvcvspuxws v2, v2 2761; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2762; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2763; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2764; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2765; P8BE-DAG: xvcvdpsp [[REG5:[vs0-9]+]], [[REG3]] 2766; P8BE-DAG: xvcvdpsp [[REG6:[vs0-9]+]], [[REG4]] 2767; P8BE: vmrgew v2, [[REG6]], [[REG5]] 2768; P8BE: xvcvspuxws v2, v2 2769; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2770; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2771; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 2772; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 2773; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 2774; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 2775; P8LE-DAG: xvcvdpsp [[REG7:[vs0-9]+]], [[REG5]] 2776; P8LE-DAG: xvcvdpsp [[REG8:[vs0-9]+]], [[REG6]] 2777; P8LE: vmrgew v2, [[REG8]], [[REG7]] 2778; P8LE: xvcvspuxws v2, v2 2779} 2780 2781; Function Attrs: norecurse nounwind readonly 2782define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 2783entry: 2784 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2785 %0 = load double, double* %arrayidx, align 8 2786 %conv = fptoui double %0 to i32 2787 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2788 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2789 %1 = load double, double* %arrayidx1, align 8 2790 %conv2 = fptoui double %1 to i32 2791 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2792 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2793 %2 = load double, double* %arrayidx4, align 8 2794 %conv5 = fptoui double %2 to i32 2795 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2796 %3 = load double, double* %ptr, align 8 2797 %conv8 = fptoui double %3 to i32 2798 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2799 ret <4 x i32> %vecinit9 2800; P9BE-LABEL: fromDiffMemConsDConvdtoui 2801; P9LE-LABEL: fromDiffMemConsDConvdtoui 2802; P8BE-LABEL: fromDiffMemConsDConvdtoui 2803; P8LE-LABEL: fromDiffMemConsDConvdtoui 2804; P9BE: lfd 2805; P9BE: lfd 2806; P9BE: lfd 2807; P9BE: lfd 2808; P9BE: xxmrghd 2809; P9BE: xxmrghd 2810; P9BE: xvcvdpsp 2811; P9BE: xvcvdpsp 2812; P9BE: vmrgew 2813; P9BE: xvcvspuxws v2 2814; P9LE: lfd 2815; P9LE: lfd 2816; P9LE: lfd 2817; P9LE: lfd 2818; P9LE: xxmrghd 2819; P9LE: xxmrghd 2820; P9LE: xvcvdpsp 2821; P9LE: xvcvdpsp 2822; P9LE: vmrgew 2823; P9LE: xvcvspuxws v2 2824; P8BE: lxsdx 2825; P8BE: lxsdx 2826; P8BE: lxsdx 2827; P8BE: lxsdx 2828; P8BE: xxmrghd 2829; P8BE: xxmrghd 2830; P8BE: xvcvdpsp 2831; P8BE: xvcvdpsp 2832; P8BE: vmrgew 2833; P8BE: xvcvspuxws v2 2834; P8LE: lxsdx 2835; P8LE: lxsdx 2836; P8LE: lxsdx 2837; P8LE: lxsdx 2838; P8LE: xxmrghd 2839; P8LE: xxmrghd 2840; P8LE: xvcvdpsp 2841; P8LE: xvcvdpsp 2842; P8LE: vmrgew 2843; P8LE: xvcvspuxws v2 2844} 2845 2846; Function Attrs: norecurse nounwind readonly 2847define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2848entry: 2849 %idxprom = sext i32 %elem to i64 2850 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2851 %0 = load double, double* %arrayidx, align 8 2852 %conv = fptoui double %0 to i32 2853 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2854 %add = add nsw i32 %elem, 1 2855 %idxprom1 = sext i32 %add to i64 2856 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2857 %1 = load double, double* %arrayidx2, align 8 2858 %conv3 = fptoui double %1 to i32 2859 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2860 %add5 = add nsw i32 %elem, 2 2861 %idxprom6 = sext i32 %add5 to i64 2862 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2863 %2 = load double, double* %arrayidx7, align 8 2864 %conv8 = fptoui double %2 to i32 2865 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2866 %add10 = add nsw i32 %elem, 3 2867 %idxprom11 = sext i32 %add10 to i64 2868 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2869 %3 = load double, double* %arrayidx12, align 8 2870 %conv13 = fptoui double %3 to i32 2871 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2872 ret <4 x i32> %vecinit14 2873; P9BE-LABEL: fromDiffMemVarAConvdtoui 2874; P9LE-LABEL: fromDiffMemVarAConvdtoui 2875; P8BE-LABEL: fromDiffMemVarAConvdtoui 2876; P8LE-LABEL: fromDiffMemVarAConvdtoui 2877; P9BE: lfdux 2878; P9BE: lfd 2879; P9BE: lfd 2880; P9BE: lfd 2881; P9BE: xxmrghd 2882; P9BE: xxmrghd 2883; P9BE: xvcvdpsp 2884; P9BE: xvcvdpsp 2885; P9BE: vmrgew 2886; P9BE: xvcvspuxws v2 2887; P9LE: lfdux 2888; P9LE: lfd 2889; P9LE: lfd 2890; P9LE: lfd 2891; P9LE: xxmrghd 2892; P9LE: xxmrghd 2893; P9LE: xvcvdpsp 2894; P9LE: xvcvdpsp 2895; P9LE: vmrgew 2896; P9LE: xvcvspuxws v2 2897; P8BE: lfdux 2898; P8BE: lxsdx 2899; P8BE: lxsdx 2900; P8BE: lxsdx 2901; P8BE: xxmrghd 2902; P8BE: xxmrghd 2903; P8BE: xvcvdpsp 2904; P8BE: xvcvdpsp 2905; P8BE: vmrgew 2906; P8BE: xvcvspuxws v2 2907; P8LE: lfdux 2908; P8LE: lxsdx 2909; P8LE: lxsdx 2910; P8LE: lxsdx 2911; P8LE: xxmrghd 2912; P8LE: xxmrghd 2913; P8LE: xvcvdpsp 2914; P8LE: xvcvdpsp 2915; P8LE: vmrgew 2916; P8LE: xvcvspuxws v2 2917} 2918 2919; Function Attrs: norecurse nounwind readonly 2920define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2921entry: 2922 %idxprom = sext i32 %elem to i64 2923 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2924 %0 = load double, double* %arrayidx, align 8 2925 %conv = fptoui double %0 to i32 2926 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2927 %sub = add nsw i32 %elem, -1 2928 %idxprom1 = sext i32 %sub to i64 2929 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2930 %1 = load double, double* %arrayidx2, align 8 2931 %conv3 = fptoui double %1 to i32 2932 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2933 %sub5 = add nsw i32 %elem, -2 2934 %idxprom6 = sext i32 %sub5 to i64 2935 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2936 %2 = load double, double* %arrayidx7, align 8 2937 %conv8 = fptoui double %2 to i32 2938 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2939 %sub10 = add nsw i32 %elem, -3 2940 %idxprom11 = sext i32 %sub10 to i64 2941 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2942 %3 = load double, double* %arrayidx12, align 8 2943 %conv13 = fptoui double %3 to i32 2944 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2945 ret <4 x i32> %vecinit14 2946; P9BE-LABEL: fromDiffMemVarDConvdtoui 2947; P9LE-LABEL: fromDiffMemVarDConvdtoui 2948; P8BE-LABEL: fromDiffMemVarDConvdtoui 2949; P8LE-LABEL: fromDiffMemVarDConvdtoui 2950; P9BE: lfdux 2951; P9BE: lfd 2952; P9BE: lfd 2953; P9BE: lfd 2954; P9BE: xxmrghd 2955; P9BE: xxmrghd 2956; P9BE: xvcvdpsp 2957; P9BE: xvcvdpsp 2958; P9BE: vmrgew 2959; P9BE: xvcvspuxws v2 2960; P9LE: lfdux 2961; P9LE: lfd 2962; P9LE: lfd 2963; P9LE: lfd 2964; P9LE: xxmrghd 2965; P9LE: xxmrghd 2966; P9LE: xvcvdpsp 2967; P9LE: xvcvdpsp 2968; P9LE: vmrgew 2969; P9LE: xvcvspuxws v2 2970; P8BE: lfdux 2971; P8BE: lxsdx 2972; P8BE: lxsdx 2973; P8BE: lxsdx 2974; P8BE: xxmrghd 2975; P8BE: xxmrghd 2976; P8BE: xvcvdpsp 2977; P8BE: xvcvdpsp 2978; P8BE: vmrgew 2979; P8BE: xvcvspuxws v2 2980; P8LE: lfdux 2981; P8LE: lxsdx 2982; P8LE: lxsdx 2983; P8LE: lxsdx 2984; P8LE: xxmrghd 2985; P8LE: xxmrghd 2986; P8LE: xvcvdpsp 2987; P8LE: xvcvdpsp 2988; P8LE: vmrgew 2989; P8LE: xvcvspuxws v2 2990} 2991 2992; Function Attrs: norecurse nounwind readnone 2993define <4 x i32> @spltRegValConvdtoui(double %val) { 2994entry: 2995 %conv = fptoui double %val to i32 2996 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2997 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2998 ret <4 x i32> %splat.splat 2999; P9BE-LABEL: spltRegValConvdtoui 3000; P9LE-LABEL: spltRegValConvdtoui 3001; P8BE-LABEL: spltRegValConvdtoui 3002; P8LE-LABEL: spltRegValConvdtoui 3003; P9BE: xscvdpuxws 3004; P9BE: xxspltw 3005; P9BE: blr 3006; P9LE: xscvdpuxws 3007; P9LE: xxspltw 3008; P9LE: blr 3009; P8BE: xscvdpuxws 3010; P8BE: xxspltw 3011; P8BE: blr 3012; P8LE: xscvdpuxws 3013; P8LE: xxspltw 3014; P8LE: blr 3015} 3016 3017; Function Attrs: norecurse nounwind readonly 3018define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3019entry: 3020 %0 = load double, double* %ptr, align 8 3021 %conv = fptoui double %0 to i32 3022 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3023 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3024 ret <4 x i32> %splat.splat 3025; P9BE-LABEL: spltMemValConvdtoui 3026; P9LE-LABEL: spltMemValConvdtoui 3027; P8BE-LABEL: spltMemValConvdtoui 3028; P8LE-LABEL: spltMemValConvdtoui 3029; P9BE: lfd 3030; P9BE: xscvdpuxws 3031; P9BE: xxspltw 3032; P9BE: blr 3033; P9LE: lfd 3034; P9LE: xscvdpuxws 3035; P9LE: xxspltw 3036; P9LE: blr 3037; P8BE: lxsdx 3038; P8BE: xscvdpuxws 3039; P8BE: xxspltw 3040; P8BE: blr 3041; P8LE: lxsdx 3042; P8LE: xscvdpuxws 3043; P8LE: xxspltw 3044; P8LE: blr 3045} 3046; Function Attrs: norecurse nounwind readnone 3047define <2 x i64> @allZeroll() { 3048entry: 3049 ret <2 x i64> zeroinitializer 3050; P9BE-LABEL: allZeroll 3051; P9LE-LABEL: allZeroll 3052; P8BE-LABEL: allZeroll 3053; P8LE-LABEL: allZeroll 3054; P9BE: xxlxor v2, v2, v2 3055; P9BE: blr 3056; P9LE: xxlxor v2, v2, v2 3057; P9LE: blr 3058; P8BE: xxlxor v2, v2, v2 3059; P8BE: blr 3060; P8LE: xxlxor v2, v2, v2 3061; P8LE: blr 3062} 3063 3064; Function Attrs: norecurse nounwind readnone 3065define <2 x i64> @allOnell() { 3066entry: 3067 ret <2 x i64> <i64 -1, i64 -1> 3068; P9BE-LABEL: allOnell 3069; P9LE-LABEL: allOnell 3070; P8BE-LABEL: allOnell 3071; P8LE-LABEL: allOnell 3072; P9BE: xxspltib v2, 255 3073; P9BE: blr 3074; P9LE: xxspltib v2, 255 3075; P9LE: blr 3076; P8BE: vspltisb v2, -1 3077; P8BE: blr 3078; P8LE: vspltisb v2, -1 3079; P8LE: blr 3080} 3081 3082; Function Attrs: norecurse nounwind readnone 3083define <2 x i64> @spltConst1ll() { 3084entry: 3085 ret <2 x i64> <i64 1, i64 1> 3086; P9BE-LABEL: spltConst1ll 3087; P9LE-LABEL: spltConst1ll 3088; P8BE-LABEL: spltConst1ll 3089; P8LE-LABEL: spltConst1ll 3090; P9BE: lxv 3091; P9BE: blr 3092; P9LE: lxv 3093; P9LE: blr 3094; P8BE: lxvd2x 3095; P8BE: blr 3096; P8LE: lxvd2x 3097; P8LE: blr 3098} 3099 3100; Function Attrs: norecurse nounwind readnone 3101define <2 x i64> @spltConst16kll() { 3102entry: 3103 ret <2 x i64> <i64 32767, i64 32767> 3104; P9BE-LABEL: spltConst16kll 3105; P9LE-LABEL: spltConst16kll 3106; P8BE-LABEL: spltConst16kll 3107; P8LE-LABEL: spltConst16kll 3108; P9BE: lxv 3109; P9BE: blr 3110; P9LE: lxv 3111; P9LE: blr 3112; P8BE: lxvd2x 3113; P8BE: blr 3114; P8LE: lxvd2x 3115; P8LE: blr 3116} 3117 3118; Function Attrs: norecurse nounwind readnone 3119define <2 x i64> @spltConst32kll() { 3120entry: 3121 ret <2 x i64> <i64 65535, i64 65535> 3122; P9BE-LABEL: spltConst32kll 3123; P9LE-LABEL: spltConst32kll 3124; P8BE-LABEL: spltConst32kll 3125; P8LE-LABEL: spltConst32kll 3126; P9BE: lxv 3127; P9BE: blr 3128; P9LE: lxv 3129; P9LE: blr 3130; P8BE: lxvd2x 3131; P8BE: blr 3132; P8LE: lxvd2x 3133; P8LE: blr 3134} 3135 3136; Function Attrs: norecurse nounwind readnone 3137define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3138entry: 3139 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3140 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3141 ret <2 x i64> %vecinit1 3142; P9BE-LABEL: fromRegsll 3143; P9LE-LABEL: fromRegsll 3144; P8BE-LABEL: fromRegsll 3145; P8LE-LABEL: fromRegsll 3146; P9BE: mtvsrdd v2, r3, r4 3147; P9BE: blr 3148; P9LE: mtvsrdd v2, r4, r3 3149; P9LE: blr 3150; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3151; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3152; P8BE: xxmrghd v2 3153; P8BE: blr 3154; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3155; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3156; P8LE: xxmrghd v2 3157; P8LE: blr 3158} 3159 3160; Function Attrs: norecurse nounwind readnone 3161define <2 x i64> @fromDiffConstsll() { 3162entry: 3163 ret <2 x i64> <i64 242, i64 -113> 3164; P9BE-LABEL: fromDiffConstsll 3165; P9LE-LABEL: fromDiffConstsll 3166; P8BE-LABEL: fromDiffConstsll 3167; P8LE-LABEL: fromDiffConstsll 3168; P9BE: lxv 3169; P9BE: blr 3170; P9LE: lxv 3171; P9LE: blr 3172; P8BE: lxvd2x 3173; P8BE: blr 3174; P8LE: lxvd2x 3175; P8LE: blr 3176} 3177 3178; Function Attrs: norecurse nounwind readonly 3179define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3180entry: 3181 %0 = load i64, i64* %arr, align 8 3182 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3183 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3184 %1 = load i64, i64* %arrayidx1, align 8 3185 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3186 ret <2 x i64> %vecinit2 3187; P9BE-LABEL: fromDiffMemConsAll 3188; P9LE-LABEL: fromDiffMemConsAll 3189; P8BE-LABEL: fromDiffMemConsAll 3190; P8LE-LABEL: fromDiffMemConsAll 3191; P9BE: lxv v2 3192; P9BE: blr 3193; P9LE: lxv v2 3194; P9LE: blr 3195; P8BE: lxvd2x v2 3196; P8BE: blr 3197; P8LE: lxvd2x 3198; P8LE: xxswapd v2 3199; P8LE: blr 3200} 3201 3202; Function Attrs: norecurse nounwind readonly 3203define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3204entry: 3205 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3206 %0 = load i64, i64* %arrayidx, align 8 3207 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3208 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3209 %1 = load i64, i64* %arrayidx1, align 8 3210 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3211 ret <2 x i64> %vecinit2 3212; P9BE-LABEL: fromDiffMemConsDll 3213; P9LE-LABEL: fromDiffMemConsDll 3214; P8BE-LABEL: fromDiffMemConsDll 3215; P8LE-LABEL: fromDiffMemConsDll 3216; P9BE: lxv v2 3217; P9BE: blr 3218; P9LE: lxv 3219; P9LE: xxswapd v2 3220; P9LE: blr 3221; P8BE: lxvd2x 3222; P8BE: xxswapd v2 3223; P8BE-NEXT: blr 3224; P8LE: lxvd2x v2 3225; P8LE-NEXT: blr 3226} 3227 3228; Function Attrs: norecurse nounwind readonly 3229define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 3230entry: 3231 %idxprom = sext i32 %elem to i64 3232 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3233 %0 = load i64, i64* %arrayidx, align 8 3234 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3235 %add = add nsw i32 %elem, 1 3236 %idxprom1 = sext i32 %add to i64 3237 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3238 %1 = load i64, i64* %arrayidx2, align 8 3239 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3240 ret <2 x i64> %vecinit3 3241; P9BE-LABEL: fromDiffMemVarAll 3242; P9LE-LABEL: fromDiffMemVarAll 3243; P8BE-LABEL: fromDiffMemVarAll 3244; P8LE-LABEL: fromDiffMemVarAll 3245; P9BE: sldi 3246; P9BE: lxvx v2 3247; P9BE-NEXT: blr 3248; P9LE: sldi 3249; P9LE: lxvx v2 3250; P9LE-NEXT: blr 3251; P8BE: sldi 3252; P8BE: lxvd2x v2 3253; P8BE-NEXT: blr 3254; P8LE: sldi 3255; P8LE: lxvd2x 3256; P8LE: xxswapd v2 3257; P8LE-NEXT: blr 3258} 3259 3260; Function Attrs: norecurse nounwind readonly 3261define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 3262entry: 3263 %idxprom = sext i32 %elem to i64 3264 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3265 %0 = load i64, i64* %arrayidx, align 8 3266 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3267 %sub = add nsw i32 %elem, -1 3268 %idxprom1 = sext i32 %sub to i64 3269 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3270 %1 = load i64, i64* %arrayidx2, align 8 3271 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3272 ret <2 x i64> %vecinit3 3273; P9BE-LABEL: fromDiffMemVarDll 3274; P9LE-LABEL: fromDiffMemVarDll 3275; P8BE-LABEL: fromDiffMemVarDll 3276; P8LE-LABEL: fromDiffMemVarDll 3277; P9BE: sldi 3278; P9BE: lxv 3279; P9BE: xxswapd v2 3280; P9BE-NEXT: blr 3281; P9LE: sldi 3282; P9LE: lxv 3283; P9LE: xxswapd v2 3284; P9LE-NEXT: blr 3285; P8BE: sldi 3286; P8BE: lxvd2x 3287; P8BE: xxswapd v2 3288; P8BE-NEXT: blr 3289; P8LE: sldi 3290; P8LE: lxvd2x v2 3291; P8LE-NEXT: blr 3292} 3293 3294; Function Attrs: norecurse nounwind readonly 3295define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 3296entry: 3297 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 3298 %0 = load i64, i64* %arrayidx, align 8 3299 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3300 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 3301 %1 = load i64, i64* %arrayidx1, align 8 3302 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3303 ret <2 x i64> %vecinit2 3304; P9BE-LABEL: fromRandMemConsll 3305; P9LE-LABEL: fromRandMemConsll 3306; P8BE-LABEL: fromRandMemConsll 3307; P8LE-LABEL: fromRandMemConsll 3308; P9BE: ld 3309; P9BE: ld 3310; P9BE: mtvsrdd v2 3311; P9BE-NEXT: blr 3312; P9LE: ld 3313; P9LE: ld 3314; P9LE: mtvsrdd v2 3315; P9LE-NEXT: blr 3316; P8BE: ld 3317; P8BE: ld 3318; P8BE-DAG: mtvsrd 3319; P8BE-DAG: mtvsrd 3320; P8BE: xxmrghd v2 3321; P8BE-NEXT: blr 3322; P8LE: ld 3323; P8LE: ld 3324; P8LE-DAG: mtvsrd 3325; P8LE-DAG: mtvsrd 3326; P8LE: xxmrghd v2 3327; P8LE-NEXT: blr 3328} 3329 3330; Function Attrs: norecurse nounwind readonly 3331define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 3332entry: 3333 %add = add nsw i32 %elem, 4 3334 %idxprom = sext i32 %add to i64 3335 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3336 %0 = load i64, i64* %arrayidx, align 8 3337 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3338 %add1 = add nsw i32 %elem, 1 3339 %idxprom2 = sext i32 %add1 to i64 3340 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 3341 %1 = load i64, i64* %arrayidx3, align 8 3342 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3343 ret <2 x i64> %vecinit4 3344; P9BE-LABEL: fromRandMemVarll 3345; P9LE-LABEL: fromRandMemVarll 3346; P8BE-LABEL: fromRandMemVarll 3347; P8LE-LABEL: fromRandMemVarll 3348; P9BE: sldi 3349; P9BE: ld 3350; P9BE: ld 3351; P9BE: mtvsrdd v2 3352; P9BE-NEXT: blr 3353; P9LE: sldi 3354; P9LE: ld 3355; P9LE: ld 3356; P9LE: mtvsrdd v2 3357; P9LE-NEXT: blr 3358; P8BE: sldi 3359; P8BE: ld 3360; P8BE: ld 3361; P8BE: mtvsrd 3362; P8BE: mtvsrd 3363; P8BE: xxmrghd v2 3364; P8BE-NEXT: blr 3365; P8LE: sldi 3366; P8LE: ld 3367; P8LE: ld 3368; P8LE: mtvsrd 3369; P8LE: mtvsrd 3370; P8LE: xxmrghd v2 3371; P8LE-NEXT: blr 3372} 3373 3374; Function Attrs: norecurse nounwind readnone 3375define <2 x i64> @spltRegValll(i64 %val) { 3376entry: 3377 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 3378 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3379 ret <2 x i64> %splat.splat 3380; P9BE-LABEL: spltRegValll 3381; P9LE-LABEL: spltRegValll 3382; P8BE-LABEL: spltRegValll 3383; P8LE-LABEL: spltRegValll 3384; P9BE: mtvsrdd v2, r3, r3 3385; P9BE-NEXT: blr 3386; P9LE: mtvsrdd v2, r3, r3 3387; P9LE-NEXT: blr 3388; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3389; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3390; P8BE-NEXT: blr 3391; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3392; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3393; P8LE-NEXT: blr 3394} 3395 3396; Function Attrs: norecurse nounwind readonly 3397define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 3398entry: 3399 %0 = load i64, i64* %ptr, align 8 3400 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 3401 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3402 ret <2 x i64> %splat.splat 3403; P9BE-LABEL: spltMemValll 3404; P9LE-LABEL: spltMemValll 3405; P8BE-LABEL: spltMemValll 3406; P8LE-LABEL: spltMemValll 3407; P9BE: lxvdsx v2 3408; P9BE-NEXT: blr 3409; P9LE: lxvdsx v2 3410; P9LE-NEXT: blr 3411; P8BE: lxvdsx v2 3412; P8BE-NEXT: blr 3413; P8LE: lxvdsx v2 3414; P8LE-NEXT: blr 3415} 3416 3417; Function Attrs: norecurse nounwind readnone 3418define <2 x i64> @spltCnstConvftoll() { 3419entry: 3420 ret <2 x i64> <i64 4, i64 4> 3421; P9BE-LABEL: spltCnstConvftoll 3422; P9LE-LABEL: spltCnstConvftoll 3423; P8BE-LABEL: spltCnstConvftoll 3424; P8LE-LABEL: spltCnstConvftoll 3425; P9BE: lxv 3426; P9BE: blr 3427; P9LE: lxv 3428; P9LE: blr 3429; P8BE: lxvd2x 3430; P8BE: blr 3431; P8LE: lxvd2x 3432; P8LE: blr 3433} 3434 3435; Function Attrs: norecurse nounwind readnone 3436define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 3437entry: 3438 %conv = fptosi float %a to i64 3439 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3440 %conv1 = fptosi float %b to i64 3441 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3442 ret <2 x i64> %vecinit2 3443; P9BE-LABEL: fromRegsConvftoll 3444; P9LE-LABEL: fromRegsConvftoll 3445; P8BE-LABEL: fromRegsConvftoll 3446; P8LE-LABEL: fromRegsConvftoll 3447; P9BE: xxmrghd 3448; P9BE: xvcvdpsxds v2 3449; P9BE-NEXT: blr 3450; P9LE: xxmrghd 3451; P9LE: xvcvdpsxds v2 3452; P9LE-NEXT: blr 3453; P8BE: xxmrghd 3454; P8BE: xvcvdpsxds v2 3455; P8BE-NEXT: blr 3456; P8LE: xxmrghd 3457; P8LE: xvcvdpsxds v2 3458; P8LE-NEXT: blr 3459} 3460 3461; Function Attrs: norecurse nounwind readnone 3462define <2 x i64> @fromDiffConstsConvftoll() { 3463entry: 3464 ret <2 x i64> <i64 24, i64 234> 3465; P9BE-LABEL: fromDiffConstsConvftoll 3466; P9LE-LABEL: fromDiffConstsConvftoll 3467; P8BE-LABEL: fromDiffConstsConvftoll 3468; P8LE-LABEL: fromDiffConstsConvftoll 3469; P9BE: lxv v2 3470; P9BE: blr 3471; P9LE: lxv v2 3472; P9LE: blr 3473; P8BE: lxvd2x v2 3474; P8BE: blr 3475; P8LE: lxvd2x 3476; P8LE: xxswapd v2 3477; P8LE: blr 3478} 3479 3480; Function Attrs: norecurse nounwind readonly 3481define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 3482entry: 3483 %0 = load float, float* %ptr, align 4 3484 %conv = fptosi float %0 to i64 3485 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3486 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 3487 %1 = load float, float* %arrayidx1, align 4 3488 %conv2 = fptosi float %1 to i64 3489 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3490 ret <2 x i64> %vecinit3 3491; P9BE-LABEL: fromDiffMemConsAConvftoll 3492; P9LE-LABEL: fromDiffMemConsAConvftoll 3493; P8BE-LABEL: fromDiffMemConsAConvftoll 3494; P8LE-LABEL: fromDiffMemConsAConvftoll 3495; P9BE: lfs 3496; P9BE: lfs 3497; P9BE: xxmrghd 3498; P9BE-NEXT: xvcvdpsxds v2 3499; P9BE-NEXT: blr 3500; P9LE: lfs 3501; P9LE: lfs 3502; P9LE: xxmrghd 3503; P9LE-NEXT: xvcvdpsxds v2 3504; P9LE-NEXT: blr 3505; P8BE: lxsspx 3506; P8BE: lxsspx 3507; P8BE: xxmrghd 3508; P8BE-NEXT: xvcvdpsxds v2 3509; P8BE-NEXT: blr 3510; P8LE: lxsspx 3511; P8LE: lxsspx 3512; P8LE: xxmrghd 3513; P8LE-NEXT: xvcvdpsxds v2 3514; P8LE-NEXT: blr 3515} 3516 3517; Function Attrs: norecurse nounwind readonly 3518define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 3519entry: 3520 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3521 %0 = load float, float* %arrayidx, align 4 3522 %conv = fptosi float %0 to i64 3523 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3524 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3525 %1 = load float, float* %arrayidx1, align 4 3526 %conv2 = fptosi float %1 to i64 3527 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3528 ret <2 x i64> %vecinit3 3529; P9BE-LABEL: fromDiffMemConsDConvftoll 3530; P9LE-LABEL: fromDiffMemConsDConvftoll 3531; P8BE-LABEL: fromDiffMemConsDConvftoll 3532; P8LE-LABEL: fromDiffMemConsDConvftoll 3533; P9BE: lfs 3534; P9BE: lfs 3535; P9BE: xxmrghd 3536; P9BE-NEXT: xvcvdpsxds v2 3537; P9BE-NEXT: blr 3538; P9LE: lfs 3539; P9LE: lfs 3540; P9LE: xxmrghd 3541; P9LE-NEXT: xvcvdpsxds v2 3542; P9LE-NEXT: blr 3543; P8BE: lxsspx 3544; P8BE: lxsspx 3545; P8BE: xxmrghd 3546; P8BE-NEXT: xvcvdpsxds v2 3547; P8BE-NEXT: blr 3548; P8LE: lxsspx 3549; P8LE: lxsspx 3550; P8LE: xxmrghd 3551; P8LE-NEXT: xvcvdpsxds v2 3552; P8LE-NEXT: blr 3553} 3554 3555; Function Attrs: norecurse nounwind readonly 3556define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3557entry: 3558 %idxprom = sext i32 %elem to i64 3559 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3560 %0 = load float, float* %arrayidx, align 4 3561 %conv = fptosi float %0 to i64 3562 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3563 %add = add nsw i32 %elem, 1 3564 %idxprom1 = sext i32 %add to i64 3565 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3566 %1 = load float, float* %arrayidx2, align 4 3567 %conv3 = fptosi float %1 to i64 3568 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3569 ret <2 x i64> %vecinit4 3570; P9BE-LABEL: fromDiffMemVarAConvftoll 3571; P9LE-LABEL: fromDiffMemVarAConvftoll 3572; P8BE-LABEL: fromDiffMemVarAConvftoll 3573; P8LE-LABEL: fromDiffMemVarAConvftoll 3574; P9BE: sldi 3575; P9BE: lfsux 3576; P9BE: lfs 3577; P9BE: xxmrghd 3578; P9BE-NEXT: xvcvdpsxds v2 3579; P9BE-NEXT: blr 3580; P9LE: sldi 3581; P9LE: lfsux 3582; P9LE: lfs 3583; P9LE: xxmrghd 3584; P9LE-NEXT: xvcvdpsxds v2 3585; P9LE-NEXT: blr 3586; P8BE: sldi 3587; P8BE: lfsux 3588; P8BE: lxsspx 3589; P8BE: xxmrghd 3590; P8BE-NEXT: xvcvdpsxds v2 3591; P8BE-NEXT: blr 3592; P8LE: sldi 3593; P8LE: lfsux 3594; P8LE: lxsspx 3595; P8LE: xxmrghd 3596; P8LE-NEXT: xvcvdpsxds v2 3597; P8LE-NEXT: blr 3598} 3599 3600; Function Attrs: norecurse nounwind readonly 3601define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3602entry: 3603 %idxprom = sext i32 %elem to i64 3604 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3605 %0 = load float, float* %arrayidx, align 4 3606 %conv = fptosi float %0 to i64 3607 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3608 %sub = add nsw i32 %elem, -1 3609 %idxprom1 = sext i32 %sub to i64 3610 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3611 %1 = load float, float* %arrayidx2, align 4 3612 %conv3 = fptosi float %1 to i64 3613 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3614 ret <2 x i64> %vecinit4 3615; P9BE-LABEL: fromDiffMemVarDConvftoll 3616; P9LE-LABEL: fromDiffMemVarDConvftoll 3617; P8BE-LABEL: fromDiffMemVarDConvftoll 3618; P8LE-LABEL: fromDiffMemVarDConvftoll 3619; P9BE: sldi 3620; P9BE: lfsux 3621; P9BE: lfs 3622; P9BE: xxmrghd 3623; P9BE-NEXT: xvcvdpsxds v2 3624; P9BE-NEXT: blr 3625; P9LE: sldi 3626; P9LE: lfsux 3627; P9LE: lfs 3628; P9LE: xxmrghd 3629; P9LE-NEXT: xvcvdpsxds v2 3630; P9LE-NEXT: blr 3631; P8BE: sldi 3632; P8BE: lfsux 3633; P8BE: lxsspx 3634; P8BE: xxmrghd 3635; P8BE-NEXT: xvcvdpsxds v2 3636; P8BE-NEXT: blr 3637; P8LE: sldi 3638; P8LE: lfsux 3639; P8LE: lxsspx 3640; P8LE: xxmrghd 3641; P8LE-NEXT: xvcvdpsxds v2 3642; P8LE-NEXT: blr 3643} 3644 3645; Function Attrs: norecurse nounwind readnone 3646define <2 x i64> @spltRegValConvftoll(float %val) { 3647entry: 3648 %conv = fptosi float %val to i64 3649 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3650 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3651 ret <2 x i64> %splat.splat 3652; P9BE-LABEL: spltRegValConvftoll 3653; P9LE-LABEL: spltRegValConvftoll 3654; P8BE-LABEL: spltRegValConvftoll 3655; P8LE-LABEL: spltRegValConvftoll 3656; P9BE: xscvdpsxds 3657; P9BE-NEXT: xxspltd v2 3658; P9BE-NEXT: blr 3659; P9LE: xscvdpsxds 3660; P9LE-NEXT: xxspltd v2 3661; P9LE-NEXT: blr 3662; P8BE: xscvdpsxds 3663; P8BE-NEXT: xxspltd v2 3664; P8BE-NEXT: blr 3665; P8LE: xscvdpsxds 3666; P8LE-NEXT: xxspltd v2 3667; P8LE-NEXT: blr 3668} 3669 3670; Function Attrs: norecurse nounwind readonly 3671define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 3672entry: 3673 %0 = load float, float* %ptr, align 4 3674 %conv = fptosi float %0 to i64 3675 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3676 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3677 ret <2 x i64> %splat.splat 3678; P9BE-LABEL: spltMemValConvftoll 3679; P9LE-LABEL: spltMemValConvftoll 3680; P8BE-LABEL: spltMemValConvftoll 3681; P8LE-LABEL: spltMemValConvftoll 3682; P9BE: lfs 3683; P9BE-NEXT: xscvdpsxds 3684; P9BE-NEXT: xxspltd v2 3685; P9BE-NEXT: blr 3686; P9LE: lfs 3687; P9LE-NEXT: xscvdpsxds 3688; P9LE-NEXT: xxspltd v2 3689; P9LE-NEXT: blr 3690; P8BE: lxsspx 3691; P8BE-NEXT: xscvdpsxds 3692; P8BE-NEXT: xxspltd v2 3693; P8BE-NEXT: blr 3694; P8LE: lxsspx 3695; P8LE-NEXT: xscvdpsxds 3696; P8LE-NEXT: xxspltd v2 3697; P8LE-NEXT: blr 3698} 3699 3700; Function Attrs: norecurse nounwind readnone 3701define <2 x i64> @spltCnstConvdtoll() { 3702entry: 3703 ret <2 x i64> <i64 4, i64 4> 3704; P9BE-LABEL: spltCnstConvdtoll 3705; P9LE-LABEL: spltCnstConvdtoll 3706; P8BE-LABEL: spltCnstConvdtoll 3707; P8LE-LABEL: spltCnstConvdtoll 3708; P9BE: lxv 3709; P9BE: blr 3710; P9LE: lxv 3711; P9LE: blr 3712; P8BE: lxvd2x 3713; P8BE: blr 3714; P8LE: lxvd2x 3715; P8LE: blr 3716} 3717 3718; Function Attrs: norecurse nounwind readnone 3719define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 3720entry: 3721 %conv = fptosi double %a to i64 3722 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3723 %conv1 = fptosi double %b to i64 3724 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3725 ret <2 x i64> %vecinit2 3726; P9BE-LABEL: fromRegsConvdtoll 3727; P9LE-LABEL: fromRegsConvdtoll 3728; P8BE-LABEL: fromRegsConvdtoll 3729; P8LE-LABEL: fromRegsConvdtoll 3730; P9BE: xxmrghd 3731; P9BE-NEXT: xvcvdpsxds 3732; P9BE-NEXT: blr 3733; P9LE: xxmrghd 3734; P9LE-NEXT: xvcvdpsxds 3735; P9LE-NEXT: blr 3736; P8BE: xxmrghd 3737; P8BE-NEXT: xvcvdpsxds 3738; P8BE-NEXT: blr 3739; P8LE: xxmrghd 3740; P8LE-NEXT: xvcvdpsxds 3741; P8LE-NEXT: blr 3742} 3743 3744; Function Attrs: norecurse nounwind readnone 3745define <2 x i64> @fromDiffConstsConvdtoll() { 3746entry: 3747 ret <2 x i64> <i64 24, i64 234> 3748; P9BE-LABEL: fromDiffConstsConvdtoll 3749; P9LE-LABEL: fromDiffConstsConvdtoll 3750; P8BE-LABEL: fromDiffConstsConvdtoll 3751; P8LE-LABEL: fromDiffConstsConvdtoll 3752; P9BE: lxv 3753; P9BE: blr 3754; P9LE: lxv 3755; P9LE: blr 3756; P8BE: lxvd2x 3757; P8BE: blr 3758; P8LE: lxvd2x 3759; P8LE: blr 3760} 3761 3762; Function Attrs: norecurse nounwind readonly 3763define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 3764entry: 3765 %0 = bitcast double* %ptr to <2 x double>* 3766 %1 = load <2 x double>, <2 x double>* %0, align 8 3767 %2 = fptosi <2 x double> %1 to <2 x i64> 3768 ret <2 x i64> %2 3769; P9BE-LABEL: fromDiffMemConsAConvdtoll 3770; P9LE-LABEL: fromDiffMemConsAConvdtoll 3771; P8BE-LABEL: fromDiffMemConsAConvdtoll 3772; P8LE-LABEL: fromDiffMemConsAConvdtoll 3773; P9BE: lxv 3774; P9BE-NEXT: xvcvdpsxds v2 3775; P9BE-NEXT: blr 3776; P9LE: lxv 3777; P9LE-NEXT: xvcvdpsxds v2 3778; P9LE-NEXT: blr 3779; P8BE: lxvd2x 3780; P8BE-NEXT: xvcvdpsxds v2 3781; P8BE-NEXT: blr 3782; P8LE: lxvd2x 3783; P8LE: xxswapd 3784; P8LE-NEXT: xvcvdpsxds v2 3785; P8LE-NEXT: blr 3786} 3787 3788; Function Attrs: norecurse nounwind readonly 3789define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 3790entry: 3791 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3792 %0 = load double, double* %arrayidx, align 8 3793 %conv = fptosi double %0 to i64 3794 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3795 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3796 %1 = load double, double* %arrayidx1, align 8 3797 %conv2 = fptosi double %1 to i64 3798 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3799 ret <2 x i64> %vecinit3 3800; P9BE-LABEL: fromDiffMemConsDConvdtoll 3801; P9LE-LABEL: fromDiffMemConsDConvdtoll 3802; P8BE-LABEL: fromDiffMemConsDConvdtoll 3803; P8LE-LABEL: fromDiffMemConsDConvdtoll 3804; P9BE: lxv 3805; P9BE-NEXT: xxswapd 3806; P9BE-NEXT: xvcvdpsxds v2 3807; P9BE-NEXT: blr 3808; P9LE: lxv 3809; P9LE-NEXT: xxswapd 3810; P9LE-NEXT: xvcvdpsxds v2 3811; P9LE-NEXT: blr 3812; P8BE: lxvd2x 3813; P8BE-NEXT: xxswapd 3814; P8BE-NEXT: xvcvdpsxds v2 3815; P8BE-NEXT: blr 3816; P8LE: lxvd2x 3817; P8LE-NEXT: xvcvdpsxds v2 3818; P8LE-NEXT: blr 3819} 3820 3821; Function Attrs: norecurse nounwind readonly 3822define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3823entry: 3824 %idxprom = sext i32 %elem to i64 3825 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3826 %0 = load double, double* %arrayidx, align 8 3827 %conv = fptosi double %0 to i64 3828 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3829 %add = add nsw i32 %elem, 1 3830 %idxprom1 = sext i32 %add to i64 3831 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3832 %1 = load double, double* %arrayidx2, align 8 3833 %conv3 = fptosi double %1 to i64 3834 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3835 ret <2 x i64> %vecinit4 3836; P9BE-LABEL: fromDiffMemVarAConvdtoll 3837; P9LE-LABEL: fromDiffMemVarAConvdtoll 3838; P8BE-LABEL: fromDiffMemVarAConvdtoll 3839; P8LE-LABEL: fromDiffMemVarAConvdtoll 3840; P9BE: sldi 3841; P9BE: lxvx 3842; P9BE-NEXT: xvcvdpsxds v2 3843; P9BE-NEXT: blr 3844; P9LE: sldi 3845; P9LE: lxvx 3846; P9LE-NEXT: xvcvdpsxds v2 3847; P9LE-NEXT: blr 3848; P8BE: sldi 3849; P8BE: lxvd2x 3850; P8BE-NEXT: xvcvdpsxds v2 3851; P8BE-NEXT: blr 3852; P8LE: sldi 3853; P8LE: lxvd2x 3854; P8LE-NEXT: xxswapd 3855; P8LE-NEXT: xvcvdpsxds v2 3856; P8LE-NEXT: blr 3857} 3858 3859; Function Attrs: norecurse nounwind readonly 3860define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3861entry: 3862 %idxprom = sext i32 %elem to i64 3863 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3864 %0 = load double, double* %arrayidx, align 8 3865 %conv = fptosi double %0 to i64 3866 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3867 %sub = add nsw i32 %elem, -1 3868 %idxprom1 = sext i32 %sub to i64 3869 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3870 %1 = load double, double* %arrayidx2, align 8 3871 %conv3 = fptosi double %1 to i64 3872 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3873 ret <2 x i64> %vecinit4 3874; P9BE-LABEL: fromDiffMemVarDConvdtoll 3875; P9LE-LABEL: fromDiffMemVarDConvdtoll 3876; P8BE-LABEL: fromDiffMemVarDConvdtoll 3877; P8LE-LABEL: fromDiffMemVarDConvdtoll 3878; P9BE: sldi 3879; P9BE: lxv 3880; P9BE-NEXT: xxswapd 3881; P9BE-NEXT: xvcvdpsxds v2 3882; P9BE-NEXT: blr 3883; P9LE: sldi 3884; P9LE: lxv 3885; P9LE-NEXT: xxswapd 3886; P9LE-NEXT: xvcvdpsxds v2 3887; P9LE-NEXT: blr 3888; P8BE: sldi 3889; P8BE: lxvd2x 3890; P8BE-NEXT: xxswapd 3891; P8BE-NEXT: xvcvdpsxds v2 3892; P8BE-NEXT: blr 3893; P8LE: sldi 3894; P8LE: lxvd2x 3895; P8LE-NEXT: xvcvdpsxds v2 3896; P8LE-NEXT: blr 3897} 3898 3899; Function Attrs: norecurse nounwind readnone 3900define <2 x i64> @spltRegValConvdtoll(double %val) { 3901entry: 3902 %conv = fptosi double %val to i64 3903 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3904 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3905 ret <2 x i64> %splat.splat 3906; P9BE-LABEL: spltRegValConvdtoll 3907; P9LE-LABEL: spltRegValConvdtoll 3908; P8BE-LABEL: spltRegValConvdtoll 3909; P8LE-LABEL: spltRegValConvdtoll 3910; P9BE: xscvdpsxds 3911; P9BE-NEXT: xxspltd v2 3912; P9BE-NEXT: blr 3913; P9LE: xscvdpsxds 3914; P9LE-NEXT: xxspltd v2 3915; P9LE-NEXT: blr 3916; P8BE: xscvdpsxds 3917; P8BE-NEXT: xxspltd v2 3918; P8BE-NEXT: blr 3919; P8LE: xscvdpsxds 3920; P8LE-NEXT: xxspltd v2 3921; P8LE-NEXT: blr 3922} 3923 3924; Function Attrs: norecurse nounwind readonly 3925define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 3926entry: 3927 %0 = load double, double* %ptr, align 8 3928 %conv = fptosi double %0 to i64 3929 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3930 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3931 ret <2 x i64> %splat.splat 3932; P9BE-LABEL: spltMemValConvdtoll 3933; P9LE-LABEL: spltMemValConvdtoll 3934; P8BE-LABEL: spltMemValConvdtoll 3935; P8LE-LABEL: spltMemValConvdtoll 3936; P9BE: lxvdsx 3937; P9BE-NEXT: xvcvdpsxds 3938; P9BE-NEXT: blr 3939; P9LE: lxvdsx 3940; P9LE-NEXT: xvcvdpsxds 3941; P9LE-NEXT: blr 3942; P8BE: lxvdsx 3943; P8BE-NEXT: xvcvdpsxds 3944; P8BE-NEXT: blr 3945; P8LE: lxvdsx 3946; P8LE-NEXT: xvcvdpsxds 3947; P8LE-NEXT: blr 3948} 3949 3950; Function Attrs: norecurse nounwind readnone 3951define <2 x i64> @allZeroull() { 3952entry: 3953 ret <2 x i64> zeroinitializer 3954; P9BE-LABEL: allZeroull 3955; P9LE-LABEL: allZeroull 3956; P8BE-LABEL: allZeroull 3957; P8LE-LABEL: allZeroull 3958; P9BE: xxlxor v2, v2, v2 3959; P9BE: blr 3960; P9LE: xxlxor v2, v2, v2 3961; P9LE: blr 3962; P8BE: xxlxor v2, v2, v2 3963; P8BE: blr 3964; P8LE: xxlxor v2, v2, v2 3965; P8LE: blr 3966} 3967 3968; Function Attrs: norecurse nounwind readnone 3969define <2 x i64> @allOneull() { 3970entry: 3971 ret <2 x i64> <i64 -1, i64 -1> 3972; P9BE-LABEL: allOneull 3973; P9LE-LABEL: allOneull 3974; P8BE-LABEL: allOneull 3975; P8LE-LABEL: allOneull 3976; P9BE: xxspltib v2, 255 3977; P9BE: blr 3978; P9LE: xxspltib v2, 255 3979; P9LE: blr 3980; P8BE: vspltisb v2, -1 3981; P8BE: blr 3982; P8LE: vspltisb v2, -1 3983; P8LE: blr 3984} 3985 3986; Function Attrs: norecurse nounwind readnone 3987define <2 x i64> @spltConst1ull() { 3988entry: 3989 ret <2 x i64> <i64 1, i64 1> 3990; P9BE-LABEL: spltConst1ull 3991; P9LE-LABEL: spltConst1ull 3992; P8BE-LABEL: spltConst1ull 3993; P8LE-LABEL: spltConst1ull 3994; P9BE: lxv 3995; P9BE: blr 3996; P9LE: lxv 3997; P9LE: blr 3998; P8BE: lxvd2x 3999; P8BE: blr 4000; P8LE: lxvd2x 4001; P8LE: blr 4002} 4003 4004; Function Attrs: norecurse nounwind readnone 4005define <2 x i64> @spltConst16kull() { 4006entry: 4007 ret <2 x i64> <i64 32767, i64 32767> 4008; P9BE-LABEL: spltConst16kull 4009; P9LE-LABEL: spltConst16kull 4010; P8BE-LABEL: spltConst16kull 4011; P8LE-LABEL: spltConst16kull 4012; P9BE: lxv 4013; P9BE: blr 4014; P9LE: lxv 4015; P9LE: blr 4016; P8BE: lxvd2x 4017; P8BE: blr 4018; P8LE: lxvd2x 4019; P8LE: blr 4020} 4021 4022; Function Attrs: norecurse nounwind readnone 4023define <2 x i64> @spltConst32kull() { 4024entry: 4025 ret <2 x i64> <i64 65535, i64 65535> 4026; P9BE-LABEL: spltConst32kull 4027; P9LE-LABEL: spltConst32kull 4028; P8BE-LABEL: spltConst32kull 4029; P8LE-LABEL: spltConst32kull 4030; P9BE: lxv 4031; P9BE: blr 4032; P9LE: lxv 4033; P9LE: blr 4034; P8BE: lxvd2x 4035; P8BE: blr 4036; P8LE: lxvd2x 4037; P8LE: blr 4038} 4039 4040; Function Attrs: norecurse nounwind readnone 4041define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 4042entry: 4043 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 4044 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4045 ret <2 x i64> %vecinit1 4046; P9BE-LABEL: fromRegsull 4047; P9LE-LABEL: fromRegsull 4048; P8BE-LABEL: fromRegsull 4049; P8LE-LABEL: fromRegsull 4050; P9BE: mtvsrdd v2, r3, r4 4051; P9BE: blr 4052; P9LE: mtvsrdd v2, r4, r3 4053; P9LE: blr 4054; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4055; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4056; P8BE: xxmrghd v2 4057; P8BE: blr 4058; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4059; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4060; P8LE: xxmrghd v2 4061; P8LE: blr 4062} 4063 4064; Function Attrs: norecurse nounwind readnone 4065define <2 x i64> @fromDiffConstsull() { 4066entry: 4067 ret <2 x i64> <i64 242, i64 -113> 4068; P9BE-LABEL: fromDiffConstsull 4069; P9LE-LABEL: fromDiffConstsull 4070; P8BE-LABEL: fromDiffConstsull 4071; P8LE-LABEL: fromDiffConstsull 4072; P9BE: lxv 4073; P9BE: blr 4074; P9LE: lxv 4075; P9LE: blr 4076; P8BE: lxvd2x 4077; P8BE: blr 4078; P8LE: lxvd2x 4079; P8LE: blr 4080} 4081 4082; Function Attrs: norecurse nounwind readonly 4083define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 4084entry: 4085 %0 = load i64, i64* %arr, align 8 4086 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4087 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4088 %1 = load i64, i64* %arrayidx1, align 8 4089 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4090 ret <2 x i64> %vecinit2 4091; P9BE-LABEL: fromDiffMemConsAull 4092; P9LE-LABEL: fromDiffMemConsAull 4093; P8BE-LABEL: fromDiffMemConsAull 4094; P8LE-LABEL: fromDiffMemConsAull 4095; P9BE: lxv v2 4096; P9BE: blr 4097; P9LE: lxv v2 4098; P9LE: blr 4099; P8BE: lxvd2x v2 4100; P8BE: blr 4101; P8LE: lxvd2x 4102; P8LE: xxswapd v2 4103; P8LE: blr 4104} 4105 4106; Function Attrs: norecurse nounwind readonly 4107define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 4108entry: 4109 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4110 %0 = load i64, i64* %arrayidx, align 8 4111 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4112 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4113 %1 = load i64, i64* %arrayidx1, align 8 4114 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4115 ret <2 x i64> %vecinit2 4116; P9BE-LABEL: fromDiffMemConsDull 4117; P9LE-LABEL: fromDiffMemConsDull 4118; P8BE-LABEL: fromDiffMemConsDull 4119; P8LE-LABEL: fromDiffMemConsDull 4120; P9BE: lxv v2 4121; P9BE: blr 4122; P9LE: lxv 4123; P9LE: xxswapd v2 4124; P9LE: blr 4125; P8BE: lxvd2x 4126; P8BE: xxswapd v2 4127; P8BE-NEXT: blr 4128; P8LE: lxvd2x v2 4129; P8LE-NEXT: blr 4130} 4131 4132; Function Attrs: norecurse nounwind readonly 4133define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 4134entry: 4135 %idxprom = sext i32 %elem to i64 4136 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4137 %0 = load i64, i64* %arrayidx, align 8 4138 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4139 %add = add nsw i32 %elem, 1 4140 %idxprom1 = sext i32 %add to i64 4141 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4142 %1 = load i64, i64* %arrayidx2, align 8 4143 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4144 ret <2 x i64> %vecinit3 4145; P9BE-LABEL: fromDiffMemVarAull 4146; P9LE-LABEL: fromDiffMemVarAull 4147; P8BE-LABEL: fromDiffMemVarAull 4148; P8LE-LABEL: fromDiffMemVarAull 4149; P9BE: sldi 4150; P9BE: lxvx v2 4151; P9BE-NEXT: blr 4152; P9LE: sldi 4153; P9LE: lxvx v2 4154; P9LE-NEXT: blr 4155; P8BE: sldi 4156; P8BE: lxvd2x v2 4157; P8BE-NEXT: blr 4158; P8LE: sldi 4159; P8LE: lxvd2x 4160; P8LE: xxswapd v2 4161; P8LE-NEXT: blr 4162} 4163 4164; Function Attrs: norecurse nounwind readonly 4165define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 4166entry: 4167 %idxprom = sext i32 %elem to i64 4168 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4169 %0 = load i64, i64* %arrayidx, align 8 4170 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4171 %sub = add nsw i32 %elem, -1 4172 %idxprom1 = sext i32 %sub to i64 4173 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4174 %1 = load i64, i64* %arrayidx2, align 8 4175 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4176 ret <2 x i64> %vecinit3 4177; P9BE-LABEL: fromDiffMemVarDull 4178; P9LE-LABEL: fromDiffMemVarDull 4179; P8BE-LABEL: fromDiffMemVarDull 4180; P8LE-LABEL: fromDiffMemVarDull 4181; P9BE: sldi 4182; P9BE: lxv 4183; P9BE: xxswapd v2 4184; P9BE-NEXT: blr 4185; P9LE: sldi 4186; P9LE: lxv 4187; P9LE: xxswapd v2 4188; P9LE-NEXT: blr 4189; P8BE: sldi 4190; P8BE: lxvd2x 4191; P8BE: xxswapd v2 4192; P8BE-NEXT: blr 4193; P8LE: sldi 4194; P8LE: lxvd2x v2 4195; P8LE-NEXT: blr 4196} 4197 4198; Function Attrs: norecurse nounwind readonly 4199define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 4200entry: 4201 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4202 %0 = load i64, i64* %arrayidx, align 8 4203 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4204 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4205 %1 = load i64, i64* %arrayidx1, align 8 4206 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4207 ret <2 x i64> %vecinit2 4208; P9BE-LABEL: fromRandMemConsull 4209; P9LE-LABEL: fromRandMemConsull 4210; P8BE-LABEL: fromRandMemConsull 4211; P8LE-LABEL: fromRandMemConsull 4212; P9BE: ld 4213; P9BE: ld 4214; P9BE: mtvsrdd v2 4215; P9BE-NEXT: blr 4216; P9LE: ld 4217; P9LE: ld 4218; P9LE: mtvsrdd v2 4219; P9LE-NEXT: blr 4220; P8BE: ld 4221; P8BE: ld 4222; P8BE-DAG: mtvsrd 4223; P8BE-DAG: mtvsrd 4224; P8BE: xxmrghd v2 4225; P8BE-NEXT: blr 4226; P8LE: ld 4227; P8LE: ld 4228; P8LE-DAG: mtvsrd 4229; P8LE-DAG: mtvsrd 4230; P8LE: xxmrghd v2 4231; P8LE-NEXT: blr 4232} 4233 4234; Function Attrs: norecurse nounwind readonly 4235define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 4236entry: 4237 %add = add nsw i32 %elem, 4 4238 %idxprom = sext i32 %add to i64 4239 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4240 %0 = load i64, i64* %arrayidx, align 8 4241 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4242 %add1 = add nsw i32 %elem, 1 4243 %idxprom2 = sext i32 %add1 to i64 4244 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4245 %1 = load i64, i64* %arrayidx3, align 8 4246 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4247 ret <2 x i64> %vecinit4 4248; P9BE-LABEL: fromRandMemVarull 4249; P9LE-LABEL: fromRandMemVarull 4250; P8BE-LABEL: fromRandMemVarull 4251; P8LE-LABEL: fromRandMemVarull 4252; P9BE: sldi 4253; P9BE: ld 4254; P9BE: ld 4255; P9BE: mtvsrdd v2 4256; P9BE-NEXT: blr 4257; P9LE: sldi 4258; P9LE: ld 4259; P9LE: ld 4260; P9LE: mtvsrdd v2 4261; P9LE-NEXT: blr 4262; P8BE: sldi 4263; P8BE: ld 4264; P8BE: ld 4265; P8BE: mtvsrd 4266; P8BE: mtvsrd 4267; P8BE: xxmrghd v2 4268; P8BE-NEXT: blr 4269; P8LE: sldi 4270; P8LE: ld 4271; P8LE: ld 4272; P8LE: mtvsrd 4273; P8LE: mtvsrd 4274; P8LE: xxmrghd v2 4275; P8LE-NEXT: blr 4276} 4277 4278; Function Attrs: norecurse nounwind readnone 4279define <2 x i64> @spltRegValull(i64 %val) { 4280entry: 4281 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4282 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4283 ret <2 x i64> %splat.splat 4284; P9BE-LABEL: spltRegValull 4285; P9LE-LABEL: spltRegValull 4286; P8BE-LABEL: spltRegValull 4287; P8LE-LABEL: spltRegValull 4288; P9BE: mtvsrdd v2, r3, r3 4289; P9BE-NEXT: blr 4290; P9LE: mtvsrdd v2, r3, r3 4291; P9LE-NEXT: blr 4292; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4293; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4294; P8BE-NEXT: blr 4295; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4296; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4297; P8LE-NEXT: blr 4298} 4299 4300; Function Attrs: norecurse nounwind readonly 4301define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 4302entry: 4303 %0 = load i64, i64* %ptr, align 8 4304 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4305 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4306 ret <2 x i64> %splat.splat 4307; P9BE-LABEL: spltMemValull 4308; P9LE-LABEL: spltMemValull 4309; P8BE-LABEL: spltMemValull 4310; P8LE-LABEL: spltMemValull 4311; P9BE: lxvdsx v2 4312; P9BE-NEXT: blr 4313; P9LE: lxvdsx v2 4314; P9LE-NEXT: blr 4315; P8BE: lxvdsx v2 4316; P8BE-NEXT: blr 4317; P8LE: lxvdsx v2 4318; P8LE-NEXT: blr 4319} 4320 4321; Function Attrs: norecurse nounwind readnone 4322define <2 x i64> @spltCnstConvftoull() { 4323entry: 4324 ret <2 x i64> <i64 4, i64 4> 4325; P9BE-LABEL: spltCnstConvftoull 4326; P9LE-LABEL: spltCnstConvftoull 4327; P8BE-LABEL: spltCnstConvftoull 4328; P8LE-LABEL: spltCnstConvftoull 4329; P9BE: lxv 4330; P9BE: blr 4331; P9LE: lxv 4332; P9LE: blr 4333; P8BE: lxvd2x 4334; P8BE: blr 4335; P8LE: lxvd2x 4336; P8LE: blr 4337} 4338 4339; Function Attrs: norecurse nounwind readnone 4340define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 4341entry: 4342 %conv = fptoui float %a to i64 4343 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4344 %conv1 = fptoui float %b to i64 4345 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4346 ret <2 x i64> %vecinit2 4347; P9BE-LABEL: fromRegsConvftoull 4348; P9LE-LABEL: fromRegsConvftoull 4349; P8BE-LABEL: fromRegsConvftoull 4350; P8LE-LABEL: fromRegsConvftoull 4351; P9BE: xxmrghd 4352; P9BE: xvcvdpuxds v2 4353; P9BE-NEXT: blr 4354; P9LE: xxmrghd 4355; P9LE: xvcvdpuxds v2 4356; P9LE-NEXT: blr 4357; P8BE: xxmrghd 4358; P8BE: xvcvdpuxds v2 4359; P8BE-NEXT: blr 4360; P8LE: xxmrghd 4361; P8LE: xvcvdpuxds v2 4362; P8LE-NEXT: blr 4363} 4364 4365; Function Attrs: norecurse nounwind readnone 4366define <2 x i64> @fromDiffConstsConvftoull() { 4367entry: 4368 ret <2 x i64> <i64 24, i64 234> 4369; P9BE-LABEL: fromDiffConstsConvftoull 4370; P9LE-LABEL: fromDiffConstsConvftoull 4371; P8BE-LABEL: fromDiffConstsConvftoull 4372; P8LE-LABEL: fromDiffConstsConvftoull 4373; P9BE: lxv v2 4374; P9BE: blr 4375; P9LE: lxv v2 4376; P9LE: blr 4377; P8BE: lxvd2x v2 4378; P8BE: blr 4379; P8LE: lxvd2x 4380; P8LE: xxswapd v2 4381; P8LE: blr 4382} 4383 4384; Function Attrs: norecurse nounwind readonly 4385define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 4386entry: 4387 %0 = load float, float* %ptr, align 4 4388 %conv = fptoui float %0 to i64 4389 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4390 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4391 %1 = load float, float* %arrayidx1, align 4 4392 %conv2 = fptoui float %1 to i64 4393 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4394 ret <2 x i64> %vecinit3 4395; P9BE-LABEL: fromDiffMemConsAConvftoull 4396; P9LE-LABEL: fromDiffMemConsAConvftoull 4397; P8BE-LABEL: fromDiffMemConsAConvftoull 4398; P8LE-LABEL: fromDiffMemConsAConvftoull 4399; P9BE: lfs 4400; P9BE: lfs 4401; P9BE: xxmrghd 4402; P9BE-NEXT: xvcvdpuxds v2 4403; P9BE-NEXT: blr 4404; P9LE: lfs 4405; P9LE: lfs 4406; P9LE: xxmrghd 4407; P9LE-NEXT: xvcvdpuxds v2 4408; P9LE-NEXT: blr 4409; P8BE: lxsspx 4410; P8BE: lxsspx 4411; P8BE: xxmrghd 4412; P8BE-NEXT: xvcvdpuxds v2 4413; P8BE-NEXT: blr 4414; P8LE: lxsspx 4415; P8LE: lxsspx 4416; P8LE: xxmrghd 4417; P8LE-NEXT: xvcvdpuxds v2 4418; P8LE-NEXT: blr 4419} 4420 4421; Function Attrs: norecurse nounwind readonly 4422define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 4423entry: 4424 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4425 %0 = load float, float* %arrayidx, align 4 4426 %conv = fptoui float %0 to i64 4427 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4428 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4429 %1 = load float, float* %arrayidx1, align 4 4430 %conv2 = fptoui float %1 to i64 4431 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4432 ret <2 x i64> %vecinit3 4433; P9BE-LABEL: fromDiffMemConsDConvftoull 4434; P9LE-LABEL: fromDiffMemConsDConvftoull 4435; P8BE-LABEL: fromDiffMemConsDConvftoull 4436; P8LE-LABEL: fromDiffMemConsDConvftoull 4437; P9BE: lfs 4438; P9BE: lfs 4439; P9BE: xxmrghd 4440; P9BE-NEXT: xvcvdpuxds v2 4441; P9BE-NEXT: blr 4442; P9LE: lfs 4443; P9LE: lfs 4444; P9LE: xxmrghd 4445; P9LE-NEXT: xvcvdpuxds v2 4446; P9LE-NEXT: blr 4447; P8BE: lxsspx 4448; P8BE: lxsspx 4449; P8BE: xxmrghd 4450; P8BE-NEXT: xvcvdpuxds v2 4451; P8BE-NEXT: blr 4452; P8LE: lxsspx 4453; P8LE: lxsspx 4454; P8LE: xxmrghd 4455; P8LE-NEXT: xvcvdpuxds v2 4456; P8LE-NEXT: blr 4457} 4458 4459; Function Attrs: norecurse nounwind readonly 4460define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4461entry: 4462 %idxprom = sext i32 %elem to i64 4463 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4464 %0 = load float, float* %arrayidx, align 4 4465 %conv = fptoui float %0 to i64 4466 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4467 %add = add nsw i32 %elem, 1 4468 %idxprom1 = sext i32 %add to i64 4469 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4470 %1 = load float, float* %arrayidx2, align 4 4471 %conv3 = fptoui float %1 to i64 4472 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4473 ret <2 x i64> %vecinit4 4474; P9BE-LABEL: fromDiffMemVarAConvftoull 4475; P9LE-LABEL: fromDiffMemVarAConvftoull 4476; P8BE-LABEL: fromDiffMemVarAConvftoull 4477; P8LE-LABEL: fromDiffMemVarAConvftoull 4478; P9BE: sldi 4479; P9BE: lfsux 4480; P9BE: lfs 4481; P9BE: xxmrghd 4482; P9BE-NEXT: xvcvdpuxds v2 4483; P9BE-NEXT: blr 4484; P9LE: sldi 4485; P9LE: lfsux 4486; P9LE: lfs 4487; P9LE: xxmrghd 4488; P9LE-NEXT: xvcvdpuxds v2 4489; P9LE-NEXT: blr 4490; P8BE: sldi 4491; P8BE: lfsux 4492; P8BE: lxsspx 4493; P8BE: xxmrghd 4494; P8BE-NEXT: xvcvdpuxds v2 4495; P8BE-NEXT: blr 4496; P8LE: sldi 4497; P8LE: lfsux 4498; P8LE: lxsspx 4499; P8LE: xxmrghd 4500; P8LE-NEXT: xvcvdpuxds v2 4501; P8LE-NEXT: blr 4502} 4503 4504; Function Attrs: norecurse nounwind readonly 4505define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4506entry: 4507 %idxprom = sext i32 %elem to i64 4508 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4509 %0 = load float, float* %arrayidx, align 4 4510 %conv = fptoui float %0 to i64 4511 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4512 %sub = add nsw i32 %elem, -1 4513 %idxprom1 = sext i32 %sub to i64 4514 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4515 %1 = load float, float* %arrayidx2, align 4 4516 %conv3 = fptoui float %1 to i64 4517 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4518 ret <2 x i64> %vecinit4 4519; P9BE-LABEL: fromDiffMemVarDConvftoull 4520; P9LE-LABEL: fromDiffMemVarDConvftoull 4521; P8BE-LABEL: fromDiffMemVarDConvftoull 4522; P8LE-LABEL: fromDiffMemVarDConvftoull 4523; P9BE: sldi 4524; P9BE: lfsux 4525; P9BE: lfs 4526; P9BE: xxmrghd 4527; P9BE-NEXT: xvcvdpuxds v2 4528; P9BE-NEXT: blr 4529; P9LE: sldi 4530; P9LE: lfsux 4531; P9LE: lfs 4532; P9LE: xxmrghd 4533; P9LE-NEXT: xvcvdpuxds v2 4534; P9LE-NEXT: blr 4535; P8BE: sldi 4536; P8BE: lfsux 4537; P8BE: lxsspx 4538; P8BE: xxmrghd 4539; P8BE-NEXT: xvcvdpuxds v2 4540; P8BE-NEXT: blr 4541; P8LE: sldi 4542; P8LE: lfsux 4543; P8LE: lxsspx 4544; P8LE: xxmrghd 4545; P8LE-NEXT: xvcvdpuxds v2 4546; P8LE-NEXT: blr 4547} 4548 4549; Function Attrs: norecurse nounwind readnone 4550define <2 x i64> @spltRegValConvftoull(float %val) { 4551entry: 4552 %conv = fptoui float %val to i64 4553 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4554 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4555 ret <2 x i64> %splat.splat 4556; P9BE-LABEL: spltRegValConvftoull 4557; P9LE-LABEL: spltRegValConvftoull 4558; P8BE-LABEL: spltRegValConvftoull 4559; P8LE-LABEL: spltRegValConvftoull 4560; P9BE: xscvdpuxds 4561; P9BE-NEXT: xxspltd v2 4562; P9BE-NEXT: blr 4563; P9LE: xscvdpuxds 4564; P9LE-NEXT: xxspltd v2 4565; P9LE-NEXT: blr 4566; P8BE: xscvdpuxds 4567; P8BE-NEXT: xxspltd v2 4568; P8BE-NEXT: blr 4569; P8LE: xscvdpuxds 4570; P8LE-NEXT: xxspltd v2 4571; P8LE-NEXT: blr 4572} 4573 4574; Function Attrs: norecurse nounwind readonly 4575define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 4576entry: 4577 %0 = load float, float* %ptr, align 4 4578 %conv = fptoui float %0 to i64 4579 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4580 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4581 ret <2 x i64> %splat.splat 4582; P9BE-LABEL: spltMemValConvftoull 4583; P9LE-LABEL: spltMemValConvftoull 4584; P8BE-LABEL: spltMemValConvftoull 4585; P8LE-LABEL: spltMemValConvftoull 4586; P9BE: lfs 4587; P9BE-NEXT: xscvdpuxds 4588; P9BE-NEXT: xxspltd v2 4589; P9BE-NEXT: blr 4590; P9LE: lfs 4591; P9LE-NEXT: xscvdpuxds 4592; P9LE-NEXT: xxspltd v2 4593; P9LE-NEXT: blr 4594; P8BE: lxsspx 4595; P8BE-NEXT: xscvdpuxds 4596; P8BE-NEXT: xxspltd v2 4597; P8BE-NEXT: blr 4598; P8LE: lxsspx 4599; P8LE-NEXT: xscvdpuxds 4600; P8LE-NEXT: xxspltd v2 4601; P8LE-NEXT: blr 4602} 4603 4604; Function Attrs: norecurse nounwind readnone 4605define <2 x i64> @spltCnstConvdtoull() { 4606entry: 4607 ret <2 x i64> <i64 4, i64 4> 4608; P9BE-LABEL: spltCnstConvdtoull 4609; P9LE-LABEL: spltCnstConvdtoull 4610; P8BE-LABEL: spltCnstConvdtoull 4611; P8LE-LABEL: spltCnstConvdtoull 4612; P9BE: lxv 4613; P9BE: blr 4614; P9LE: lxv 4615; P9LE: blr 4616; P8BE: lxvd2x 4617; P8BE: blr 4618; P8LE: lxvd2x 4619; P8LE: blr 4620} 4621 4622; Function Attrs: norecurse nounwind readnone 4623define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 4624entry: 4625 %conv = fptoui double %a to i64 4626 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4627 %conv1 = fptoui double %b to i64 4628 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4629 ret <2 x i64> %vecinit2 4630; P9BE-LABEL: fromRegsConvdtoull 4631; P9LE-LABEL: fromRegsConvdtoull 4632; P8BE-LABEL: fromRegsConvdtoull 4633; P8LE-LABEL: fromRegsConvdtoull 4634; P9BE: xxmrghd 4635; P9BE-NEXT: xvcvdpuxds 4636; P9BE-NEXT: blr 4637; P9LE: xxmrghd 4638; P9LE-NEXT: xvcvdpuxds 4639; P9LE-NEXT: blr 4640; P8BE: xxmrghd 4641; P8BE-NEXT: xvcvdpuxds 4642; P8BE-NEXT: blr 4643; P8LE: xxmrghd 4644; P8LE-NEXT: xvcvdpuxds 4645; P8LE-NEXT: blr 4646} 4647 4648; Function Attrs: norecurse nounwind readnone 4649define <2 x i64> @fromDiffConstsConvdtoull() { 4650entry: 4651 ret <2 x i64> <i64 24, i64 234> 4652; P9BE-LABEL: fromDiffConstsConvdtoull 4653; P9LE-LABEL: fromDiffConstsConvdtoull 4654; P8BE-LABEL: fromDiffConstsConvdtoull 4655; P8LE-LABEL: fromDiffConstsConvdtoull 4656; P9BE: lxv 4657; P9BE: blr 4658; P9LE: lxv 4659; P9LE: blr 4660; P8BE: lxvd2x 4661; P8BE: blr 4662; P8LE: lxvd2x 4663; P8LE: blr 4664} 4665 4666; Function Attrs: norecurse nounwind readonly 4667define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 4668entry: 4669 %0 = bitcast double* %ptr to <2 x double>* 4670 %1 = load <2 x double>, <2 x double>* %0, align 8 4671 %2 = fptoui <2 x double> %1 to <2 x i64> 4672 ret <2 x i64> %2 4673; P9BE-LABEL: fromDiffMemConsAConvdtoull 4674; P9LE-LABEL: fromDiffMemConsAConvdtoull 4675; P8BE-LABEL: fromDiffMemConsAConvdtoull 4676; P8LE-LABEL: fromDiffMemConsAConvdtoull 4677; P9BE: lxv 4678; P9BE-NEXT: xvcvdpuxds v2 4679; P9BE-NEXT: blr 4680; P9LE: lxv 4681; P9LE-NEXT: xvcvdpuxds v2 4682; P9LE-NEXT: blr 4683; P8BE: lxvd2x 4684; P8BE-NEXT: xvcvdpuxds v2 4685; P8BE-NEXT: blr 4686; P8LE: lxvd2x 4687; P8LE: xxswapd 4688; P8LE-NEXT: xvcvdpuxds v2 4689; P8LE-NEXT: blr 4690} 4691 4692; Function Attrs: norecurse nounwind readonly 4693define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 4694entry: 4695 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4696 %0 = load double, double* %arrayidx, align 8 4697 %conv = fptoui double %0 to i64 4698 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4699 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4700 %1 = load double, double* %arrayidx1, align 8 4701 %conv2 = fptoui double %1 to i64 4702 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4703 ret <2 x i64> %vecinit3 4704; P9BE-LABEL: fromDiffMemConsDConvdtoull 4705; P9LE-LABEL: fromDiffMemConsDConvdtoull 4706; P8BE-LABEL: fromDiffMemConsDConvdtoull 4707; P8LE-LABEL: fromDiffMemConsDConvdtoull 4708; P9BE: lxv 4709; P9BE-NEXT: xxswapd 4710; P9BE-NEXT: xvcvdpuxds v2 4711; P9BE-NEXT: blr 4712; P9LE: lxv 4713; P9LE-NEXT: xxswapd 4714; P9LE-NEXT: xvcvdpuxds v2 4715; P9LE-NEXT: blr 4716; P8BE: lxvd2x 4717; P8BE-NEXT: xxswapd 4718; P8BE-NEXT: xvcvdpuxds v2 4719; P8BE-NEXT: blr 4720; P8LE: lxvd2x 4721; P8LE-NEXT: xvcvdpuxds v2 4722; P8LE-NEXT: blr 4723} 4724 4725; Function Attrs: norecurse nounwind readonly 4726define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4727entry: 4728 %idxprom = sext i32 %elem to i64 4729 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4730 %0 = load double, double* %arrayidx, align 8 4731 %conv = fptoui double %0 to i64 4732 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4733 %add = add nsw i32 %elem, 1 4734 %idxprom1 = sext i32 %add to i64 4735 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4736 %1 = load double, double* %arrayidx2, align 8 4737 %conv3 = fptoui double %1 to i64 4738 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4739 ret <2 x i64> %vecinit4 4740; P9BE-LABEL: fromDiffMemVarAConvdtoull 4741; P9LE-LABEL: fromDiffMemVarAConvdtoull 4742; P8BE-LABEL: fromDiffMemVarAConvdtoull 4743; P8LE-LABEL: fromDiffMemVarAConvdtoull 4744; P9BE: sldi 4745; P9BE: lxvx 4746; P9BE-NEXT: xvcvdpuxds v2 4747; P9BE-NEXT: blr 4748; P9LE: sldi 4749; P9LE: lxvx 4750; P9LE-NEXT: xvcvdpuxds v2 4751; P9LE-NEXT: blr 4752; P8BE: sldi 4753; P8BE: lxvd2x 4754; P8BE-NEXT: xvcvdpuxds v2 4755; P8BE-NEXT: blr 4756; P8LE: sldi 4757; P8LE: lxvd2x 4758; P8LE-NEXT: xxswapd 4759; P8LE-NEXT: xvcvdpuxds v2 4760; P8LE-NEXT: blr 4761} 4762 4763; Function Attrs: norecurse nounwind readonly 4764define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4765entry: 4766 %idxprom = sext i32 %elem to i64 4767 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4768 %0 = load double, double* %arrayidx, align 8 4769 %conv = fptoui double %0 to i64 4770 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4771 %sub = add nsw i32 %elem, -1 4772 %idxprom1 = sext i32 %sub to i64 4773 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4774 %1 = load double, double* %arrayidx2, align 8 4775 %conv3 = fptoui double %1 to i64 4776 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4777 ret <2 x i64> %vecinit4 4778; P9BE-LABEL: fromDiffMemVarDConvdtoull 4779; P9LE-LABEL: fromDiffMemVarDConvdtoull 4780; P8BE-LABEL: fromDiffMemVarDConvdtoull 4781; P8LE-LABEL: fromDiffMemVarDConvdtoull 4782; P9BE: sldi 4783; P9BE: lxv 4784; P9BE-NEXT: xxswapd 4785; P9BE-NEXT: xvcvdpuxds v2 4786; P9BE-NEXT: blr 4787; P9LE: sldi 4788; P9LE: lxv 4789; P9LE-NEXT: xxswapd 4790; P9LE-NEXT: xvcvdpuxds v2 4791; P9LE-NEXT: blr 4792; P8BE: sldi 4793; P8BE: lxvd2x 4794; P8BE-NEXT: xxswapd 4795; P8BE-NEXT: xvcvdpuxds v2 4796; P8BE-NEXT: blr 4797; P8LE: sldi 4798; P8LE: lxvd2x 4799; P8LE-NEXT: xvcvdpuxds v2 4800; P8LE-NEXT: blr 4801} 4802 4803; Function Attrs: norecurse nounwind readnone 4804define <2 x i64> @spltRegValConvdtoull(double %val) { 4805entry: 4806 %conv = fptoui double %val to i64 4807 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4808 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4809 ret <2 x i64> %splat.splat 4810; P9BE-LABEL: spltRegValConvdtoull 4811; P9LE-LABEL: spltRegValConvdtoull 4812; P8BE-LABEL: spltRegValConvdtoull 4813; P8LE-LABEL: spltRegValConvdtoull 4814; P9BE: xscvdpuxds 4815; P9BE-NEXT: xxspltd v2 4816; P9BE-NEXT: blr 4817; P9LE: xscvdpuxds 4818; P9LE-NEXT: xxspltd v2 4819; P9LE-NEXT: blr 4820; P8BE: xscvdpuxds 4821; P8BE-NEXT: xxspltd v2 4822; P8BE-NEXT: blr 4823; P8LE: xscvdpuxds 4824; P8LE-NEXT: xxspltd v2 4825; P8LE-NEXT: blr 4826} 4827 4828; Function Attrs: norecurse nounwind readonly 4829define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 4830entry: 4831 %0 = load double, double* %ptr, align 8 4832 %conv = fptoui double %0 to i64 4833 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4834 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4835 ret <2 x i64> %splat.splat 4836; P9BE-LABEL: spltMemValConvdtoull 4837; P9LE-LABEL: spltMemValConvdtoull 4838; P8BE-LABEL: spltMemValConvdtoull 4839; P8LE-LABEL: spltMemValConvdtoull 4840; P9BE: lxvdsx 4841; P9BE-NEXT: xvcvdpuxds 4842; P9BE-NEXT: blr 4843; P9LE: lxvdsx 4844; P9LE-NEXT: xvcvdpuxds 4845; P9LE-NEXT: blr 4846; P8BE: lxvdsx 4847; P8BE-NEXT: xvcvdpuxds 4848; P8BE-NEXT: blr 4849; P8LE: lxvdsx 4850; P8LE-NEXT: xvcvdpuxds 4851; P8LE-NEXT: blr 4852} 4853