1; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 2; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 3; RUN: -check-prefix=P9BE -implicit-check-not frsp 4; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 5; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 6; RUN: -check-prefix=P9LE -implicit-check-not frsp 7; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 8; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 9; RUN: -check-prefix=P8BE -implicit-check-not frsp 10; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 11; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 12; RUN: -check-prefix=P8LE -implicit-check-not frsp 13 14; This test case comes from the following C test case (included as it may be 15; slightly more readable than the LLVM IR. 16 17;/* This test case provides various ways of building vectors to ensure we 18; produce optimal code for all cases. The cases are (for each type): 19; - All zeros 20; - All ones 21; - Splat of a constant 22; - From different values already in registers 23; - From different constants 24; - From different values in memory 25; - Splat of a value in register 26; - Splat of a value in memory 27; - Inserting element into existing vector 28; - Inserting element from existing vector into existing vector 29; 30; With conversions (float <-> int) 31; - Splat of a constant 32; - From different values already in registers 33; - From different constants 34; - From different values in memory 35; - Splat of a value in register 36; - Splat of a value in memory 37; - Inserting element into existing vector 38; - Inserting element from existing vector into existing vector 39;*/ 40; 41;/*=================================== int ===================================*/ 42;// P8: xxlxor // 43;// P9: xxlxor // 44;vector int allZeroi() { // 45; return (vector int)0; // 46;} // 47;// P8: vspltisb -1 // 48;// P9: xxspltisb 255 // 49;vector int allOnei() { // 50; return (vector int)-1; // 51;} // 52;// P8: vspltisw 1 // 53;// P9: vspltisw 1 // 54;vector int spltConst1i() { // 55; return (vector int)1; // 56;} // 57;// P8: vspltisw -15; vsrw // 58;// P9: vspltisw -15; vsrw // 59;vector int spltConst16ki() { // 60; return (vector int)((1<<15) - 1); // 61;} // 62;// P8: vspltisw -16; vsrw // 63;// P9: vspltisw -16; vsrw // 64;vector int spltConst32ki() { // 65; return (vector int)((1<<16) - 1); // 66;} // 67;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 68;// P9: 2 x mtvsrdd, vmrgow // 69;vector int fromRegsi(int a, int b, int c, int d) { // 70; return (vector int){ a, b, c, d }; // 71;} // 72;// P8: lxvd2x, xxswapd // 73;// P9: lxvx (or even lxv) // 74;vector int fromDiffConstsi() { // 75; return (vector int) { 242, -113, 889, 19 }; // 76;} // 77;// P8: lxvd2x, xxswapd // 78;// P9: lxvx // 79;vector int fromDiffMemConsAi(int *arr) { // 80; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 81;} // 82;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 83;// P9: 2 x lxvx, vperm // 84;vector int fromDiffMemConsDi(int *arr) { // 85; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 86;} // 87;// P8: sldi 2, lxvd2x, xxswapd // 88;// P9: sldi 2, lxvx // 89;vector int fromDiffMemVarAi(int *arr, int elem) { // 90; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 91;} // 92;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 93;// P9: sldi 2, 2 x lxvx, vperm // 94;vector int fromDiffMemVarDi(int *arr, int elem) { // 95; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 96;} // 97;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 98;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 99;vector int fromRandMemConsi(int *arr) { // 100; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 101;} // 102;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 103;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 104;vector int fromRandMemVari(int *arr, int elem) { // 105; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 106;} // 107;// P8: mtvsrwz, xxspltw // 108;// P9: mtvsrws // 109;vector int spltRegVali(int val) { // 110; return (vector int) val; // 111;} // 112;// P8: lxsiwax, xxspltw // 113;// P9: lxvwsx // 114;vector int spltMemVali(int *ptr) { // 115; return (vector int)*ptr; // 116;} // 117;// P8: vspltisw // 118;// P9: vspltisw // 119;vector int spltCnstConvftoi() { // 120; return (vector int) 4.74f; // 121;} // 122;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 123;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 124;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 125; return (vector int) { a, b, c, d }; // 126;} // 127;// P8: lxvd2x, xxswapd // 128;// P9: lxvx (even lxv) // 129;vector int fromDiffConstsConvftoi() { // 130; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 131;} // 132;// P8: lxvd2x, xxswapd, xvcvspsxws // 133;// P9: lxvx, xvcvspsxws // 134;vector int fromDiffMemConsAConvftoi(float *ptr) { // 135; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 136;} // 137;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 138;// P9: 2 x lxvx, vperm, xvcvspsxws // 139;vector int fromDiffMemConsDConvftoi(float *ptr) { // 140; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 141;} // 142;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 143;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 144;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 145;// sldi 2, load, xvcvspuxws // 146;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 147; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 148;} // 149;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 150;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 151;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 152;// sldi 2, 2 x load, vperm, xvcvspuxws // 153;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 154; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 155;} // 156;// P8: xscvdpsxws, xxspltw // 157;// P9: xscvdpsxws, xxspltw // 158;vector int spltRegValConvftoi(float val) { // 159; return (vector int) val; // 160;} // 161;// P8: lxsspx, xscvdpsxws, xxspltw // 162;// P9: lxvwsx, xvcvspsxws // 163;vector int spltMemValConvftoi(float *ptr) { // 164; return (vector int)*ptr; // 165;} // 166;// P8: vspltisw // 167;// P9: vspltisw // 168;vector int spltCnstConvdtoi() { // 169; return (vector int) 4.74; // 170;} // 171;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 172;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 173;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 174; return (vector int) { a, b, c, d }; // 175;} // 176;// P8: lxvd2x, xxswapd // 177;// P9: lxvx (even lxv) // 178;vector int fromDiffConstsConvdtoi() { // 179; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 180;} // 181;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 182;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 183;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 184; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 185;} // 186;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 187;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 189; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 190;} // 191;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 192;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 194; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 195;} // 196;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 197;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 198;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 199; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 200;} // 201;// P8: xscvdpsxws, xxspltw // 202;// P9: xscvdpsxws, xxspltw // 203;vector int spltRegValConvdtoi(double val) { // 204; return (vector int) val; // 205;} // 206;// P8: lxsdx, xscvdpsxws, xxspltw // 207;// P9: lxssp, xscvdpsxws, xxspltw // 208;vector int spltMemValConvdtoi(double *ptr) { // 209; return (vector int)*ptr; // 210;} // 211;/*=================================== int ===================================*/ 212;/*=============================== unsigned int ==============================*/ 213;// P8: xxlxor // 214;// P9: xxlxor // 215;vector unsigned int allZeroui() { // 216; return (vector unsigned int)0; // 217;} // 218;// P8: vspltisb -1 // 219;// P9: xxspltisb 255 // 220;vector unsigned int allOneui() { // 221; return (vector unsigned int)-1; // 222;} // 223;// P8: vspltisw 1 // 224;// P9: vspltisw 1 // 225;vector unsigned int spltConst1ui() { // 226; return (vector unsigned int)1; // 227;} // 228;// P8: vspltisw -15; vsrw // 229;// P9: vspltisw -15; vsrw // 230;vector unsigned int spltConst16kui() { // 231; return (vector unsigned int)((1<<15) - 1); // 232;} // 233;// P8: vspltisw -16; vsrw // 234;// P9: vspltisw -16; vsrw // 235;vector unsigned int spltConst32kui() { // 236; return (vector unsigned int)((1<<16) - 1); // 237;} // 238;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 239;// P9: 2 x mtvsrdd, vmrgow // 240;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 241; unsigned int c, unsigned int d) { // 242; return (vector unsigned int){ a, b, c, d }; // 243;} // 244;// P8: lxvd2x, xxswapd // 245;// P9: lxvx (or even lxv) // 246;vector unsigned int fromDiffConstsui() { // 247; return (vector unsigned int) { 242, -113, 889, 19 }; // 248;} // 249;// P8: lxvd2x, xxswapd // 250;// P9: lxvx // 251;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 252; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 253;} // 254;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 255;// P9: 2 x lxvx, vperm // 256;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 257; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 258;} // 259;// P8: sldi 2, lxvd2x, xxswapd // 260;// P9: sldi 2, lxvx // 261;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 262; return (vector unsigned int) { arr[elem], arr[elem+1], // 263; arr[elem+2], arr[elem+3] }; // 264;} // 265;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 266;// P9: sldi 2, 2 x lxvx, vperm // 267;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 268; return (vector unsigned int) { arr[elem], arr[elem-1], // 269; arr[elem-2], arr[elem-3] }; // 270;} // 271;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 272;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 273;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 274; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 275;} // 276;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 277;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 278;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 279; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 280; arr[elem+2], arr[elem+8] }; // 281;} // 282;// P8: mtvsrwz, xxspltw // 283;// P9: mtvsrws // 284;vector unsigned int spltRegValui(unsigned int val) { // 285; return (vector unsigned int) val; // 286;} // 287;// P8: lxsiwax, xxspltw // 288;// P9: lxvwsx // 289;vector unsigned int spltMemValui(unsigned int *ptr) { // 290; return (vector unsigned int)*ptr; // 291;} // 292;// P8: vspltisw // 293;// P9: vspltisw // 294;vector unsigned int spltCnstConvftoui() { // 295; return (vector unsigned int) 4.74f; // 296;} // 297;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 298;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 299;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 300; return (vector unsigned int) { a, b, c, d }; // 301;} // 302;// P8: lxvd2x, xxswapd // 303;// P9: lxvx (even lxv) // 304;vector unsigned int fromDiffConstsConvftoui() { // 305; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 306;} // 307;// P8: lxvd2x, xxswapd, xvcvspuxws // 308;// P9: lxvx, xvcvspuxws // 309;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 310; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 311;} // 312;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 313;// P9: 2 x lxvx, vperm, xvcvspuxws // 314;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 315; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 316;} // 317;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 319;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 320;// sldi 2, load, xvcvspuxws // 321;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 322; return (vector unsigned int) { arr[elem], arr[elem+1], // 323; arr[elem+2], arr[elem+3] }; // 324;} // 325;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 326;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 327;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 328;// sldi 2, 2 x load, vperm, xvcvspuxws // 329;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 330; return (vector unsigned int) { arr[elem], arr[elem-1], // 331; arr[elem-2], arr[elem-3] }; // 332;} // 333;// P8: xscvdpuxws, xxspltw // 334;// P9: xscvdpuxws, xxspltw // 335;vector unsigned int spltRegValConvftoui(float val) { // 336; return (vector unsigned int) val; // 337;} // 338;// P8: lxsspx, xscvdpuxws, xxspltw // 339;// P9: lxvwsx, xvcvspuxws // 340;vector unsigned int spltMemValConvftoui(float *ptr) { // 341; return (vector unsigned int)*ptr; // 342;} // 343;// P8: vspltisw // 344;// P9: vspltisw // 345;vector unsigned int spltCnstConvdtoui() { // 346; return (vector unsigned int) 4.74; // 347;} // 348;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 349;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 350;vector unsigned int fromRegsConvdtoui(double a, double b, // 351; double c, double d) { // 352; return (vector unsigned int) { a, b, c, d }; // 353;} // 354;// P8: lxvd2x, xxswapd // 355;// P9: lxvx (even lxv) // 356;vector unsigned int fromDiffConstsConvdtoui() { // 357; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 358;} // 359;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 360;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 361;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 362; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 363;} // 364;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 365;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 366;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 367; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 368;} // 369;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 370;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 371;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 372; return (vector unsigned int) { arr[elem], arr[elem+1], // 373; arr[elem+2], arr[elem+3] }; // 374;} // 375;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 376;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 377;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 378; return (vector unsigned int) { arr[elem], arr[elem-1], // 379; arr[elem-2], arr[elem-3] }; // 380;} // 381;// P8: xscvdpuxws, xxspltw // 382;// P9: xscvdpuxws, xxspltw // 383;vector unsigned int spltRegValConvdtoui(double val) { // 384; return (vector unsigned int) val; // 385;} // 386;// P8: lxsspx, xscvdpuxws, xxspltw // 387;// P9: lfd, xscvdpuxws, xxspltw // 388;vector unsigned int spltMemValConvdtoui(double *ptr) { // 389; return (vector unsigned int)*ptr; // 390;} // 391;/*=============================== unsigned int ==============================*/ 392;/*=============================== long long =================================*/ 393;// P8: xxlxor // 394;// P9: xxlxor // 395;vector long long allZeroll() { // 396; return (vector long long)0; // 397;} // 398;// P8: vspltisb -1 // 399;// P9: xxspltisb 255 // 400;vector long long allOnell() { // 401; return (vector long long)-1; // 402;} // 403;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 404;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 405;vector long long spltConst1ll() { // 406; return (vector long long)1; // 407;} // 408;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 409;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 410;vector long long spltConst16kll() { // 411; return (vector long long)((1<<15) - 1); // 412;} // 413;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 414;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 415;vector long long spltConst32kll() { // 416; return (vector long long)((1<<16) - 1); // 417;} // 418;// P8: 2 x mtvsrd, xxmrghd // 419;// P9: mtvsrdd // 420;vector long long fromRegsll(long long a, long long b) { // 421; return (vector long long){ a, b }; // 422;} // 423;// P8: lxvd2x, xxswapd // 424;// P9: lxvx (or even lxv) // 425;vector long long fromDiffConstsll() { // 426; return (vector long long) { 242, -113 }; // 427;} // 428;// P8: lxvd2x, xxswapd // 429;// P9: lxvx // 430;vector long long fromDiffMemConsAll(long long *arr) { // 431; return (vector long long) { arr[0], arr[1] }; // 432;} // 433;// P8: lxvd2x // 434;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 435;vector long long fromDiffMemConsDll(long long *arr) { // 436; return (vector long long) { arr[3], arr[2] }; // 437;} // 438;// P8: sldi 3, lxvd2x, xxswapd // 439;// P9: sldi 3, lxvx // 440;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 441; return (vector long long) { arr[elem], arr[elem+1] }; // 442;} // 443;// P8: sldi 3, lxvd2x // 444;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 445;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 446; return (vector long long) { arr[elem], arr[elem-1] }; // 447;} // 448;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 449;// P9: 2 x ld, mtvsrdd // 450;vector long long fromRandMemConsll(long long *arr) { // 451; return (vector long long) { arr[4], arr[18] }; // 452;} // 453;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 454;// P9: sldi 3, add, 2 x ld, mtvsrdd // 455;vector long long fromRandMemVarll(long long *arr, int elem) { // 456; return (vector long long) { arr[elem+4], arr[elem+1] }; // 457;} // 458;// P8: mtvsrd, xxspltd // 459;// P9: mtvsrdd // 460;vector long long spltRegValll(long long val) { // 461; return (vector long long) val; // 462;} // 463;// P8: lxvdsx // 464;// P9: lxvdsx // 465;vector long long spltMemValll(long long *ptr) { // 466; return (vector long long)*ptr; // 467;} // 468;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 469;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 470;vector long long spltCnstConvftoll() { // 471; return (vector long long) 4.74f; // 472;} // 473;// P8: xxmrghd, xvcvdpsxds // 474;// P9: xxmrghd, xvcvdpsxds // 475;vector long long fromRegsConvftoll(float a, float b) { // 476; return (vector long long) { a, b }; // 477;} // 478;// P8: lxvd2x, xxswapd // 479;// P9: lxvx (even lxv) // 480;vector long long fromDiffConstsConvftoll() { // 481; return (vector long long) { 24.46f, 234.f }; // 482;} // 483;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 484;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 485;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 486; return (vector long long) { ptr[0], ptr[1] }; // 487;} // 488;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 489;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 490;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 491; return (vector long long) { ptr[3], ptr[2] }; // 492;} // 493;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 494;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 495;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 496; return (vector long long) { arr[elem], arr[elem+1] }; // 497;} // 498;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 499;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 500;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 501; return (vector long long) { arr[elem], arr[elem-1] }; // 502;} // 503;// P8: xscvdpsxds, xxspltd // 504;// P9: xscvdpsxds, xxspltd // 505;vector long long spltRegValConvftoll(float val) { // 506; return (vector long long) val; // 507;} // 508;// P8: lxsspx, xscvdpsxds, xxspltd // 509;// P9: lfs, xscvdpsxds, xxspltd // 510;vector long long spltMemValConvftoll(float *ptr) { // 511; return (vector long long)*ptr; // 512;} // 513;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 514;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 515;vector long long spltCnstConvdtoll() { // 516; return (vector long long) 4.74; // 517;} // 518;// P8: xxmrghd, xvcvdpsxds // 519;// P9: xxmrghd, xvcvdpsxds // 520;vector long long fromRegsConvdtoll(double a, double b) { // 521; return (vector long long) { a, b }; // 522;} // 523;// P8: lxvd2x, xxswapd // 524;// P9: lxvx (even lxv) // 525;vector long long fromDiffConstsConvdtoll() { // 526; return (vector long long) { 24.46, 234. }; // 527;} // 528;// P8: lxvd2x, xxswapd, xvcvdpsxds // 529;// P9: lxvx, xvcvdpsxds // 530;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 531; return (vector long long) { ptr[0], ptr[1] }; // 532;} // 533;// P8: lxvd2x, xvcvdpsxds // 534;// P9: lxvx, xxswapd, xvcvdpsxds // 535;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 536; return (vector long long) { ptr[3], ptr[2] }; // 537;} // 538;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 539;// P9: sldi 3, lxvx, xvcvdpsxds // 540;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 541; return (vector long long) { arr[elem], arr[elem+1] }; // 542;} // 543;// P8: sldi 3, lxvd2x, xvcvdpsxds // 544;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 545;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 546; return (vector long long) { arr[elem], arr[elem-1] }; // 547;} // 548;// P8: xscvdpsxds, xxspltd // 549;// P9: xscvdpsxds, xxspltd // 550;vector long long spltRegValConvdtoll(double val) { // 551; return (vector long long) val; // 552;} // 553;// P8: lxvdsx, xvcvdpsxds // 554;// P9: lxvdsx, xvcvdpsxds // 555;vector long long spltMemValConvdtoll(double *ptr) { // 556; return (vector long long)*ptr; // 557;} // 558;/*=============================== long long =================================*/ 559;/*========================== unsigned long long =============================*/ 560;// P8: xxlxor // 561;// P9: xxlxor // 562;vector unsigned long long allZeroull() { // 563; return (vector unsigned long long)0; // 564;} // 565;// P8: vspltisb -1 // 566;// P9: xxspltisb 255 // 567;vector unsigned long long allOneull() { // 568; return (vector unsigned long long)-1; // 569;} // 570;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 571;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 572;vector unsigned long long spltConst1ull() { // 573; return (vector unsigned long long)1; // 574;} // 575;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 576;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 577;vector unsigned long long spltConst16kull() { // 578; return (vector unsigned long long)((1<<15) - 1); // 579;} // 580;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 581;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 582;vector unsigned long long spltConst32kull() { // 583; return (vector unsigned long long)((1<<16) - 1); // 584;} // 585;// P8: 2 x mtvsrd, xxmrghd // 586;// P9: mtvsrdd // 587;vector unsigned long long fromRegsull(unsigned long long a, // 588; unsigned long long b) { // 589; return (vector unsigned long long){ a, b }; // 590;} // 591;// P8: lxvd2x, xxswapd // 592;// P9: lxvx (or even lxv) // 593;vector unsigned long long fromDiffConstsull() { // 594; return (vector unsigned long long) { 242, -113 }; // 595;} // 596;// P8: lxvd2x, xxswapd // 597;// P9: lxvx // 598;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 599; return (vector unsigned long long) { arr[0], arr[1] }; // 600;} // 601;// P8: lxvd2x // 602;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 603;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 604; return (vector unsigned long long) { arr[3], arr[2] }; // 605;} // 606;// P8: sldi 3, lxvd2x, xxswapd // 607;// P9: sldi 3, lxvx // 608;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 609; int elem) { // 610; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 611;} // 612;// P8: sldi 3, lxvd2x // 613;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 614;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 615; int elem) { // 616; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 617;} // 618;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 619;// P9: 2 x ld, mtvsrdd // 620;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 621; return (vector unsigned long long) { arr[4], arr[18] }; // 622;} // 623;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 624;// P9: sldi 3, add, 2 x ld, mtvsrdd // 625;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 626; int elem) { // 627; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 628;} // 629;// P8: mtvsrd, xxspltd // 630;// P9: mtvsrdd // 631;vector unsigned long long spltRegValull(unsigned long long val) { // 632; return (vector unsigned long long) val; // 633;} // 634;// P8: lxvdsx // 635;// P9: lxvdsx // 636;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 637; return (vector unsigned long long)*ptr; // 638;} // 639;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 640;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 641;vector unsigned long long spltCnstConvftoull() { // 642; return (vector unsigned long long) 4.74f; // 643;} // 644;// P8: xxmrghd, xvcvdpuxds // 645;// P9: xxmrghd, xvcvdpuxds // 646;vector unsigned long long fromRegsConvftoull(float a, float b) { // 647; return (vector unsigned long long) { a, b }; // 648;} // 649;// P8: lxvd2x, xxswapd // 650;// P9: lxvx (even lxv) // 651;vector unsigned long long fromDiffConstsConvftoull() { // 652; return (vector unsigned long long) { 24.46f, 234.f }; // 653;} // 654;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 655;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 656;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 657; return (vector unsigned long long) { ptr[0], ptr[1] }; // 658;} // 659;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 660;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 661;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 662; return (vector unsigned long long) { ptr[3], ptr[2] }; // 663;} // 664;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 665;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 666;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 667; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 668;} // 669;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 670;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 671;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 672; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 673;} // 674;// P8: xscvdpuxds, xxspltd // 675;// P9: xscvdpuxds, xxspltd // 676;vector unsigned long long spltRegValConvftoull(float val) { // 677; return (vector unsigned long long) val; // 678;} // 679;// P8: lxsspx, xscvdpuxds, xxspltd // 680;// P9: lfs, xscvdpuxds, xxspltd // 681;vector unsigned long long spltMemValConvftoull(float *ptr) { // 682; return (vector unsigned long long)*ptr; // 683;} // 684;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 685;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 686;vector unsigned long long spltCnstConvdtoull() { // 687; return (vector unsigned long long) 4.74; // 688;} // 689;// P8: xxmrghd, xvcvdpuxds // 690;// P9: xxmrghd, xvcvdpuxds // 691;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 692; return (vector unsigned long long) { a, b }; // 693;} // 694;// P8: lxvd2x, xxswapd // 695;// P9: lxvx (even lxv) // 696;vector unsigned long long fromDiffConstsConvdtoull() { // 697; return (vector unsigned long long) { 24.46, 234. }; // 698;} // 699;// P8: lxvd2x, xxswapd, xvcvdpuxds // 700;// P9: lxvx, xvcvdpuxds // 701;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 702; return (vector unsigned long long) { ptr[0], ptr[1] }; // 703;} // 704;// P8: lxvd2x, xvcvdpuxds // 705;// P9: lxvx, xxswapd, xvcvdpuxds // 706;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 707; return (vector unsigned long long) { ptr[3], ptr[2] }; // 708;} // 709;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 710;// P9: sldi 3, lxvx, xvcvdpuxds // 711;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 712; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 713;} // 714;// P8: sldi 3, lxvd2x, xvcvdpuxds // 715;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 716;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 717; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 718;} // 719;// P8: xscvdpuxds, xxspltd // 720;// P9: xscvdpuxds, xxspltd // 721;vector unsigned long long spltRegValConvdtoull(double val) { // 722; return (vector unsigned long long) val; // 723;} // 724;// P8: lxvdsx, xvcvdpuxds // 725;// P9: lxvdsx, xvcvdpuxds // 726;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 727; return (vector unsigned long long)*ptr; // 728;} // 729;/*========================== unsigned long long ==============================*/ 730 731; Function Attrs: norecurse nounwind readnone 732define <4 x i32> @allZeroi() { 733entry: 734 ret <4 x i32> zeroinitializer 735; P9BE-LABEL: allZeroi 736; P9LE-LABEL: allZeroi 737; P8BE-LABEL: allZeroi 738; P8LE-LABEL: allZeroi 739; P9BE: xxlxor v2, v2, v2 740; P9BE: blr 741; P9LE: xxlxor v2, v2, v2 742; P9LE: blr 743; P8BE: xxlxor v2, v2, v2 744; P8BE: blr 745; P8LE: xxlxor v2, v2, v2 746; P8LE: blr 747} 748 749; Function Attrs: norecurse nounwind readnone 750define <4 x i32> @allOnei() { 751entry: 752 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 753; P9BE-LABEL: allOnei 754; P9LE-LABEL: allOnei 755; P8BE-LABEL: allOnei 756; P8LE-LABEL: allOnei 757; P9BE: xxspltib v2, 255 758; P9BE: blr 759; P9LE: xxspltib v2, 255 760; P9LE: blr 761; P8BE: vspltisb v2, -1 762; P8BE: blr 763; P8LE: vspltisb v2, -1 764; P8LE: blr 765} 766 767; Function Attrs: norecurse nounwind readnone 768define <4 x i32> @spltConst1i() { 769entry: 770 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 771; P9BE-LABEL: spltConst1i 772; P9LE-LABEL: spltConst1i 773; P8BE-LABEL: spltConst1i 774; P8LE-LABEL: spltConst1i 775; P9BE: vspltisw v2, 1 776; P9BE: blr 777; P9LE: vspltisw v2, 1 778; P9LE: blr 779; P8BE: vspltisw v2, 1 780; P8BE: blr 781; P8LE: vspltisw v2, 1 782; P8LE: blr 783} 784 785; Function Attrs: norecurse nounwind readnone 786define <4 x i32> @spltConst16ki() { 787entry: 788 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 789; P9BE-LABEL: spltConst16ki 790; P9LE-LABEL: spltConst16ki 791; P8BE-LABEL: spltConst16ki 792; P8LE-LABEL: spltConst16ki 793; P9BE: vspltisw v2, -15 794; P9BE: vsrw v2, v2, v2 795; P9BE: blr 796; P9LE: vspltisw v2, -15 797; P9LE: vsrw v2, v2, v2 798; P9LE: blr 799; P8BE: vspltisw v2, -15 800; P8BE: vsrw v2, v2, v2 801; P8BE: blr 802; P8LE: vspltisw v2, -15 803; P8LE: vsrw v2, v2, v2 804; P8LE: blr 805} 806 807; Function Attrs: norecurse nounwind readnone 808define <4 x i32> @spltConst32ki() { 809entry: 810 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 811; P9BE-LABEL: spltConst32ki 812; P9LE-LABEL: spltConst32ki 813; P8BE-LABEL: spltConst32ki 814; P8LE-LABEL: spltConst32ki 815; P9BE: vspltisw v2, -16 816; P9BE: vsrw v2, v2, v2 817; P9BE: blr 818; P9LE: vspltisw v2, -16 819; P9LE: vsrw v2, v2, v2 820; P9LE: blr 821; P8BE: vspltisw v2, -16 822; P8BE: vsrw v2, v2, v2 823; P8BE: blr 824; P8LE: vspltisw v2, -16 825; P8LE: vsrw v2, v2, v2 826; P8LE: blr 827} 828 829; Function Attrs: norecurse nounwind readnone 830define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 831entry: 832 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 833 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 834 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 835 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 836 ret <4 x i32> %vecinit3 837; P9BE-LABEL: fromRegsi 838; P9LE-LABEL: fromRegsi 839; P8BE-LABEL: fromRegsi 840; P8LE-LABEL: fromRegsi 841; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 842; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 843; P9BE: vmrgow v2, [[REG1]], [[REG2]] 844; P9BE: blr 845; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 846; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 847; P9LE: vmrgow v2, [[REG2]], [[REG1]] 848; P9LE: blr 849; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 850; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 851; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 852; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 853; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 854; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 855; P8BE: vmrgow v2, [[REG5]], [[REG6]] 856; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 857; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 858; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 859; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 860; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 861; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 862; P8LE: vmrgow v2, [[REG6]], [[REG5]] 863} 864 865; Function Attrs: norecurse nounwind readnone 866define <4 x i32> @fromDiffConstsi() { 867entry: 868 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 869; P9BE-LABEL: fromDiffConstsi 870; P9LE-LABEL: fromDiffConstsi 871; P8BE-LABEL: fromDiffConstsi 872; P8LE-LABEL: fromDiffConstsi 873; P9BE: lxv 874; P9BE: blr 875; P9LE: lxv 876; P9LE: blr 877; P8BE: lxvw4x 878; P8BE: blr 879; P8LE: lvx 880; P8LE-NOT: xxswapd 881; P8LE: blr 882} 883 884; Function Attrs: norecurse nounwind readonly 885define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 886entry: 887 %0 = load i32, i32* %arr, align 4 888 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 889 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 890 %1 = load i32, i32* %arrayidx1, align 4 891 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 892 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 893 %2 = load i32, i32* %arrayidx3, align 4 894 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 895 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 896 %3 = load i32, i32* %arrayidx5, align 4 897 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 898 ret <4 x i32> %vecinit6 899; P9BE-LABEL: fromDiffMemConsAi 900; P9LE-LABEL: fromDiffMemConsAi 901; P8BE-LABEL: fromDiffMemConsAi 902; P8LE-LABEL: fromDiffMemConsAi 903; P9BE: lxv 904; P9BE: blr 905; P9LE: lxv 906; P9LE: blr 907; P8BE: lxvw4x 908; P8BE: blr 909; P8LE: lxvd2x 910; P8LE: xxswapd 911; P8LE: blr 912} 913 914; Function Attrs: norecurse nounwind readonly 915define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 916entry: 917 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 918 %0 = load i32, i32* %arrayidx, align 4 919 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 920 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 921 %1 = load i32, i32* %arrayidx1, align 4 922 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 923 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 924 %2 = load i32, i32* %arrayidx3, align 4 925 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 926 %3 = load i32, i32* %arr, align 4 927 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 928 ret <4 x i32> %vecinit6 929; P9BE-LABEL: fromDiffMemConsDi 930; P9LE-LABEL: fromDiffMemConsDi 931; P8BE-LABEL: fromDiffMemConsDi 932; P8LE-LABEL: fromDiffMemConsDi 933; P9BE: lxv 934; P9BE: lxv 935; P9BE: vperm 936; P9BE: blr 937; P9LE: lxv 938; P9LE: lxv 939; P9LE: vperm 940; P9LE: blr 941; P8BE: lxvw4x 942; P8BE: lxvw4x 943; P8BE: vperm 944; P8BE: blr 945; P8LE: lxvd2x 946; P8LE-DAG: lvx 947; P8LE: xxswapd 948; P8LE: vperm 949; P8LE: blr 950} 951 952; Function Attrs: norecurse nounwind readonly 953define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 954entry: 955 %idxprom = sext i32 %elem to i64 956 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 957 %0 = load i32, i32* %arrayidx, align 4 958 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 959 %add = add nsw i32 %elem, 1 960 %idxprom1 = sext i32 %add to i64 961 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 962 %1 = load i32, i32* %arrayidx2, align 4 963 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 964 %add4 = add nsw i32 %elem, 2 965 %idxprom5 = sext i32 %add4 to i64 966 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 967 %2 = load i32, i32* %arrayidx6, align 4 968 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 969 %add8 = add nsw i32 %elem, 3 970 %idxprom9 = sext i32 %add8 to i64 971 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 972 %3 = load i32, i32* %arrayidx10, align 4 973 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 974 ret <4 x i32> %vecinit11 975; P9BE-LABEL: fromDiffMemVarAi 976; P9LE-LABEL: fromDiffMemVarAi 977; P8BE-LABEL: fromDiffMemVarAi 978; P8LE-LABEL: fromDiffMemVarAi 979; P9BE: sldi r4, r4, 2 980; P9BE: lxvx v2, r3, r4 981; P9BE: blr 982; P9LE: sldi r4, r4, 2 983; P9LE: lxvx v2, r3, r4 984; P9LE: blr 985; P8BE: sldi r4, r4, 2 986; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 987; P8BE: blr 988; P8LE: sldi r4, r4, 2 989; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 990; P8LE: xxswapd 991; P8LE: blr 992} 993 994; Function Attrs: norecurse nounwind readonly 995define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 996entry: 997 %idxprom = sext i32 %elem to i64 998 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 999 %0 = load i32, i32* %arrayidx, align 4 1000 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1001 %sub = add nsw i32 %elem, -1 1002 %idxprom1 = sext i32 %sub to i64 1003 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1004 %1 = load i32, i32* %arrayidx2, align 4 1005 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1006 %sub4 = add nsw i32 %elem, -2 1007 %idxprom5 = sext i32 %sub4 to i64 1008 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1009 %2 = load i32, i32* %arrayidx6, align 4 1010 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1011 %sub8 = add nsw i32 %elem, -3 1012 %idxprom9 = sext i32 %sub8 to i64 1013 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1014 %3 = load i32, i32* %arrayidx10, align 4 1015 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1016 ret <4 x i32> %vecinit11 1017; P9BE-LABEL: fromDiffMemVarDi 1018; P9LE-LABEL: fromDiffMemVarDi 1019; P8BE-LABEL: fromDiffMemVarDi 1020; P8LE-LABEL: fromDiffMemVarDi 1021; P9BE: sldi {{r[0-9]+}}, r4, 2 1022; P9BE-DAG: lxvx {{v[0-9]+}} 1023; P9BE-DAG: lxvx 1024; P9BE: vperm 1025; P9BE: blr 1026; P9LE: sldi {{r[0-9]+}}, r4, 2 1027; P9LE-DAG: lxvx {{v[0-9]+}} 1028; P9LE-DAG: lxvx 1029; P9LE: vperm 1030; P9LE: blr 1031; P8BE: sldi {{r[0-9]+}}, r4, 2 1032; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 1033; P8BE-DAG: lxvw4x 1034; P8BE: vperm 1035; P8BE: blr 1036; P8LE: sldi {{r[0-9]+}}, r4, 2 1037; P8LE-DAG: lxvd2x 1038; P8LE-DAG: lxvd2x 1039; P8LE: xxswapd 1040; P8LE: vperm 1041; P8LE: blr 1042} 1043 1044; Function Attrs: norecurse nounwind readonly 1045define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1046entry: 1047 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1048 %0 = load i32, i32* %arrayidx, align 4 1049 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1050 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1051 %1 = load i32, i32* %arrayidx1, align 4 1052 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1053 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1054 %2 = load i32, i32* %arrayidx3, align 4 1055 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1056 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1057 %3 = load i32, i32* %arrayidx5, align 4 1058 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1059 ret <4 x i32> %vecinit6 1060; P9BE-LABEL: fromRandMemConsi 1061; P9LE-LABEL: fromRandMemConsi 1062; P8BE-LABEL: fromRandMemConsi 1063; P8LE-LABEL: fromRandMemConsi 1064; P9BE: lwz 1065; P9BE: lwz 1066; P9BE: lwz 1067; P9BE: lwz 1068; P9BE: mtvsrdd 1069; P9BE: mtvsrdd 1070; P9BE: vmrgow 1071; P9LE: lwz 1072; P9LE: lwz 1073; P9LE: lwz 1074; P9LE: lwz 1075; P9LE: mtvsrdd 1076; P9LE: mtvsrdd 1077; P9LE: vmrgow 1078; P8BE: lwz 1079; P8BE: lwz 1080; P8BE: lwz 1081; P8BE: lwz 1082; P8BE: mtvsrwz 1083; P8BE: mtvsrwz 1084; P8BE: mtvsrwz 1085; P8BE: mtvsrwz 1086; P8BE: xxmrghd 1087; P8BE: xxmrghd 1088; P8BE: vmrgow 1089; P8LE: lwz 1090; P8LE: lwz 1091; P8LE: lwz 1092; P8LE: lwz 1093; P8LE: mtvsrwz 1094; P8LE: mtvsrwz 1095; P8LE: mtvsrwz 1096; P8LE: mtvsrwz 1097; P8LE: xxmrghd 1098; P8LE: xxmrghd 1099; P8LE: vmrgow 1100} 1101 1102; Function Attrs: norecurse nounwind readonly 1103define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1104entry: 1105 %add = add nsw i32 %elem, 4 1106 %idxprom = sext i32 %add to i64 1107 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1108 %0 = load i32, i32* %arrayidx, align 4 1109 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1110 %add1 = add nsw i32 %elem, 1 1111 %idxprom2 = sext i32 %add1 to i64 1112 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1113 %1 = load i32, i32* %arrayidx3, align 4 1114 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1115 %add5 = add nsw i32 %elem, 2 1116 %idxprom6 = sext i32 %add5 to i64 1117 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1118 %2 = load i32, i32* %arrayidx7, align 4 1119 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1120 %add9 = add nsw i32 %elem, 8 1121 %idxprom10 = sext i32 %add9 to i64 1122 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1123 %3 = load i32, i32* %arrayidx11, align 4 1124 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1125 ret <4 x i32> %vecinit12 1126; P9BE-LABEL: fromRandMemVari 1127; P9LE-LABEL: fromRandMemVari 1128; P8BE-LABEL: fromRandMemVari 1129; P8LE-LABEL: fromRandMemVari 1130; P9BE: sldi r4, r4, 2 1131; P9BE: lwz 1132; P9BE: lwz 1133; P9BE: lwz 1134; P9BE: lwz 1135; P9BE: mtvsrdd 1136; P9BE: mtvsrdd 1137; P9BE: vmrgow 1138; P9LE: sldi r4, r4, 2 1139; P9LE: lwz 1140; P9LE: lwz 1141; P9LE: lwz 1142; P9LE: lwz 1143; P9LE: mtvsrdd 1144; P9LE: mtvsrdd 1145; P9LE: vmrgow 1146; P8BE: sldi r4, r4, 2 1147; P8BE: lwz 1148; P8BE: lwz 1149; P8BE: lwz 1150; P8BE: lwz 1151; P8BE: mtvsrwz 1152; P8BE: mtvsrwz 1153; P8BE: mtvsrwz 1154; P8BE: mtvsrwz 1155; P8BE: xxmrghd 1156; P8BE: xxmrghd 1157; P8BE: vmrgow 1158; P8LE: sldi r4, r4, 2 1159; P8LE: lwz 1160; P8LE: lwz 1161; P8LE: lwz 1162; P8LE: lwz 1163; P8LE: mtvsrwz 1164; P8LE: mtvsrwz 1165; P8LE: mtvsrwz 1166; P8LE: mtvsrwz 1167; P8LE: xxmrghd 1168; P8LE: xxmrghd 1169; P8LE: vmrgow 1170} 1171 1172; Function Attrs: norecurse nounwind readnone 1173define <4 x i32> @spltRegVali(i32 signext %val) { 1174entry: 1175 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1176 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1177 ret <4 x i32> %splat.splat 1178; P9BE-LABEL: spltRegVali 1179; P9LE-LABEL: spltRegVali 1180; P8BE-LABEL: spltRegVali 1181; P8LE-LABEL: spltRegVali 1182; P9BE: mtvsrws v2, r3 1183; P9BE: blr 1184; P9LE: mtvsrws v2, r3 1185; P9LE: blr 1186; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 1187; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1188; P8BE: blr 1189; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 1190; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1191; P8LE: blr 1192} 1193 1194; Function Attrs: norecurse nounwind readonly 1195define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1196entry: 1197 %0 = load i32, i32* %ptr, align 4 1198 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1199 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1200 ret <4 x i32> %splat.splat 1201; P9BE-LABEL: spltMemVali 1202; P9LE-LABEL: spltMemVali 1203; P8BE-LABEL: spltMemVali 1204; P8LE-LABEL: spltMemVali 1205; P9BE: lxvwsx v2, 0, r3 1206; P9BE: blr 1207; P9LE: lxvwsx v2, 0, r3 1208; P9LE: blr 1209; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 1210; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 1211; P8BE: blr 1212; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 1213; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 1214; P8LE: blr 1215} 1216 1217; Function Attrs: norecurse nounwind readnone 1218define <4 x i32> @spltCnstConvftoi() { 1219entry: 1220 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1221; P9BE-LABEL: spltCnstConvftoi 1222; P9LE-LABEL: spltCnstConvftoi 1223; P8BE-LABEL: spltCnstConvftoi 1224; P8LE-LABEL: spltCnstConvftoi 1225; P9BE: vspltisw v2, 4 1226; P9BE: blr 1227; P9LE: vspltisw v2, 4 1228; P9LE: blr 1229; P8BE: vspltisw v2, 4 1230; P8BE: blr 1231; P8LE: vspltisw v2, 4 1232; P8LE: blr 1233} 1234 1235; Function Attrs: norecurse nounwind readnone 1236define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1237entry: 1238 %conv = fptosi float %a to i32 1239 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1240 %conv1 = fptosi float %b to i32 1241 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1242 %conv3 = fptosi float %c to i32 1243 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1244 %conv5 = fptosi float %d to i32 1245 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1246 ret <4 x i32> %vecinit6 1247; P9BE-LABEL: fromRegsConvftoi 1248; P9LE-LABEL: fromRegsConvftoi 1249; P8BE-LABEL: fromRegsConvftoi 1250; P8LE-LABEL: fromRegsConvftoi 1251; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1252; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1253; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1254; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1255; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1256; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1257; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1258; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1259; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1260; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1261; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1262; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1263; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1264; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1265; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1266; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1267; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1268; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1269; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1270; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1271} 1272 1273; Function Attrs: norecurse nounwind readnone 1274define <4 x i32> @fromDiffConstsConvftoi() { 1275entry: 1276 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1277; P9BE-LABEL: fromDiffConstsConvftoi 1278; P9LE-LABEL: fromDiffConstsConvftoi 1279; P8BE-LABEL: fromDiffConstsConvftoi 1280; P8LE-LABEL: fromDiffConstsConvftoi 1281; P9BE: lxv 1282; P9BE: blr 1283; P9LE: lxv 1284; P9LE: blr 1285; P8BE: lxvw4x 1286; P8BE: blr 1287; P8LE: lvx 1288; P8LE-NOT: xxswapd 1289; P8LE: blr 1290} 1291 1292; Function Attrs: norecurse nounwind readonly 1293define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1294entry: 1295 %0 = bitcast float* %ptr to <4 x float>* 1296 %1 = load <4 x float>, <4 x float>* %0, align 4 1297 %2 = fptosi <4 x float> %1 to <4 x i32> 1298 ret <4 x i32> %2 1299; P9BE-LABEL: fromDiffMemConsAConvftoi 1300; P9LE-LABEL: fromDiffMemConsAConvftoi 1301; P8BE-LABEL: fromDiffMemConsAConvftoi 1302; P8LE-LABEL: fromDiffMemConsAConvftoi 1303; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 1304; P9BE: xvcvspsxws v2, [[REG1]] 1305; P9BE: blr 1306; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 1307; P9LE: xvcvspsxws v2, [[REG1]] 1308; P9LE: blr 1309; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 1310; P8BE: xvcvspsxws v2, [[REG1]] 1311; P8BE: blr 1312; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1313; P8LE: xxswapd 1314; P8LE: xvcvspsxws v2, v2 1315; P8LE: blr 1316} 1317 1318; Function Attrs: norecurse nounwind readonly 1319define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1320entry: 1321 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1322 %0 = load float, float* %arrayidx, align 4 1323 %conv = fptosi float %0 to i32 1324 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1325 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1326 %1 = load float, float* %arrayidx1, align 4 1327 %conv2 = fptosi float %1 to i32 1328 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1329 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1330 %2 = load float, float* %arrayidx4, align 4 1331 %conv5 = fptosi float %2 to i32 1332 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1333 %3 = load float, float* %ptr, align 4 1334 %conv8 = fptosi float %3 to i32 1335 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1336 ret <4 x i32> %vecinit9 1337; P9BE-LABEL: fromDiffMemConsDConvftoi 1338; P9LE-LABEL: fromDiffMemConsDConvftoi 1339; P8BE-LABEL: fromDiffMemConsDConvftoi 1340; P8LE-LABEL: fromDiffMemConsDConvftoi 1341; P9BE: lxv 1342; P9BE: lxv 1343; P9BE: vperm 1344; P9BE: xvcvspsxws 1345; P9BE: blr 1346; P9LE: lxv 1347; P9LE: lxv 1348; P9LE: vperm 1349; P9LE: xvcvspsxws 1350; P9LE: blr 1351; P8BE: lxvw4x 1352; P8BE: lxvw4x 1353; P8BE: vperm 1354; P8BE: xvcvspsxws 1355; P8BE: blr 1356; P8LE: lxvd2x 1357; P8LE-DAG: lvx 1358; P8LE: xxswapd 1359; P8LE: vperm 1360; P8LE: xvcvspsxws 1361; P8LE: blr 1362} 1363 1364; Function Attrs: norecurse nounwind readonly 1365define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1366entry: 1367 %idxprom = sext i32 %elem to i64 1368 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1369 %0 = load float, float* %arrayidx, align 4 1370 %conv = fptosi float %0 to i32 1371 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1372 %add = add nsw i32 %elem, 1 1373 %idxprom1 = sext i32 %add to i64 1374 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1375 %1 = load float, float* %arrayidx2, align 4 1376 %conv3 = fptosi float %1 to i32 1377 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1378 %add5 = add nsw i32 %elem, 2 1379 %idxprom6 = sext i32 %add5 to i64 1380 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1381 %2 = load float, float* %arrayidx7, align 4 1382 %conv8 = fptosi float %2 to i32 1383 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1384 %add10 = add nsw i32 %elem, 3 1385 %idxprom11 = sext i32 %add10 to i64 1386 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1387 %3 = load float, float* %arrayidx12, align 4 1388 %conv13 = fptosi float %3 to i32 1389 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1390 ret <4 x i32> %vecinit14 1391; P9BE-LABEL: fromDiffMemVarAConvftoi 1392; P9LE-LABEL: fromDiffMemVarAConvftoi 1393; P8BE-LABEL: fromDiffMemVarAConvftoi 1394; P8LE-LABEL: fromDiffMemVarAConvftoi 1395; FIXME: implement finding consecutive loads with pre-inc 1396; P9BE: lfsux 1397; P9LE: lfsux 1398; P8BE: lfsux 1399; P8LE: lfsux 1400} 1401 1402; Function Attrs: norecurse nounwind readonly 1403define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1404entry: 1405 %idxprom = sext i32 %elem to i64 1406 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1407 %0 = load float, float* %arrayidx, align 4 1408 %conv = fptosi float %0 to i32 1409 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1410 %sub = add nsw i32 %elem, -1 1411 %idxprom1 = sext i32 %sub to i64 1412 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1413 %1 = load float, float* %arrayidx2, align 4 1414 %conv3 = fptosi float %1 to i32 1415 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1416 %sub5 = add nsw i32 %elem, -2 1417 %idxprom6 = sext i32 %sub5 to i64 1418 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1419 %2 = load float, float* %arrayidx7, align 4 1420 %conv8 = fptosi float %2 to i32 1421 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1422 %sub10 = add nsw i32 %elem, -3 1423 %idxprom11 = sext i32 %sub10 to i64 1424 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1425 %3 = load float, float* %arrayidx12, align 4 1426 %conv13 = fptosi float %3 to i32 1427 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1428 ret <4 x i32> %vecinit14 1429; P9BE-LABEL: fromDiffMemVarDConvftoi 1430; P9LE-LABEL: fromDiffMemVarDConvftoi 1431; P8BE-LABEL: fromDiffMemVarDConvftoi 1432; P8LE-LABEL: fromDiffMemVarDConvftoi 1433; FIXME: implement finding consecutive loads with pre-inc 1434; P9BE: lfsux 1435; P9LE: lfsux 1436; P8BE: lfsux 1437; P8LE: lfsux 1438} 1439 1440; Function Attrs: norecurse nounwind readnone 1441define <4 x i32> @spltRegValConvftoi(float %val) { 1442entry: 1443 %conv = fptosi float %val to i32 1444 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1445 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1446 ret <4 x i32> %splat.splat 1447; P9BE-LABEL: spltRegValConvftoi 1448; P9LE-LABEL: spltRegValConvftoi 1449; P8BE-LABEL: spltRegValConvftoi 1450; P8LE-LABEL: spltRegValConvftoi 1451; P9BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1452; P9BE: xxspltw v2, vs[[REG1]], 1 1453; P9BE: blr 1454; P9LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1455; P9LE: xxspltw v2, vs[[REG1]], 1 1456; P9LE: blr 1457; P8BE: xscvdpsxws f[[REG1:[0-9]+]], f1 1458; P8BE: xxspltw v2, vs[[REG1]], 1 1459; P8BE: blr 1460; P8LE: xscvdpsxws f[[REG1:[0-9]+]], f1 1461; P8LE: xxspltw v2, vs[[REG1]], 1 1462; P8LE: blr 1463} 1464 1465; Function Attrs: norecurse nounwind readonly 1466define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1467entry: 1468 %0 = load float, float* %ptr, align 4 1469 %conv = fptosi float %0 to i32 1470 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1471 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1472 ret <4 x i32> %splat.splat 1473; P9BE-LABEL: spltMemValConvftoi 1474; P9LE-LABEL: spltMemValConvftoi 1475; P8BE-LABEL: spltMemValConvftoi 1476; P8LE-LABEL: spltMemValConvftoi 1477; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 1478; P9BE: xvcvspsxws v2, [[REG1]] 1479; P9LE: [[REG1:[vs0-9]+]], 0, r3 1480; P9LE: xvcvspsxws v2, [[REG1]] 1481; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 1482; P8BE: xscvdpsxws f[[REG2:[0-9]+]], [[REG1]] 1483; P8BE: xxspltw v2, vs[[REG2]], 1 1484; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 1485; P8LE: xscvdpsxws f[[REG2:[vs0-9]+]], [[REG1]] 1486; P8LE: xxspltw v2, vs[[REG2]], 1 1487} 1488 1489; Function Attrs: norecurse nounwind readnone 1490define <4 x i32> @spltCnstConvdtoi() { 1491entry: 1492 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1493; P9BE-LABEL: spltCnstConvdtoi 1494; P9LE-LABEL: spltCnstConvdtoi 1495; P8BE-LABEL: spltCnstConvdtoi 1496; P8LE-LABEL: spltCnstConvdtoi 1497; P9BE: vspltisw v2, 4 1498; P9BE: blr 1499; P9LE: vspltisw v2, 4 1500; P9LE: blr 1501; P8BE: vspltisw v2, 4 1502; P8BE: blr 1503; P8LE: vspltisw v2, 4 1504; P8LE: blr 1505} 1506 1507; Function Attrs: norecurse nounwind readnone 1508define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1509entry: 1510 %conv = fptosi double %a to i32 1511 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1512 %conv1 = fptosi double %b to i32 1513 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1514 %conv3 = fptosi double %c to i32 1515 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1516 %conv5 = fptosi double %d to i32 1517 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1518 ret <4 x i32> %vecinit6 1519; P9BE-LABEL: fromRegsConvdtoi 1520; P9LE-LABEL: fromRegsConvdtoi 1521; P8BE-LABEL: fromRegsConvdtoi 1522; P8LE-LABEL: fromRegsConvdtoi 1523; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1524; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1525; P9BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1526; P9BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1527; P9BE: vmrgew v2, [[REG3]], [[REG4]] 1528; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1529; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1530; P9LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1531; P9LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1532; P9LE: vmrgew v2, [[REG4]], [[REG3]] 1533; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 1534; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 1535; P8BE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1536; P8BE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1537; P8BE: vmrgew v2, [[REG3]], [[REG4]] 1538; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 1539; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 1540; P8LE-DAG: xvcvdpsxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 1541; P8LE-DAG: xvcvdpsxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 1542; P8LE: vmrgew v2, [[REG4]], [[REG3]] 1543} 1544 1545; Function Attrs: norecurse nounwind readnone 1546define <4 x i32> @fromDiffConstsConvdtoi() { 1547entry: 1548 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1549; P9BE-LABEL: fromDiffConstsConvdtoi 1550; P9LE-LABEL: fromDiffConstsConvdtoi 1551; P8BE-LABEL: fromDiffConstsConvdtoi 1552; P8LE-LABEL: fromDiffConstsConvdtoi 1553; P9BE: lxv 1554; P9BE: blr 1555; P9LE: lxv 1556; P9LE: blr 1557; P8BE: lxvw4x 1558; P8BE: blr 1559; P8LE: lvx 1560; P8LE-NOT: xxswapd 1561; P8LE: blr 1562} 1563 1564; Function Attrs: norecurse nounwind readonly 1565define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1566entry: 1567 %0 = bitcast double* %ptr to <2 x double>* 1568 %1 = load <2 x double>, <2 x double>* %0, align 8 1569 %2 = fptosi <2 x double> %1 to <2 x i32> 1570 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1571 %3 = bitcast double* %arrayidx4 to <2 x double>* 1572 %4 = load <2 x double>, <2 x double>* %3, align 8 1573 %5 = fptosi <2 x double> %4 to <2 x i32> 1574 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1575 ret <4 x i32> %vecinit9 1576; P9BE-LABEL: fromDiffMemConsAConvdtoi 1577; P9LE-LABEL: fromDiffMemConsAConvdtoi 1578; P8BE-LABEL: fromDiffMemConsAConvdtoi 1579; P8LE-LABEL: fromDiffMemConsAConvdtoi 1580; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 1581; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 1582; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1583; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1584; P9BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1585; P9BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1586; P9BE: vmrgew v2, [[REG6]], [[REG5]] 1587; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 1588; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 1589; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 1590; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 1591; P9LE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1592; P9LE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1593; P9LE: vmrgew v2, [[REG6]], [[REG5]] 1594; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1595; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1596; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 1597; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 1598; P8BE-DAG: xvcvdpsxws [[REG5:[vs0-9]+]], [[REG3]] 1599; P8BE-DAG: xvcvdpsxws [[REG6:[vs0-9]+]], [[REG4]] 1600; P8BE: vmrgew v2, [[REG6]], [[REG5]] 1601; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 1602; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 1603; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 1604; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 1605; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 1606; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 1607; P8LE-DAG: xvcvdpsxws [[REG7:[vs0-9]+]], [[REG5]] 1608; P8LE-DAG: xvcvdpsxws [[REG8:[vs0-9]+]], [[REG6]] 1609; P8LE: vmrgew v2, [[REG8]], [[REG7]] 1610} 1611 1612; Function Attrs: norecurse nounwind readonly 1613define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1614entry: 1615 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1616 %0 = load double, double* %arrayidx, align 8 1617 %conv = fptosi double %0 to i32 1618 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1619 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1620 %1 = load double, double* %arrayidx1, align 8 1621 %conv2 = fptosi double %1 to i32 1622 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1623 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1624 %2 = load double, double* %arrayidx4, align 8 1625 %conv5 = fptosi double %2 to i32 1626 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1627 %3 = load double, double* %ptr, align 8 1628 %conv8 = fptosi double %3 to i32 1629 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1630 ret <4 x i32> %vecinit9 1631; P9BE-LABEL: fromDiffMemConsDConvdtoi 1632; P9LE-LABEL: fromDiffMemConsDConvdtoi 1633; P8BE-LABEL: fromDiffMemConsDConvdtoi 1634; P8LE-LABEL: fromDiffMemConsDConvdtoi 1635; P9BE: lfd 1636; P9BE: lfd 1637; P9BE: lfd 1638; P9BE: lfd 1639; P9BE: xxmrghd 1640; P9BE: xxmrghd 1641; P9BE: xvcvdpsxws 1642; P9BE: xvcvdpsxws 1643; P9BE: vmrgew v2 1644; P9LE: lfd 1645; P9LE: lfd 1646; P9LE: lfd 1647; P9LE: lfd 1648; P9LE: xxmrghd 1649; P9LE: xxmrghd 1650; P9LE: xvcvdpsxws 1651; P9LE: xvcvdpsxws 1652; P9LE: vmrgew v2 1653; P8BE: lfdx 1654; P8BE: lfd 1655; P8BE: lfd 1656; P8BE: lfd 1657; P8BE: xxmrghd 1658; P8BE: xxmrghd 1659; P8BE: xvcvdpsxws 1660; P8BE: xvcvdpsxws 1661; P8BE: vmrgew v2 1662; P8LE: lfdx 1663; P8LE: lfd 1664; P8LE: lfd 1665; P8LE: lfd 1666; P8LE: xxmrghd 1667; P8LE: xxmrghd 1668; P8LE: xvcvdpsxws 1669; P8LE: xvcvdpsxws 1670; P8LE: vmrgew v2 1671} 1672 1673; Function Attrs: norecurse nounwind readonly 1674define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1675entry: 1676 %idxprom = sext i32 %elem to i64 1677 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1678 %0 = load double, double* %arrayidx, align 8 1679 %conv = fptosi double %0 to i32 1680 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1681 %add = add nsw i32 %elem, 1 1682 %idxprom1 = sext i32 %add to i64 1683 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1684 %1 = load double, double* %arrayidx2, align 8 1685 %conv3 = fptosi double %1 to i32 1686 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1687 %add5 = add nsw i32 %elem, 2 1688 %idxprom6 = sext i32 %add5 to i64 1689 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1690 %2 = load double, double* %arrayidx7, align 8 1691 %conv8 = fptosi double %2 to i32 1692 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1693 %add10 = add nsw i32 %elem, 3 1694 %idxprom11 = sext i32 %add10 to i64 1695 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1696 %3 = load double, double* %arrayidx12, align 8 1697 %conv13 = fptosi double %3 to i32 1698 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1699 ret <4 x i32> %vecinit14 1700; P9BE-LABEL: fromDiffMemVarAConvdtoi 1701; P9LE-LABEL: fromDiffMemVarAConvdtoi 1702; P8BE-LABEL: fromDiffMemVarAConvdtoi 1703; P8LE-LABEL: fromDiffMemVarAConvdtoi 1704; P9BE: lfdux 1705; P9BE: lfd 1706; P9BE: lfd 1707; P9BE: lfd 1708; P9BE: xxmrghd 1709; P9BE: xxmrghd 1710; P9BE: xvcvdpsxws 1711; P9BE: xvcvdpsxws 1712; P9BE: vmrgew v2 1713; P9LE: lfdux 1714; P9LE: lfd 1715; P9LE: lfd 1716; P9LE: lfd 1717; P9LE: xxmrghd 1718; P9LE: xxmrghd 1719; P9LE: xvcvdpsxws 1720; P9LE: xvcvdpsxws 1721; P9LE: vmrgew v2 1722; P8BE: lfdux 1723; P8BE: lfd 1724; P8BE: lfd 1725; P8BE: lfd 1726; P8BE: xxmrghd 1727; P8BE: xxmrghd 1728; P8BE: xvcvdpsxws 1729; P8BE: xvcvdpsxws 1730; P8BE: vmrgew v2 1731; P8LE: lfdux 1732; P8LE: lfd 1733; P8LE: lfd 1734; P8LE: lfd 1735; P8LE: xxmrghd 1736; P8LE: xxmrghd 1737; P8LE: xvcvdpsxws 1738; P8LE: xvcvdpsxws 1739; P8LE: vmrgew v2 1740} 1741 1742; Function Attrs: norecurse nounwind readonly 1743define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1744entry: 1745 %idxprom = sext i32 %elem to i64 1746 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 1747 %0 = load double, double* %arrayidx, align 8 1748 %conv = fptosi double %0 to i32 1749 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1750 %sub = add nsw i32 %elem, -1 1751 %idxprom1 = sext i32 %sub to i64 1752 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 1753 %1 = load double, double* %arrayidx2, align 8 1754 %conv3 = fptosi double %1 to i32 1755 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1756 %sub5 = add nsw i32 %elem, -2 1757 %idxprom6 = sext i32 %sub5 to i64 1758 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 1759 %2 = load double, double* %arrayidx7, align 8 1760 %conv8 = fptosi double %2 to i32 1761 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1762 %sub10 = add nsw i32 %elem, -3 1763 %idxprom11 = sext i32 %sub10 to i64 1764 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 1765 %3 = load double, double* %arrayidx12, align 8 1766 %conv13 = fptosi double %3 to i32 1767 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1768 ret <4 x i32> %vecinit14 1769; P9BE-LABEL: fromDiffMemVarDConvdtoi 1770; P9LE-LABEL: fromDiffMemVarDConvdtoi 1771; P8BE-LABEL: fromDiffMemVarDConvdtoi 1772; P8LE-LABEL: fromDiffMemVarDConvdtoi 1773; P9BE: lfdux 1774; P9BE: lfd 1775; P9BE: lfd 1776; P9BE: lfd 1777; P9BE: xxmrghd 1778; P9BE: xxmrghd 1779; P9BE: xvcvdpsxws 1780; P9BE: xvcvdpsxws 1781; P9BE: vmrgew v2 1782; P9LE: lfdux 1783; P9LE: lfd 1784; P9LE: lfd 1785; P9LE: lfd 1786; P9LE: xxmrghd 1787; P9LE: xxmrghd 1788; P9LE: xvcvdpsxws 1789; P9LE: xvcvdpsxws 1790; P9LE: vmrgew v2 1791; P8BE: lfdux 1792; P8BE: lfd 1793; P8BE: lfd 1794; P8BE: lfd 1795; P8BE: xxmrghd 1796; P8BE: xxmrghd 1797; P8BE: xvcvdpsxws 1798; P8BE: xvcvdpsxws 1799; P8BE: vmrgew v2 1800; P8LE: lfdux 1801; P8LE: lfd 1802; P8LE: lfd 1803; P8LE: lfd 1804; P8LE: xxmrghd 1805; P8LE: xxmrghd 1806; P8LE: xvcvdpsxws 1807; P8LE: xvcvdpsxws 1808; P8LE: vmrgew v2 1809} 1810 1811; Function Attrs: norecurse nounwind readnone 1812define <4 x i32> @spltRegValConvdtoi(double %val) { 1813entry: 1814 %conv = fptosi double %val to i32 1815 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1816 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1817 ret <4 x i32> %splat.splat 1818; P9BE-LABEL: spltRegValConvdtoi 1819; P9LE-LABEL: spltRegValConvdtoi 1820; P8BE-LABEL: spltRegValConvdtoi 1821; P8LE-LABEL: spltRegValConvdtoi 1822; P9BE: xscvdpsxws 1823; P9BE: xxspltw 1824; P9BE: blr 1825; P9LE: xscvdpsxws 1826; P9LE: xxspltw 1827; P9LE: blr 1828; P8BE: xscvdpsxws 1829; P8BE: xxspltw 1830; P8BE: blr 1831; P8LE: xscvdpsxws 1832; P8LE: xxspltw 1833; P8LE: blr 1834} 1835 1836; Function Attrs: norecurse nounwind readonly 1837define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 1838entry: 1839 %0 = load double, double* %ptr, align 8 1840 %conv = fptosi double %0 to i32 1841 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1842 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1843 ret <4 x i32> %splat.splat 1844; P9BE-LABEL: spltMemValConvdtoi 1845; P9LE-LABEL: spltMemValConvdtoi 1846; P8BE-LABEL: spltMemValConvdtoi 1847; P8LE-LABEL: spltMemValConvdtoi 1848; P9BE: lfd 1849; P9BE: xscvdpsxws 1850; P9BE: xxspltw 1851; P9BE: blr 1852; P9LE: lfd 1853; P9LE: xscvdpsxws 1854; P9LE: xxspltw 1855; P9LE: blr 1856; P8BE: lfdx 1857; P8BE: xscvdpsxws 1858; P8BE: xxspltw 1859; P8BE: blr 1860; P8LE: lfdx 1861; P8LE: xscvdpsxws 1862; P8LE: xxspltw 1863; P8LE: blr 1864} 1865; Function Attrs: norecurse nounwind readnone 1866define <4 x i32> @allZeroui() { 1867entry: 1868 ret <4 x i32> zeroinitializer 1869; P9BE-LABEL: allZeroui 1870; P9LE-LABEL: allZeroui 1871; P8BE-LABEL: allZeroui 1872; P8LE-LABEL: allZeroui 1873; P9BE: xxlxor v2, v2, v2 1874; P9BE: blr 1875; P9LE: xxlxor v2, v2, v2 1876; P9LE: blr 1877; P8BE: xxlxor v2, v2, v2 1878; P8BE: blr 1879; P8LE: xxlxor v2, v2, v2 1880; P8LE: blr 1881} 1882 1883; Function Attrs: norecurse nounwind readnone 1884define <4 x i32> @allOneui() { 1885entry: 1886 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 1887; P9BE-LABEL: allOneui 1888; P9LE-LABEL: allOneui 1889; P8BE-LABEL: allOneui 1890; P8LE-LABEL: allOneui 1891; P9BE: xxspltib v2, 255 1892; P9BE: blr 1893; P9LE: xxspltib v2, 255 1894; P9LE: blr 1895; P8BE: vspltisb v2, -1 1896; P8BE: blr 1897; P8LE: vspltisb v2, -1 1898; P8LE: blr 1899} 1900 1901; Function Attrs: norecurse nounwind readnone 1902define <4 x i32> @spltConst1ui() { 1903entry: 1904 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 1905; P9BE-LABEL: spltConst1ui 1906; P9LE-LABEL: spltConst1ui 1907; P8BE-LABEL: spltConst1ui 1908; P8LE-LABEL: spltConst1ui 1909; P9BE: vspltisw v2, 1 1910; P9BE: blr 1911; P9LE: vspltisw v2, 1 1912; P9LE: blr 1913; P8BE: vspltisw v2, 1 1914; P8BE: blr 1915; P8LE: vspltisw v2, 1 1916; P8LE: blr 1917} 1918 1919; Function Attrs: norecurse nounwind readnone 1920define <4 x i32> @spltConst16kui() { 1921entry: 1922 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 1923; P9BE-LABEL: spltConst16kui 1924; P9LE-LABEL: spltConst16kui 1925; P8BE-LABEL: spltConst16kui 1926; P8LE-LABEL: spltConst16kui 1927; P9BE: vspltisw v2, -15 1928; P9BE: vsrw v2, v2, v2 1929; P9BE: blr 1930; P9LE: vspltisw v2, -15 1931; P9LE: vsrw v2, v2, v2 1932; P9LE: blr 1933; P8BE: vspltisw v2, -15 1934; P8BE: vsrw v2, v2, v2 1935; P8BE: blr 1936; P8LE: vspltisw v2, -15 1937; P8LE: vsrw v2, v2, v2 1938; P8LE: blr 1939} 1940 1941; Function Attrs: norecurse nounwind readnone 1942define <4 x i32> @spltConst32kui() { 1943entry: 1944 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 1945; P9BE-LABEL: spltConst32kui 1946; P9LE-LABEL: spltConst32kui 1947; P8BE-LABEL: spltConst32kui 1948; P8LE-LABEL: spltConst32kui 1949; P9BE: vspltisw v2, -16 1950; P9BE: vsrw v2, v2, v2 1951; P9BE: blr 1952; P9LE: vspltisw v2, -16 1953; P9LE: vsrw v2, v2, v2 1954; P9LE: blr 1955; P8BE: vspltisw v2, -16 1956; P8BE: vsrw v2, v2, v2 1957; P8BE: blr 1958; P8LE: vspltisw v2, -16 1959; P8LE: vsrw v2, v2, v2 1960; P8LE: blr 1961} 1962 1963; Function Attrs: norecurse nounwind readnone 1964define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 1965entry: 1966 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 1967 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 1968 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 1969 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 1970 ret <4 x i32> %vecinit3 1971; P9BE-LABEL: fromRegsui 1972; P9LE-LABEL: fromRegsui 1973; P8BE-LABEL: fromRegsui 1974; P8LE-LABEL: fromRegsui 1975; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5 1976; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6 1977; P9BE: vmrgow v2, [[REG1]], [[REG2]] 1978; P9BE: blr 1979; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3 1980; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4 1981; P9LE: vmrgow v2, [[REG2]], [[REG1]] 1982; P9LE: blr 1983; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 1984; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 1985; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 1986; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 1987; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]] 1988; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]] 1989; P8BE: vmrgow v2, [[REG5]], [[REG6]] 1990; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3 1991; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4 1992; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5 1993; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6 1994; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]] 1995; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]] 1996; P8LE: vmrgow v2, [[REG6]], [[REG5]] 1997} 1998 1999; Function Attrs: norecurse nounwind readnone 2000define <4 x i32> @fromDiffConstsui() { 2001entry: 2002 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2003; P9BE-LABEL: fromDiffConstsui 2004; P9LE-LABEL: fromDiffConstsui 2005; P8BE-LABEL: fromDiffConstsui 2006; P8LE-LABEL: fromDiffConstsui 2007; P9BE: lxv 2008; P9BE: blr 2009; P9LE: lxv 2010; P9LE: blr 2011; P8BE: lxvw4x 2012; P8BE: blr 2013; P8LE: lvx 2014; P8LE-NOT: xxswapd 2015; P8LE: blr 2016} 2017 2018; Function Attrs: norecurse nounwind readonly 2019define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2020entry: 2021 %0 = load i32, i32* %arr, align 4 2022 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2023 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2024 %1 = load i32, i32* %arrayidx1, align 4 2025 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2026 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2027 %2 = load i32, i32* %arrayidx3, align 4 2028 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2029 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2030 %3 = load i32, i32* %arrayidx5, align 4 2031 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2032 ret <4 x i32> %vecinit6 2033; P9BE-LABEL: fromDiffMemConsAui 2034; P9LE-LABEL: fromDiffMemConsAui 2035; P8BE-LABEL: fromDiffMemConsAui 2036; P8LE-LABEL: fromDiffMemConsAui 2037; P9BE: lxv 2038; P9BE: blr 2039; P9LE: lxv 2040; P9LE: blr 2041; P8BE: lxvw4x 2042; P8BE: blr 2043; P8LE: lxvd2x 2044; P8LE: xxswapd 2045; P8LE: blr 2046} 2047 2048; Function Attrs: norecurse nounwind readonly 2049define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2050entry: 2051 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2052 %0 = load i32, i32* %arrayidx, align 4 2053 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2054 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2055 %1 = load i32, i32* %arrayidx1, align 4 2056 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2057 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2058 %2 = load i32, i32* %arrayidx3, align 4 2059 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2060 %3 = load i32, i32* %arr, align 4 2061 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2062 ret <4 x i32> %vecinit6 2063; P9BE-LABEL: fromDiffMemConsDui 2064; P9LE-LABEL: fromDiffMemConsDui 2065; P8BE-LABEL: fromDiffMemConsDui 2066; P8LE-LABEL: fromDiffMemConsDui 2067; P9BE: lxv 2068; P9BE: lxv 2069; P9BE: vperm 2070; P9BE: blr 2071; P9LE: lxv 2072; P9LE: lxv 2073; P9LE: vperm 2074; P9LE: blr 2075; P8BE: lxvw4x 2076; P8BE: lxvw4x 2077; P8BE: vperm 2078; P8BE: blr 2079; P8LE: lxvd2x 2080; P8LE-DAG: lvx 2081; P8LE-NOT: xxswapd 2082; P8LE: xxswapd 2083; P8LE: vperm 2084; P8LE: blr 2085} 2086 2087; Function Attrs: norecurse nounwind readonly 2088define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2089entry: 2090 %idxprom = sext i32 %elem to i64 2091 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2092 %0 = load i32, i32* %arrayidx, align 4 2093 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2094 %add = add nsw i32 %elem, 1 2095 %idxprom1 = sext i32 %add to i64 2096 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2097 %1 = load i32, i32* %arrayidx2, align 4 2098 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2099 %add4 = add nsw i32 %elem, 2 2100 %idxprom5 = sext i32 %add4 to i64 2101 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2102 %2 = load i32, i32* %arrayidx6, align 4 2103 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2104 %add8 = add nsw i32 %elem, 3 2105 %idxprom9 = sext i32 %add8 to i64 2106 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2107 %3 = load i32, i32* %arrayidx10, align 4 2108 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2109 ret <4 x i32> %vecinit11 2110; P9BE-LABEL: fromDiffMemVarAui 2111; P9LE-LABEL: fromDiffMemVarAui 2112; P8BE-LABEL: fromDiffMemVarAui 2113; P8LE-LABEL: fromDiffMemVarAui 2114; P9BE: sldi r4, r4, 2 2115; P9BE: lxvx v2, r3, r4 2116; P9BE: blr 2117; P9LE: sldi r4, r4, 2 2118; P9LE: lxvx v2, r3, r4 2119; P9LE: blr 2120; P8BE: sldi r4, r4, 2 2121; P8BE: lxvw4x {{[vs0-9]+}}, r3, r4 2122; P8BE: blr 2123; P8LE: sldi r4, r4, 2 2124; P8LE: lxvd2x {{[vs0-9]+}}, r3, r4 2125; P8LE: xxswapd 2126; P8LE: blr 2127} 2128 2129; Function Attrs: norecurse nounwind readonly 2130define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2131entry: 2132 %idxprom = sext i32 %elem to i64 2133 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2134 %0 = load i32, i32* %arrayidx, align 4 2135 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2136 %sub = add nsw i32 %elem, -1 2137 %idxprom1 = sext i32 %sub to i64 2138 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2139 %1 = load i32, i32* %arrayidx2, align 4 2140 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2141 %sub4 = add nsw i32 %elem, -2 2142 %idxprom5 = sext i32 %sub4 to i64 2143 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2144 %2 = load i32, i32* %arrayidx6, align 4 2145 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2146 %sub8 = add nsw i32 %elem, -3 2147 %idxprom9 = sext i32 %sub8 to i64 2148 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2149 %3 = load i32, i32* %arrayidx10, align 4 2150 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2151 ret <4 x i32> %vecinit11 2152; P9BE-LABEL: fromDiffMemVarDui 2153; P9LE-LABEL: fromDiffMemVarDui 2154; P8BE-LABEL: fromDiffMemVarDui 2155; P8LE-LABEL: fromDiffMemVarDui 2156; P9BE-DAG: sldi {{r[0-9]+}}, r4, 2 2157; P9BE-DAG: addi r3, r3, -12 2158; P9BE-DAG: lxvx {{v[0-9]+}}, 0, r3 2159; P9BE-DAG: lxvx 2160; P9BE: vperm 2161; P9BE: blr 2162; P9LE-DAG: sldi {{r[0-9]+}}, r4, 2 2163; P9LE-DAG: addi r3, r3, -12 2164; P9LE-DAG: lxvx {{v[0-9]+}}, 0, r3 2165; P9LE-DAG: lxv 2166; P9LE: vperm 2167; P9LE: blr 2168; P8BE-DAG: sldi {{r[0-9]+}}, r4, 2 2169; P8BE-DAG: lxvw4x {{v[0-9]+}}, 0, r3 2170; P8BE-DAG: lxvw4x 2171; P8BE: vperm 2172; P8BE: blr 2173; P8LE-DAG: sldi {{r[0-9]+}}, r4, 2 2174; P8LE-DAG: lvx 2175; P8LE-DAG: lvx 2176; P8LE: vperm 2177; P8LE: blr 2178} 2179 2180; Function Attrs: norecurse nounwind readonly 2181define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2182entry: 2183 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2184 %0 = load i32, i32* %arrayidx, align 4 2185 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2186 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2187 %1 = load i32, i32* %arrayidx1, align 4 2188 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2189 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2190 %2 = load i32, i32* %arrayidx3, align 4 2191 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2192 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2193 %3 = load i32, i32* %arrayidx5, align 4 2194 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2195 ret <4 x i32> %vecinit6 2196; P9BE-LABEL: fromRandMemConsui 2197; P9LE-LABEL: fromRandMemConsui 2198; P8BE-LABEL: fromRandMemConsui 2199; P8LE-LABEL: fromRandMemConsui 2200; P9BE: lwz 2201; P9BE: lwz 2202; P9BE: lwz 2203; P9BE: lwz 2204; P9BE: mtvsrdd 2205; P9BE: mtvsrdd 2206; P9BE: vmrgow 2207; P9LE: lwz 2208; P9LE: lwz 2209; P9LE: lwz 2210; P9LE: lwz 2211; P9LE: mtvsrdd 2212; P9LE: mtvsrdd 2213; P9LE: vmrgow 2214; P8BE: lwz 2215; P8BE: lwz 2216; P8BE: lwz 2217; P8BE: lwz 2218; P8BE: mtvsrwz 2219; P8BE: mtvsrwz 2220; P8BE: mtvsrwz 2221; P8BE: mtvsrwz 2222; P8BE: xxmrghd 2223; P8BE: xxmrghd 2224; P8BE: vmrgow 2225; P8LE: lwz 2226; P8LE: lwz 2227; P8LE: lwz 2228; P8LE: lwz 2229; P8LE: mtvsrwz 2230; P8LE: mtvsrwz 2231; P8LE: mtvsrwz 2232; P8LE: mtvsrwz 2233; P8LE: xxmrghd 2234; P8LE: xxmrghd 2235; P8LE: vmrgow 2236} 2237 2238; Function Attrs: norecurse nounwind readonly 2239define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2240entry: 2241 %add = add nsw i32 %elem, 4 2242 %idxprom = sext i32 %add to i64 2243 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2244 %0 = load i32, i32* %arrayidx, align 4 2245 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2246 %add1 = add nsw i32 %elem, 1 2247 %idxprom2 = sext i32 %add1 to i64 2248 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2249 %1 = load i32, i32* %arrayidx3, align 4 2250 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2251 %add5 = add nsw i32 %elem, 2 2252 %idxprom6 = sext i32 %add5 to i64 2253 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2254 %2 = load i32, i32* %arrayidx7, align 4 2255 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2256 %add9 = add nsw i32 %elem, 8 2257 %idxprom10 = sext i32 %add9 to i64 2258 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2259 %3 = load i32, i32* %arrayidx11, align 4 2260 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2261 ret <4 x i32> %vecinit12 2262; P9BE-LABEL: fromRandMemVarui 2263; P9LE-LABEL: fromRandMemVarui 2264; P8BE-LABEL: fromRandMemVarui 2265; P8LE-LABEL: fromRandMemVarui 2266; P9BE: sldi r4, r4, 2 2267; P9BE: lwz 2268; P9BE: lwz 2269; P9BE: lwz 2270; P9BE: lwz 2271; P9BE: mtvsrdd 2272; P9BE: mtvsrdd 2273; P9BE: vmrgow 2274; P9LE: sldi r4, r4, 2 2275; P9LE: lwz 2276; P9LE: lwz 2277; P9LE: lwz 2278; P9LE: lwz 2279; P9LE: mtvsrdd 2280; P9LE: mtvsrdd 2281; P9LE: vmrgow 2282; P8BE: sldi r4, r4, 2 2283; P8BE: lwz 2284; P8BE: lwz 2285; P8BE: lwz 2286; P8BE: lwz 2287; P8BE: mtvsrwz 2288; P8BE: mtvsrwz 2289; P8BE: mtvsrwz 2290; P8BE: mtvsrwz 2291; P8BE: xxmrghd 2292; P8BE: xxmrghd 2293; P8BE: vmrgow 2294; P8LE: sldi r4, r4, 2 2295; P8LE: lwz 2296; P8LE: lwz 2297; P8LE: lwz 2298; P8LE: lwz 2299; P8LE: mtvsrwz 2300; P8LE: mtvsrwz 2301; P8LE: mtvsrwz 2302; P8LE: mtvsrwz 2303; P8LE: xxmrghd 2304; P8LE: xxmrghd 2305; P8LE: vmrgow 2306} 2307 2308; Function Attrs: norecurse nounwind readnone 2309define <4 x i32> @spltRegValui(i32 zeroext %val) { 2310entry: 2311 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2312 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2313 ret <4 x i32> %splat.splat 2314; P9BE-LABEL: spltRegValui 2315; P9LE-LABEL: spltRegValui 2316; P8BE-LABEL: spltRegValui 2317; P8LE-LABEL: spltRegValui 2318; P9BE: mtvsrws v2, r3 2319; P9BE: blr 2320; P9LE: mtvsrws v2, r3 2321; P9LE: blr 2322; P8BE: mtvsrwz {{[vsf0-9]+}}, r3 2323; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2324; P8BE: blr 2325; P8LE: mtvsrwz {{[vsf0-9]+}}, r3 2326; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2327; P8LE: blr 2328} 2329 2330; Function Attrs: norecurse nounwind readonly 2331define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2332entry: 2333 %0 = load i32, i32* %ptr, align 4 2334 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2335 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2336 ret <4 x i32> %splat.splat 2337; P9BE-LABEL: spltMemValui 2338; P9LE-LABEL: spltMemValui 2339; P8BE-LABEL: spltMemValui 2340; P8LE-LABEL: spltMemValui 2341; P9BE: lxvwsx v2, 0, r3 2342; P9BE: blr 2343; P9LE: lxvwsx v2, 0, r3 2344; P9LE: blr 2345; P8BE: lxsiwax {{[vsf0-9]+}}, 0, r3 2346; P8BE: xxspltw v2, {{[vsf0-9]+}}, 1 2347; P8BE: blr 2348; P8LE: lxsiwax {{[vsf0-9]+}}, 0, r3 2349; P8LE: xxspltw v2, {{[vsf0-9]+}}, 1 2350; P8LE: blr 2351} 2352 2353; Function Attrs: norecurse nounwind readnone 2354define <4 x i32> @spltCnstConvftoui() { 2355entry: 2356 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2357; P9BE-LABEL: spltCnstConvftoui 2358; P9LE-LABEL: spltCnstConvftoui 2359; P8BE-LABEL: spltCnstConvftoui 2360; P8LE-LABEL: spltCnstConvftoui 2361; P9BE: vspltisw v2, 4 2362; P9BE: blr 2363; P9LE: vspltisw v2, 4 2364; P9LE: blr 2365; P8BE: vspltisw v2, 4 2366; P8BE: blr 2367; P8LE: vspltisw v2, 4 2368; P8LE: blr 2369} 2370 2371; Function Attrs: norecurse nounwind readnone 2372define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2373entry: 2374 %conv = fptoui float %a to i32 2375 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2376 %conv1 = fptoui float %b to i32 2377 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2378 %conv3 = fptoui float %c to i32 2379 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2380 %conv5 = fptoui float %d to i32 2381 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2382 ret <4 x i32> %vecinit6 2383; P9BE-LABEL: fromRegsConvftoui 2384; P9LE-LABEL: fromRegsConvftoui 2385; P8BE-LABEL: fromRegsConvftoui 2386; P8LE-LABEL: fromRegsConvftoui 2387; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2388; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2389; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2390; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2391; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2392; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2393; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2394; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2395; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2396; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2397; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2398; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2399; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2400; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2401; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2402; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2403; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2404; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2405; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2406; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2407} 2408 2409; Function Attrs: norecurse nounwind readnone 2410define <4 x i32> @fromDiffConstsConvftoui() { 2411entry: 2412 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2413; P9BE-LABEL: fromDiffConstsConvftoui 2414; P9LE-LABEL: fromDiffConstsConvftoui 2415; P8BE-LABEL: fromDiffConstsConvftoui 2416; P8LE-LABEL: fromDiffConstsConvftoui 2417; P9BE: lxv 2418; P9BE: blr 2419; P9LE: lxv 2420; P9LE: blr 2421; P8BE: lxvw4x 2422; P8BE: blr 2423; P8LE: lvx 2424; P8LE-NOT: xxswapd 2425; P8LE: blr 2426} 2427 2428; Function Attrs: norecurse nounwind readonly 2429define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2430entry: 2431 %0 = bitcast float* %ptr to <4 x float>* 2432 %1 = load <4 x float>, <4 x float>* %0, align 4 2433 %2 = fptoui <4 x float> %1 to <4 x i32> 2434 ret <4 x i32> %2 2435; P9BE-LABEL: fromDiffMemConsAConvftoui 2436; P9LE-LABEL: fromDiffMemConsAConvftoui 2437; P8BE-LABEL: fromDiffMemConsAConvftoui 2438; P8LE-LABEL: fromDiffMemConsAConvftoui 2439; P9BE: lxv [[REG1:[vs0-9]+]], 0(r3) 2440; P9BE: xvcvspuxws v2, [[REG1]] 2441; P9BE: blr 2442; P9LE: lxv [[REG1:[vs0-9]+]], 0(r3) 2443; P9LE: xvcvspuxws v2, [[REG1]] 2444; P9LE: blr 2445; P8BE: lxvw4x [[REG1:[vs0-9]+]], 0, r3 2446; P8BE: xvcvspuxws v2, [[REG1]] 2447; P8BE: blr 2448; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2449; P8LE: xxswapd v2, [[REG1]] 2450; P8LE: xvcvspuxws v2, v2 2451; P8LE: blr 2452} 2453 2454; Function Attrs: norecurse nounwind readonly 2455define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2456entry: 2457 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 2458 %0 = load float, float* %arrayidx, align 4 2459 %conv = fptoui float %0 to i32 2460 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2461 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 2462 %1 = load float, float* %arrayidx1, align 4 2463 %conv2 = fptoui float %1 to i32 2464 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2465 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 2466 %2 = load float, float* %arrayidx4, align 4 2467 %conv5 = fptoui float %2 to i32 2468 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2469 %3 = load float, float* %ptr, align 4 2470 %conv8 = fptoui float %3 to i32 2471 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2472 ret <4 x i32> %vecinit9 2473; P9BE-LABEL: fromDiffMemConsDConvftoui 2474; P9LE-LABEL: fromDiffMemConsDConvftoui 2475; P8BE-LABEL: fromDiffMemConsDConvftoui 2476; P8LE-LABEL: fromDiffMemConsDConvftoui 2477; P9BE: lxv 2478; P9BE: lxv 2479; P9BE: vperm 2480; P9BE: xvcvspuxws 2481; P9BE: blr 2482; P9LE: lxv 2483; P9LE: lxv 2484; P9LE: vperm 2485; P9LE: xvcvspuxws 2486; P9LE: blr 2487; P8BE: lxvw4x 2488; P8BE: lxvw4x 2489; P8BE: vperm 2490; P8BE: xvcvspuxws 2491; P8BE: blr 2492; P8LE-DAG: lxvd2x 2493; P8LE-DAG: lvx 2494; P8LE: xxswapd 2495; P8LE: vperm 2496; P8LE: xvcvspuxws 2497; P8LE: blr 2498} 2499 2500; Function Attrs: norecurse nounwind readonly 2501define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2502entry: 2503 %idxprom = sext i32 %elem to i64 2504 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2505 %0 = load float, float* %arrayidx, align 4 2506 %conv = fptoui float %0 to i32 2507 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2508 %add = add nsw i32 %elem, 1 2509 %idxprom1 = sext i32 %add to i64 2510 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2511 %1 = load float, float* %arrayidx2, align 4 2512 %conv3 = fptoui float %1 to i32 2513 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2514 %add5 = add nsw i32 %elem, 2 2515 %idxprom6 = sext i32 %add5 to i64 2516 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2517 %2 = load float, float* %arrayidx7, align 4 2518 %conv8 = fptoui float %2 to i32 2519 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2520 %add10 = add nsw i32 %elem, 3 2521 %idxprom11 = sext i32 %add10 to i64 2522 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2523 %3 = load float, float* %arrayidx12, align 4 2524 %conv13 = fptoui float %3 to i32 2525 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2526 ret <4 x i32> %vecinit14 2527; P9BE-LABEL: fromDiffMemVarAConvftoui 2528; P9LE-LABEL: fromDiffMemVarAConvftoui 2529; P8BE-LABEL: fromDiffMemVarAConvftoui 2530; P8LE-LABEL: fromDiffMemVarAConvftoui 2531; FIXME: implement finding consecutive loads with pre-inc 2532; P9BE: lfsux 2533; P9LE: lfsux 2534; P8BE: lfsux 2535; P8LE: lfsux 2536} 2537 2538; Function Attrs: norecurse nounwind readonly 2539define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 2540entry: 2541 %idxprom = sext i32 %elem to i64 2542 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 2543 %0 = load float, float* %arrayidx, align 4 2544 %conv = fptoui float %0 to i32 2545 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2546 %sub = add nsw i32 %elem, -1 2547 %idxprom1 = sext i32 %sub to i64 2548 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 2549 %1 = load float, float* %arrayidx2, align 4 2550 %conv3 = fptoui float %1 to i32 2551 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2552 %sub5 = add nsw i32 %elem, -2 2553 %idxprom6 = sext i32 %sub5 to i64 2554 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 2555 %2 = load float, float* %arrayidx7, align 4 2556 %conv8 = fptoui float %2 to i32 2557 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2558 %sub10 = add nsw i32 %elem, -3 2559 %idxprom11 = sext i32 %sub10 to i64 2560 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 2561 %3 = load float, float* %arrayidx12, align 4 2562 %conv13 = fptoui float %3 to i32 2563 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2564 ret <4 x i32> %vecinit14 2565; P9BE-LABEL: fromDiffMemVarDConvftoui 2566; P9LE-LABEL: fromDiffMemVarDConvftoui 2567; P8BE-LABEL: fromDiffMemVarDConvftoui 2568; P8LE-LABEL: fromDiffMemVarDConvftoui 2569; FIXME: implement finding consecutive loads with pre-inc 2570; P9BE: lfsux 2571; P9LE: lfsux 2572; P8BE: lfsux 2573; P8LE: lfsux 2574} 2575 2576; Function Attrs: norecurse nounwind readnone 2577define <4 x i32> @spltRegValConvftoui(float %val) { 2578entry: 2579 %conv = fptoui float %val to i32 2580 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2581 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2582 ret <4 x i32> %splat.splat 2583; P9BE-LABEL: spltRegValConvftoui 2584; P9LE-LABEL: spltRegValConvftoui 2585; P8BE-LABEL: spltRegValConvftoui 2586; P8LE-LABEL: spltRegValConvftoui 2587; P9BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2588; P9BE: xxspltw v2, vs[[REG1]], 1 2589; P9BE: blr 2590; P9LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2591; P9LE: xxspltw v2, vs[[REG1]], 1 2592; P9LE: blr 2593; P8BE: xscvdpuxws f[[REG1:[0-9]+]], f1 2594; P8BE: xxspltw v2, vs[[REG1]], 1 2595; P8BE: blr 2596; P8LE: xscvdpuxws f[[REG1:[0-9]+]], f1 2597; P8LE: xxspltw v2, vs[[REG1]], 1 2598; P8LE: blr 2599} 2600 2601; Function Attrs: norecurse nounwind readonly 2602define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 2603entry: 2604 %0 = load float, float* %ptr, align 4 2605 %conv = fptoui float %0 to i32 2606 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2607 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2608 ret <4 x i32> %splat.splat 2609; P9BE-LABEL: spltMemValConvftoui 2610; P9LE-LABEL: spltMemValConvftoui 2611; P8BE-LABEL: spltMemValConvftoui 2612; P8LE-LABEL: spltMemValConvftoui 2613; P9BE: lxvwsx [[REG1:[vs0-9]+]], 0, r3 2614; P9BE: xvcvspuxws v2, [[REG1]] 2615; P9LE: [[REG1:[vs0-9]+]], 0, r3 2616; P9LE: xvcvspuxws v2, [[REG1]] 2617; P8BE: lfsx [[REG1:f[0-9]+]], 0, r3 2618; P8BE: xscvdpuxws f[[REG2:[0-9]+]], [[REG1]] 2619; P8BE: xxspltw v2, vs[[REG2]], 1 2620; P8LE: lfsx [[REG1:f[0-9]+]], 0, r3 2621; P8LE: xscvdpuxws f[[REG2:[vs0-9]+]], [[REG1]] 2622; P8LE: xxspltw v2, vs[[REG2]], 1 2623} 2624 2625; Function Attrs: norecurse nounwind readnone 2626define <4 x i32> @spltCnstConvdtoui() { 2627entry: 2628 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2629; P9BE-LABEL: spltCnstConvdtoui 2630; P9LE-LABEL: spltCnstConvdtoui 2631; P8BE-LABEL: spltCnstConvdtoui 2632; P8LE-LABEL: spltCnstConvdtoui 2633; P9BE: vspltisw v2, 4 2634; P9BE: blr 2635; P9LE: vspltisw v2, 4 2636; P9LE: blr 2637; P8BE: vspltisw v2, 4 2638; P8BE: blr 2639; P8LE: vspltisw v2, 4 2640; P8LE: blr 2641} 2642 2643; Function Attrs: norecurse nounwind readnone 2644define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 2645entry: 2646 %conv = fptoui double %a to i32 2647 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2648 %conv1 = fptoui double %b to i32 2649 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2650 %conv3 = fptoui double %c to i32 2651 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2652 %conv5 = fptoui double %d to i32 2653 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2654 ret <4 x i32> %vecinit6 2655; P9BE-LABEL: fromRegsConvdtoui 2656; P9LE-LABEL: fromRegsConvdtoui 2657; P8BE-LABEL: fromRegsConvdtoui 2658; P8LE-LABEL: fromRegsConvdtoui 2659; P9BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2660; P9BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2661; P9BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2662; P9BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2663; P9BE: vmrgew v2, [[REG3]], [[REG4]] 2664; P9LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2665; P9LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2666; P9LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2667; P9LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2668; P9LE: vmrgew v2, [[REG4]], [[REG3]] 2669; P8BE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs1, vs3 2670; P8BE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs2, vs4 2671; P8BE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2672; P8BE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2673; P8BE: vmrgew v2, [[REG3]], [[REG4]] 2674; P8LE-DAG: xxmrghd {{[vs]+}}[[REG1:[0-9]+]], vs3, vs1 2675; P8LE-DAG: xxmrghd {{[vs]+}}[[REG2:[0-9]+]], vs4, vs2 2676; P8LE-DAG: xvcvdpuxws [[REG3:v[0-9]+]], {{[vs]+}}[[REG1]] 2677; P8LE-DAG: xvcvdpuxws [[REG4:v[0-9]+]], {{[vs]+}}[[REG2]] 2678; P8LE: vmrgew v2, [[REG4]], [[REG3]] 2679} 2680 2681; Function Attrs: norecurse nounwind readnone 2682define <4 x i32> @fromDiffConstsConvdtoui() { 2683entry: 2684 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2685; P9BE-LABEL: fromDiffConstsConvdtoui 2686; P9LE-LABEL: fromDiffConstsConvdtoui 2687; P8BE-LABEL: fromDiffConstsConvdtoui 2688; P8LE-LABEL: fromDiffConstsConvdtoui 2689; P9BE: lxv 2690; P9BE: blr 2691; P9LE: lxv 2692; P9LE: blr 2693; P8BE: lxvw4x 2694; P8BE: blr 2695; P8LE: lvx 2696; P8LE-NOT: xxswapd 2697; P8LE: blr 2698} 2699 2700; Function Attrs: norecurse nounwind readonly 2701define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 2702entry: 2703 %0 = bitcast double* %ptr to <2 x double>* 2704 %1 = load <2 x double>, <2 x double>* %0, align 8 2705 %2 = fptoui <2 x double> %1 to <2 x i32> 2706 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 2707 %3 = bitcast double* %arrayidx4 to <2 x double>* 2708 %4 = load <2 x double>, <2 x double>* %3, align 8 2709 %5 = fptoui <2 x double> %4 to <2 x i32> 2710 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 2711 ret <4 x i32> %vecinit9 2712; P9BE-LABEL: fromDiffMemConsAConvdtoui 2713; P9LE-LABEL: fromDiffMemConsAConvdtoui 2714; P8BE-LABEL: fromDiffMemConsAConvdtoui 2715; P8LE-LABEL: fromDiffMemConsAConvdtoui 2716; P9BE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 2717; P9BE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 2718; P9BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2719; P9BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2720; P9BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2721; P9BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2722; P9BE: vmrgew v2, [[REG6]], [[REG5]] 2723; P9LE-DAG: lxv [[REG1:[vs0-9]+]], 0(r3) 2724; P9LE-DAG: lxv [[REG2:[vs0-9]+]], 16(r3) 2725; P9LE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG2]], [[REG1]] 2726; P9LE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG2]], [[REG1]] 2727; P9LE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2728; P9LE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2729; P9LE: vmrgew v2, [[REG6]], [[REG5]] 2730; P8BE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2731; P8BE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2732; P8BE-DAG: xxmrgld [[REG3:[vs0-9]+]], [[REG1]], [[REG2]] 2733; P8BE-DAG: xxmrghd [[REG4:[vs0-9]+]], [[REG1]], [[REG2]] 2734; P8BE-DAG: xvcvdpuxws [[REG5:[vs0-9]+]], [[REG3]] 2735; P8BE-DAG: xvcvdpuxws [[REG6:[vs0-9]+]], [[REG4]] 2736; P8BE: vmrgew v2, [[REG6]], [[REG5]] 2737; P8LE: lxvd2x [[REG1:[vs0-9]+]], 0, r3 2738; P8LE: lxvd2x [[REG2:[vs0-9]+]], r3, r4 2739; P8LE-DAG: xxswapd [[REG3:[vs0-9]+]], [[REG1]] 2740; P8LE-DAG: xxswapd [[REG4:[vs0-9]+]], [[REG2]] 2741; P8LE-DAG: xxmrgld [[REG5:[vs0-9]+]], [[REG4]], [[REG3]] 2742; P8LE-DAG: xxmrghd [[REG6:[vs0-9]+]], [[REG4]], [[REG3]] 2743; P8LE-DAG: xvcvdpuxws [[REG7:[vs0-9]+]], [[REG5]] 2744; P8LE-DAG: xvcvdpuxws [[REG8:[vs0-9]+]], [[REG6]] 2745; P8LE: vmrgew v2, [[REG8]], [[REG7]] 2746} 2747 2748; Function Attrs: norecurse nounwind readonly 2749define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 2750entry: 2751 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2752 %0 = load double, double* %arrayidx, align 8 2753 %conv = fptoui double %0 to i32 2754 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2755 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2756 %1 = load double, double* %arrayidx1, align 8 2757 %conv2 = fptoui double %1 to i32 2758 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2759 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2760 %2 = load double, double* %arrayidx4, align 8 2761 %conv5 = fptoui double %2 to i32 2762 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2763 %3 = load double, double* %ptr, align 8 2764 %conv8 = fptoui double %3 to i32 2765 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2766 ret <4 x i32> %vecinit9 2767; P9BE-LABEL: fromDiffMemConsDConvdtoui 2768; P9LE-LABEL: fromDiffMemConsDConvdtoui 2769; P8BE-LABEL: fromDiffMemConsDConvdtoui 2770; P8LE-LABEL: fromDiffMemConsDConvdtoui 2771; P9BE: lfd 2772; P9BE: lfd 2773; P9BE: lfd 2774; P9BE: lfd 2775; P9BE: xxmrghd 2776; P9BE: xxmrghd 2777; P9BE: xvcvdpuxws 2778; P9BE: xvcvdpuxws 2779; P9BE: vmrgew v2 2780; P9LE: lfd 2781; P9LE: lfd 2782; P9LE: lfd 2783; P9LE: lfd 2784; P9LE: xxmrghd 2785; P9LE: xxmrghd 2786; P9LE: xvcvdpuxws 2787; P9LE: xvcvdpuxws 2788; P9LE: vmrgew v2 2789; P8BE: lfdx 2790; P8BE: lfd 2791; P8BE: lfd 2792; P8BE: lfd 2793; P8BE: xxmrghd 2794; P8BE: xxmrghd 2795; P8BE: xvcvdpuxws 2796; P8BE: xvcvdpuxws 2797; P8BE: vmrgew v2 2798; P8LE: lfdx 2799; P8LE: lfd 2800; P8LE: lfd 2801; P8LE: lfd 2802; P8LE: xxmrghd 2803; P8LE: xxmrghd 2804; P8LE: xvcvdpuxws 2805; P8LE: xvcvdpuxws 2806; P8LE: vmrgew v2 2807} 2808 2809; Function Attrs: norecurse nounwind readonly 2810define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2811entry: 2812 %idxprom = sext i32 %elem to i64 2813 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2814 %0 = load double, double* %arrayidx, align 8 2815 %conv = fptoui double %0 to i32 2816 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2817 %add = add nsw i32 %elem, 1 2818 %idxprom1 = sext i32 %add to i64 2819 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2820 %1 = load double, double* %arrayidx2, align 8 2821 %conv3 = fptoui double %1 to i32 2822 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2823 %add5 = add nsw i32 %elem, 2 2824 %idxprom6 = sext i32 %add5 to i64 2825 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2826 %2 = load double, double* %arrayidx7, align 8 2827 %conv8 = fptoui double %2 to i32 2828 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2829 %add10 = add nsw i32 %elem, 3 2830 %idxprom11 = sext i32 %add10 to i64 2831 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2832 %3 = load double, double* %arrayidx12, align 8 2833 %conv13 = fptoui double %3 to i32 2834 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2835 ret <4 x i32> %vecinit14 2836; P9BE-LABEL: fromDiffMemVarAConvdtoui 2837; P9LE-LABEL: fromDiffMemVarAConvdtoui 2838; P8BE-LABEL: fromDiffMemVarAConvdtoui 2839; P8LE-LABEL: fromDiffMemVarAConvdtoui 2840; P9BE: lfdux 2841; P9BE: lfd 2842; P9BE: lfd 2843; P9BE: lfd 2844; P9BE: xxmrghd 2845; P9BE: xxmrghd 2846; P9BE: xvcvdpuxws 2847; P9BE: xvcvdpuxws 2848; P9BE: vmrgew v2 2849; P9LE: lfdux 2850; P9LE: lfd 2851; P9LE: lfd 2852; P9LE: lfd 2853; P9LE: xxmrghd 2854; P9LE: xxmrghd 2855; P9LE: xvcvdpuxws 2856; P9LE: xvcvdpuxws 2857; P9LE: vmrgew v2 2858; P8BE: lfdux 2859; P8BE: lfd 2860; P8BE: lfd 2861; P8BE: lfd 2862; P8BE: xxmrghd 2863; P8BE: xxmrghd 2864; P8BE: xvcvdpuxws 2865; P8BE: xvcvdpuxws 2866; P8BE: vmrgew v2 2867; P8LE: lfdux 2868; P8LE: lfd 2869; P8LE: lfd 2870; P8LE: lfd 2871; P8LE: xxmrghd 2872; P8LE: xxmrghd 2873; P8LE: xvcvdpuxws 2874; P8LE: xvcvdpuxws 2875; P8LE: vmrgew v2 2876} 2877 2878; Function Attrs: norecurse nounwind readonly 2879define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 2880entry: 2881 %idxprom = sext i32 %elem to i64 2882 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2883 %0 = load double, double* %arrayidx, align 8 2884 %conv = fptoui double %0 to i32 2885 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2886 %sub = add nsw i32 %elem, -1 2887 %idxprom1 = sext i32 %sub to i64 2888 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2889 %1 = load double, double* %arrayidx2, align 8 2890 %conv3 = fptoui double %1 to i32 2891 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2892 %sub5 = add nsw i32 %elem, -2 2893 %idxprom6 = sext i32 %sub5 to i64 2894 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2895 %2 = load double, double* %arrayidx7, align 8 2896 %conv8 = fptoui double %2 to i32 2897 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2898 %sub10 = add nsw i32 %elem, -3 2899 %idxprom11 = sext i32 %sub10 to i64 2900 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2901 %3 = load double, double* %arrayidx12, align 8 2902 %conv13 = fptoui double %3 to i32 2903 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2904 ret <4 x i32> %vecinit14 2905; P9BE-LABEL: fromDiffMemVarDConvdtoui 2906; P9LE-LABEL: fromDiffMemVarDConvdtoui 2907; P8BE-LABEL: fromDiffMemVarDConvdtoui 2908; P8LE-LABEL: fromDiffMemVarDConvdtoui 2909; P9BE: lfdux 2910; P9BE: lfd 2911; P9BE: lfd 2912; P9BE: lfd 2913; P9BE: xxmrghd 2914; P9BE: xxmrghd 2915; P9BE: xvcvdpuxws 2916; P9BE: xvcvdpuxws 2917; P9BE: vmrgew v2 2918; P9LE: lfdux 2919; P9LE: lfd 2920; P9LE: lfd 2921; P9LE: lfd 2922; P9LE: xxmrghd 2923; P9LE: xxmrghd 2924; P9LE: xvcvdpuxws 2925; P9LE: xvcvdpuxws 2926; P9LE: vmrgew v2 2927; P8BE: lfdux 2928; P8BE: lfd 2929; P8BE: lfd 2930; P8BE: lfd 2931; P8BE: xxmrghd 2932; P8BE: xxmrghd 2933; P8BE: xvcvdpuxws 2934; P8BE: xvcvdpuxws 2935; P8BE: vmrgew v2 2936; P8LE: lfdux 2937; P8LE: lfd 2938; P8LE: lfd 2939; P8LE: lfd 2940; P8LE: xxmrghd 2941; P8LE: xxmrghd 2942; P8LE: xvcvdpuxws 2943; P8LE: xvcvdpuxws 2944; P8LE: vmrgew v2 2945} 2946 2947; Function Attrs: norecurse nounwind readnone 2948define <4 x i32> @spltRegValConvdtoui(double %val) { 2949entry: 2950 %conv = fptoui double %val to i32 2951 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2952 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2953 ret <4 x i32> %splat.splat 2954; P9BE-LABEL: spltRegValConvdtoui 2955; P9LE-LABEL: spltRegValConvdtoui 2956; P8BE-LABEL: spltRegValConvdtoui 2957; P8LE-LABEL: spltRegValConvdtoui 2958; P9BE: xscvdpuxws 2959; P9BE: xxspltw 2960; P9BE: blr 2961; P9LE: xscvdpuxws 2962; P9LE: xxspltw 2963; P9LE: blr 2964; P8BE: xscvdpuxws 2965; P8BE: xxspltw 2966; P8BE: blr 2967; P8LE: xscvdpuxws 2968; P8LE: xxspltw 2969; P8LE: blr 2970} 2971 2972; Function Attrs: norecurse nounwind readonly 2973define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 2974entry: 2975 %0 = load double, double* %ptr, align 8 2976 %conv = fptoui double %0 to i32 2977 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2978 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2979 ret <4 x i32> %splat.splat 2980; P9BE-LABEL: spltMemValConvdtoui 2981; P9LE-LABEL: spltMemValConvdtoui 2982; P8BE-LABEL: spltMemValConvdtoui 2983; P8LE-LABEL: spltMemValConvdtoui 2984; P9BE: lfd 2985; P9BE: xscvdpuxws 2986; P9BE: xxspltw 2987; P9BE: blr 2988; P9LE: lfd 2989; P9LE: xscvdpuxws 2990; P9LE: xxspltw 2991; P9LE: blr 2992; P8BE: lfdx 2993; P8BE: xscvdpuxws 2994; P8BE: xxspltw 2995; P8BE: blr 2996; P8LE: lfdx 2997; P8LE: xscvdpuxws 2998; P8LE: xxspltw 2999; P8LE: blr 3000} 3001; Function Attrs: norecurse nounwind readnone 3002define <2 x i64> @allZeroll() { 3003entry: 3004 ret <2 x i64> zeroinitializer 3005; P9BE-LABEL: allZeroll 3006; P9LE-LABEL: allZeroll 3007; P8BE-LABEL: allZeroll 3008; P8LE-LABEL: allZeroll 3009; P9BE: xxlxor v2, v2, v2 3010; P9BE: blr 3011; P9LE: xxlxor v2, v2, v2 3012; P9LE: blr 3013; P8BE: xxlxor v2, v2, v2 3014; P8BE: blr 3015; P8LE: xxlxor v2, v2, v2 3016; P8LE: blr 3017} 3018 3019; Function Attrs: norecurse nounwind readnone 3020define <2 x i64> @allOnell() { 3021entry: 3022 ret <2 x i64> <i64 -1, i64 -1> 3023; P9BE-LABEL: allOnell 3024; P9LE-LABEL: allOnell 3025; P8BE-LABEL: allOnell 3026; P8LE-LABEL: allOnell 3027; P9BE: xxspltib v2, 255 3028; P9BE: blr 3029; P9LE: xxspltib v2, 255 3030; P9LE: blr 3031; P8BE: vspltisb v2, -1 3032; P8BE: blr 3033; P8LE: vspltisb v2, -1 3034; P8LE: blr 3035} 3036 3037; Function Attrs: norecurse nounwind readnone 3038define <2 x i64> @spltConst1ll() { 3039entry: 3040 ret <2 x i64> <i64 1, i64 1> 3041; P9BE-LABEL: spltConst1ll 3042; P9LE-LABEL: spltConst1ll 3043; P8BE-LABEL: spltConst1ll 3044; P8LE-LABEL: spltConst1ll 3045; P9BE: lxv 3046; P9BE: blr 3047; P9LE: lxv 3048; P9LE: blr 3049; P8BE: lxvd2x 3050; P8BE: blr 3051; P8LE: lxvd2x 3052; P8LE: blr 3053} 3054 3055; Function Attrs: norecurse nounwind readnone 3056define <2 x i64> @spltConst16kll() { 3057entry: 3058 ret <2 x i64> <i64 32767, i64 32767> 3059; P9BE-LABEL: spltConst16kll 3060; P9LE-LABEL: spltConst16kll 3061; P8BE-LABEL: spltConst16kll 3062; P8LE-LABEL: spltConst16kll 3063; P9BE: lxv 3064; P9BE: blr 3065; P9LE: lxv 3066; P9LE: blr 3067; P8BE: lxvd2x 3068; P8BE: blr 3069; P8LE: lxvd2x 3070; P8LE: blr 3071} 3072 3073; Function Attrs: norecurse nounwind readnone 3074define <2 x i64> @spltConst32kll() { 3075entry: 3076 ret <2 x i64> <i64 65535, i64 65535> 3077; P9BE-LABEL: spltConst32kll 3078; P9LE-LABEL: spltConst32kll 3079; P8BE-LABEL: spltConst32kll 3080; P8LE-LABEL: spltConst32kll 3081; P9BE: lxv 3082; P9BE: blr 3083; P9LE: lxv 3084; P9LE: blr 3085; P8BE: lxvd2x 3086; P8BE: blr 3087; P8LE: lxvd2x 3088; P8LE: blr 3089} 3090 3091; Function Attrs: norecurse nounwind readnone 3092define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3093entry: 3094 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3095 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3096 ret <2 x i64> %vecinit1 3097; P9BE-LABEL: fromRegsll 3098; P9LE-LABEL: fromRegsll 3099; P8BE-LABEL: fromRegsll 3100; P8LE-LABEL: fromRegsll 3101; P9BE: mtvsrdd v2, r3, r4 3102; P9BE: blr 3103; P9LE: mtvsrdd v2, r4, r3 3104; P9LE: blr 3105; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3106; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3107; P8BE: xxmrghd v2 3108; P8BE: blr 3109; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 3110; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 3111; P8LE: xxmrghd v2 3112; P8LE: blr 3113} 3114 3115; Function Attrs: norecurse nounwind readnone 3116define <2 x i64> @fromDiffConstsll() { 3117entry: 3118 ret <2 x i64> <i64 242, i64 -113> 3119; P9BE-LABEL: fromDiffConstsll 3120; P9LE-LABEL: fromDiffConstsll 3121; P8BE-LABEL: fromDiffConstsll 3122; P8LE-LABEL: fromDiffConstsll 3123; P9BE: lxv 3124; P9BE: blr 3125; P9LE: lxv 3126; P9LE: blr 3127; P8BE: lxvd2x 3128; P8BE: blr 3129; P8LE: lxvd2x 3130; P8LE: blr 3131} 3132 3133; Function Attrs: norecurse nounwind readonly 3134define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3135entry: 3136 %0 = load i64, i64* %arr, align 8 3137 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3138 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3139 %1 = load i64, i64* %arrayidx1, align 8 3140 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3141 ret <2 x i64> %vecinit2 3142; P9BE-LABEL: fromDiffMemConsAll 3143; P9LE-LABEL: fromDiffMemConsAll 3144; P8BE-LABEL: fromDiffMemConsAll 3145; P8LE-LABEL: fromDiffMemConsAll 3146; P9BE: lxv v2 3147; P9BE: blr 3148; P9LE: lxv v2 3149; P9LE: blr 3150; P8BE: lxvd2x v2 3151; P8BE: blr 3152; P8LE: lxvd2x 3153; P8LE: xxswapd v2 3154; P8LE: blr 3155} 3156 3157; Function Attrs: norecurse nounwind readonly 3158define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3159entry: 3160 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3161 %0 = load i64, i64* %arrayidx, align 8 3162 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3163 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3164 %1 = load i64, i64* %arrayidx1, align 8 3165 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3166 ret <2 x i64> %vecinit2 3167; P9BE-LABEL: fromDiffMemConsDll 3168; P9LE-LABEL: fromDiffMemConsDll 3169; P8BE-LABEL: fromDiffMemConsDll 3170; P8LE-LABEL: fromDiffMemConsDll 3171; P9BE: lxv v2 3172; P9BE: blr 3173; P9LE: lxv 3174; P9LE: xxswapd v2 3175; P9LE: blr 3176; P8BE: lxvd2x 3177; P8BE: xxswapd v2 3178; P8BE-NEXT: blr 3179; P8LE: lxvd2x v2 3180; P8LE-NEXT: blr 3181} 3182 3183; Function Attrs: norecurse nounwind readonly 3184define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 3185entry: 3186 %idxprom = sext i32 %elem to i64 3187 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3188 %0 = load i64, i64* %arrayidx, align 8 3189 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3190 %add = add nsw i32 %elem, 1 3191 %idxprom1 = sext i32 %add to i64 3192 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3193 %1 = load i64, i64* %arrayidx2, align 8 3194 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3195 ret <2 x i64> %vecinit3 3196; P9BE-LABEL: fromDiffMemVarAll 3197; P9LE-LABEL: fromDiffMemVarAll 3198; P8BE-LABEL: fromDiffMemVarAll 3199; P8LE-LABEL: fromDiffMemVarAll 3200; P9BE: sldi 3201; P9BE: lxvx v2 3202; P9BE-NEXT: blr 3203; P9LE: sldi 3204; P9LE: lxvx v2 3205; P9LE-NEXT: blr 3206; P8BE: sldi 3207; P8BE: lxvd2x v2 3208; P8BE-NEXT: blr 3209; P8LE: sldi 3210; P8LE: lxvd2x 3211; P8LE: xxswapd v2 3212; P8LE-NEXT: blr 3213} 3214 3215; Function Attrs: norecurse nounwind readonly 3216define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 3217entry: 3218 %idxprom = sext i32 %elem to i64 3219 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3220 %0 = load i64, i64* %arrayidx, align 8 3221 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3222 %sub = add nsw i32 %elem, -1 3223 %idxprom1 = sext i32 %sub to i64 3224 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 3225 %1 = load i64, i64* %arrayidx2, align 8 3226 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3227 ret <2 x i64> %vecinit3 3228; P9BE-LABEL: fromDiffMemVarDll 3229; P9LE-LABEL: fromDiffMemVarDll 3230; P8BE-LABEL: fromDiffMemVarDll 3231; P8LE-LABEL: fromDiffMemVarDll 3232; P9BE: sldi 3233; P9BE: lxv 3234; P9BE: xxswapd v2 3235; P9BE-NEXT: blr 3236; P9LE: sldi 3237; P9LE: lxv 3238; P9LE: xxswapd v2 3239; P9LE-NEXT: blr 3240; P8BE: sldi 3241; P8BE: lxvd2x 3242; P8BE: xxswapd v2 3243; P8BE-NEXT: blr 3244; P8LE: sldi 3245; P8LE: lxvd2x v2 3246; P8LE-NEXT: blr 3247} 3248 3249; Function Attrs: norecurse nounwind readonly 3250define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 3251entry: 3252 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 3253 %0 = load i64, i64* %arrayidx, align 8 3254 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3255 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 3256 %1 = load i64, i64* %arrayidx1, align 8 3257 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3258 ret <2 x i64> %vecinit2 3259; P9BE-LABEL: fromRandMemConsll 3260; P9LE-LABEL: fromRandMemConsll 3261; P8BE-LABEL: fromRandMemConsll 3262; P8LE-LABEL: fromRandMemConsll 3263; P9BE: ld 3264; P9BE: ld 3265; P9BE: mtvsrdd v2 3266; P9BE-NEXT: blr 3267; P9LE: ld 3268; P9LE: ld 3269; P9LE: mtvsrdd v2 3270; P9LE-NEXT: blr 3271; P8BE: ld 3272; P8BE: ld 3273; P8BE-DAG: mtvsrd 3274; P8BE-DAG: mtvsrd 3275; P8BE: xxmrghd v2 3276; P8BE-NEXT: blr 3277; P8LE: ld 3278; P8LE: ld 3279; P8LE-DAG: mtvsrd 3280; P8LE-DAG: mtvsrd 3281; P8LE: xxmrghd v2 3282; P8LE-NEXT: blr 3283} 3284 3285; Function Attrs: norecurse nounwind readonly 3286define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 3287entry: 3288 %add = add nsw i32 %elem, 4 3289 %idxprom = sext i32 %add to i64 3290 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 3291 %0 = load i64, i64* %arrayidx, align 8 3292 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3293 %add1 = add nsw i32 %elem, 1 3294 %idxprom2 = sext i32 %add1 to i64 3295 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 3296 %1 = load i64, i64* %arrayidx3, align 8 3297 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3298 ret <2 x i64> %vecinit4 3299; P9BE-LABEL: fromRandMemVarll 3300; P9LE-LABEL: fromRandMemVarll 3301; P8BE-LABEL: fromRandMemVarll 3302; P8LE-LABEL: fromRandMemVarll 3303; P9BE: sldi 3304; P9BE: ld 3305; P9BE: ld 3306; P9BE: mtvsrdd v2 3307; P9BE-NEXT: blr 3308; P9LE: sldi 3309; P9LE: ld 3310; P9LE: ld 3311; P9LE: mtvsrdd v2 3312; P9LE-NEXT: blr 3313; P8BE: sldi 3314; P8BE: ld 3315; P8BE: ld 3316; P8BE: mtvsrd 3317; P8BE: mtvsrd 3318; P8BE: xxmrghd v2 3319; P8BE-NEXT: blr 3320; P8LE: sldi 3321; P8LE: ld 3322; P8LE: ld 3323; P8LE: mtvsrd 3324; P8LE: mtvsrd 3325; P8LE: xxmrghd v2 3326; P8LE-NEXT: blr 3327} 3328 3329; Function Attrs: norecurse nounwind readnone 3330define <2 x i64> @spltRegValll(i64 %val) { 3331entry: 3332 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 3333 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3334 ret <2 x i64> %splat.splat 3335; P9BE-LABEL: spltRegValll 3336; P9LE-LABEL: spltRegValll 3337; P8BE-LABEL: spltRegValll 3338; P8LE-LABEL: spltRegValll 3339; P9BE: mtvsrdd v2, r3, r3 3340; P9BE-NEXT: blr 3341; P9LE: mtvsrdd v2, r3, r3 3342; P9LE-NEXT: blr 3343; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3344; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3345; P8BE-NEXT: blr 3346; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 3347; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 3348; P8LE-NEXT: blr 3349} 3350 3351; Function Attrs: norecurse nounwind readonly 3352define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 3353entry: 3354 %0 = load i64, i64* %ptr, align 8 3355 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 3356 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3357 ret <2 x i64> %splat.splat 3358; P9BE-LABEL: spltMemValll 3359; P9LE-LABEL: spltMemValll 3360; P8BE-LABEL: spltMemValll 3361; P8LE-LABEL: spltMemValll 3362; P9BE: lxvdsx v2 3363; P9BE-NEXT: blr 3364; P9LE: lxvdsx v2 3365; P9LE-NEXT: blr 3366; P8BE: lxvdsx v2 3367; P8BE-NEXT: blr 3368; P8LE: lxvdsx v2 3369; P8LE-NEXT: blr 3370} 3371 3372; Function Attrs: norecurse nounwind readnone 3373define <2 x i64> @spltCnstConvftoll() { 3374entry: 3375 ret <2 x i64> <i64 4, i64 4> 3376; P9BE-LABEL: spltCnstConvftoll 3377; P9LE-LABEL: spltCnstConvftoll 3378; P8BE-LABEL: spltCnstConvftoll 3379; P8LE-LABEL: spltCnstConvftoll 3380; P9BE: lxv 3381; P9BE: blr 3382; P9LE: lxv 3383; P9LE: blr 3384; P8BE: lxvd2x 3385; P8BE: blr 3386; P8LE: lxvd2x 3387; P8LE: blr 3388} 3389 3390; Function Attrs: norecurse nounwind readnone 3391define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 3392entry: 3393 %conv = fptosi float %a to i64 3394 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3395 %conv1 = fptosi float %b to i64 3396 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3397 ret <2 x i64> %vecinit2 3398; P9BE-LABEL: fromRegsConvftoll 3399; P9LE-LABEL: fromRegsConvftoll 3400; P8BE-LABEL: fromRegsConvftoll 3401; P8LE-LABEL: fromRegsConvftoll 3402; P9BE: xxmrghd 3403; P9BE: xvcvdpsxds v2 3404; P9BE-NEXT: blr 3405; P9LE: xxmrghd 3406; P9LE: xvcvdpsxds v2 3407; P9LE-NEXT: blr 3408; P8BE: xxmrghd 3409; P8BE: xvcvdpsxds v2 3410; P8BE-NEXT: blr 3411; P8LE: xxmrghd 3412; P8LE: xvcvdpsxds v2 3413; P8LE-NEXT: blr 3414} 3415 3416; Function Attrs: norecurse nounwind readnone 3417define <2 x i64> @fromDiffConstsConvftoll() { 3418entry: 3419 ret <2 x i64> <i64 24, i64 234> 3420; P9BE-LABEL: fromDiffConstsConvftoll 3421; P9LE-LABEL: fromDiffConstsConvftoll 3422; P8BE-LABEL: fromDiffConstsConvftoll 3423; P8LE-LABEL: fromDiffConstsConvftoll 3424; P9BE: lxvx v2 3425; P9BE: blr 3426; P9LE: lxvx v2 3427; P9LE: blr 3428; P8BE: lxvd2x v2 3429; P8BE: blr 3430; P8LE: lxvd2x 3431; P8LE: xxswapd v2 3432; P8LE: blr 3433} 3434 3435; Function Attrs: norecurse nounwind readonly 3436define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 3437entry: 3438 %0 = load float, float* %ptr, align 4 3439 %conv = fptosi float %0 to i64 3440 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3441 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 3442 %1 = load float, float* %arrayidx1, align 4 3443 %conv2 = fptosi float %1 to i64 3444 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3445 ret <2 x i64> %vecinit3 3446; P9BE-LABEL: fromDiffMemConsAConvftoll 3447; P9LE-LABEL: fromDiffMemConsAConvftoll 3448; P8BE-LABEL: fromDiffMemConsAConvftoll 3449; P8LE-LABEL: fromDiffMemConsAConvftoll 3450; P9BE: lfs 3451; P9BE: lfs 3452; P9BE: xxmrghd 3453; P9BE-NEXT: xvcvdpsxds v2 3454; P9BE-NEXT: blr 3455; P9LE: lfs 3456; P9LE: lfs 3457; P9LE: xxmrghd 3458; P9LE-NEXT: xvcvdpsxds v2 3459; P9LE-NEXT: blr 3460; P8BE: lfs 3461; P8BE: lfs 3462; P8BE: xxmrghd 3463; P8BE-NEXT: xvcvdpsxds v2 3464; P8BE-NEXT: blr 3465; P8LE: lfs 3466; P8LE: lfs 3467; P8LE: xxmrghd 3468; P8LE-NEXT: xvcvdpsxds v2 3469; P8LE-NEXT: blr 3470} 3471 3472; Function Attrs: norecurse nounwind readonly 3473define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 3474entry: 3475 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3476 %0 = load float, float* %arrayidx, align 4 3477 %conv = fptosi float %0 to i64 3478 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3479 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3480 %1 = load float, float* %arrayidx1, align 4 3481 %conv2 = fptosi float %1 to i64 3482 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3483 ret <2 x i64> %vecinit3 3484; P9BE-LABEL: fromDiffMemConsDConvftoll 3485; P9LE-LABEL: fromDiffMemConsDConvftoll 3486; P8BE-LABEL: fromDiffMemConsDConvftoll 3487; P8LE-LABEL: fromDiffMemConsDConvftoll 3488; P9BE: lfs 3489; P9BE: lfs 3490; P9BE: xxmrghd 3491; P9BE-NEXT: xvcvdpsxds v2 3492; P9BE-NEXT: blr 3493; P9LE: lfs 3494; P9LE: lfs 3495; P9LE: xxmrghd 3496; P9LE-NEXT: xvcvdpsxds v2 3497; P9LE-NEXT: blr 3498; P8BE: lfs 3499; P8BE: lfs 3500; P8BE: xxmrghd 3501; P8BE-NEXT: xvcvdpsxds v2 3502; P8BE-NEXT: blr 3503; P8LE: lfs 3504; P8LE: lfs 3505; P8LE: xxmrghd 3506; P8LE-NEXT: xvcvdpsxds v2 3507; P8LE-NEXT: blr 3508} 3509 3510; Function Attrs: norecurse nounwind readonly 3511define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3512entry: 3513 %idxprom = sext i32 %elem to i64 3514 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3515 %0 = load float, float* %arrayidx, align 4 3516 %conv = fptosi float %0 to i64 3517 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3518 %add = add nsw i32 %elem, 1 3519 %idxprom1 = sext i32 %add to i64 3520 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3521 %1 = load float, float* %arrayidx2, align 4 3522 %conv3 = fptosi float %1 to i64 3523 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3524 ret <2 x i64> %vecinit4 3525; P9BE-LABEL: fromDiffMemVarAConvftoll 3526; P9LE-LABEL: fromDiffMemVarAConvftoll 3527; P8BE-LABEL: fromDiffMemVarAConvftoll 3528; P8LE-LABEL: fromDiffMemVarAConvftoll 3529; P9BE: sldi 3530; P9BE: lfsux 3531; P9BE: lfs 3532; P9BE: xxmrghd 3533; P9BE-NEXT: xvcvdpsxds v2 3534; P9BE-NEXT: blr 3535; P9LE: sldi 3536; P9LE: lfsux 3537; P9LE: lfs 3538; P9LE: xxmrghd 3539; P9LE-NEXT: xvcvdpsxds v2 3540; P9LE-NEXT: blr 3541; P8BE: sldi 3542; P8BE: lfsux 3543; P8BE: lfs 3544; P8BE: xxmrghd 3545; P8BE-NEXT: xvcvdpsxds v2 3546; P8BE-NEXT: blr 3547; P8LE: sldi 3548; P8LE: lfsux 3549; P8LE: lfs 3550; P8LE: xxmrghd 3551; P8LE-NEXT: xvcvdpsxds v2 3552; P8LE-NEXT: blr 3553} 3554 3555; Function Attrs: norecurse nounwind readonly 3556define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 3557entry: 3558 %idxprom = sext i32 %elem to i64 3559 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3560 %0 = load float, float* %arrayidx, align 4 3561 %conv = fptosi float %0 to i64 3562 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3563 %sub = add nsw i32 %elem, -1 3564 %idxprom1 = sext i32 %sub to i64 3565 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3566 %1 = load float, float* %arrayidx2, align 4 3567 %conv3 = fptosi float %1 to i64 3568 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3569 ret <2 x i64> %vecinit4 3570; P9BE-LABEL: fromDiffMemVarDConvftoll 3571; P9LE-LABEL: fromDiffMemVarDConvftoll 3572; P8BE-LABEL: fromDiffMemVarDConvftoll 3573; P8LE-LABEL: fromDiffMemVarDConvftoll 3574; P9BE: sldi 3575; P9BE: lfsux 3576; P9BE: lfs 3577; P9BE: xxmrghd 3578; P9BE-NEXT: xvcvdpsxds v2 3579; P9BE-NEXT: blr 3580; P9LE: sldi 3581; P9LE: lfsux 3582; P9LE: lfs 3583; P9LE: xxmrghd 3584; P9LE-NEXT: xvcvdpsxds v2 3585; P9LE-NEXT: blr 3586; P8BE: sldi 3587; P8BE: lfsux 3588; P8BE: lfs 3589; P8BE: xxmrghd 3590; P8BE-NEXT: xvcvdpsxds v2 3591; P8BE-NEXT: blr 3592; P8LE: sldi 3593; P8LE: lfsux 3594; P8LE: lfs 3595; P8LE: xxmrghd 3596; P8LE-NEXT: xvcvdpsxds v2 3597; P8LE-NEXT: blr 3598} 3599 3600; Function Attrs: norecurse nounwind readnone 3601define <2 x i64> @spltRegValConvftoll(float %val) { 3602entry: 3603 %conv = fptosi float %val to i64 3604 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3605 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3606 ret <2 x i64> %splat.splat 3607; P9BE-LABEL: spltRegValConvftoll 3608; P9LE-LABEL: spltRegValConvftoll 3609; P8BE-LABEL: spltRegValConvftoll 3610; P8LE-LABEL: spltRegValConvftoll 3611; P9BE: xscvdpsxds 3612; P9BE-NEXT: xxspltd v2 3613; P9BE-NEXT: blr 3614; P9LE: xscvdpsxds 3615; P9LE-NEXT: xxspltd v2 3616; P9LE-NEXT: blr 3617; P8BE: xscvdpsxds 3618; P8BE-NEXT: xxspltd v2 3619; P8BE-NEXT: blr 3620; P8LE: xscvdpsxds 3621; P8LE-NEXT: xxspltd v2 3622; P8LE-NEXT: blr 3623} 3624 3625; Function Attrs: norecurse nounwind readonly 3626define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 3627entry: 3628 %0 = load float, float* %ptr, align 4 3629 %conv = fptosi float %0 to i64 3630 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3631 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3632 ret <2 x i64> %splat.splat 3633; P9BE-LABEL: spltMemValConvftoll 3634; P9LE-LABEL: spltMemValConvftoll 3635; P8BE-LABEL: spltMemValConvftoll 3636; P8LE-LABEL: spltMemValConvftoll 3637; P9BE: lfs 3638; P9BE-NEXT: xscvdpsxds 3639; P9BE-NEXT: xxspltd v2 3640; P9BE-NEXT: blr 3641; P9LE: lfs 3642; P9LE-NEXT: xscvdpsxds 3643; P9LE-NEXT: xxspltd v2 3644; P9LE-NEXT: blr 3645; P8BE: lfs 3646; P8BE-NEXT: xscvdpsxds 3647; P8BE-NEXT: xxspltd v2 3648; P8BE-NEXT: blr 3649; P8LE: lfs 3650; P8LE-NEXT: xscvdpsxds 3651; P8LE-NEXT: xxspltd v2 3652; P8LE-NEXT: blr 3653} 3654 3655; Function Attrs: norecurse nounwind readnone 3656define <2 x i64> @spltCnstConvdtoll() { 3657entry: 3658 ret <2 x i64> <i64 4, i64 4> 3659; P9BE-LABEL: spltCnstConvdtoll 3660; P9LE-LABEL: spltCnstConvdtoll 3661; P8BE-LABEL: spltCnstConvdtoll 3662; P8LE-LABEL: spltCnstConvdtoll 3663; P9BE: lxv 3664; P9BE: blr 3665; P9LE: lxv 3666; P9LE: blr 3667; P8BE: lxvd2x 3668; P8BE: blr 3669; P8LE: lxvd2x 3670; P8LE: blr 3671} 3672 3673; Function Attrs: norecurse nounwind readnone 3674define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 3675entry: 3676 %conv = fptosi double %a to i64 3677 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3678 %conv1 = fptosi double %b to i64 3679 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 3680 ret <2 x i64> %vecinit2 3681; P9BE-LABEL: fromRegsConvdtoll 3682; P9LE-LABEL: fromRegsConvdtoll 3683; P8BE-LABEL: fromRegsConvdtoll 3684; P8LE-LABEL: fromRegsConvdtoll 3685; P9BE: xxmrghd 3686; P9BE-NEXT: xvcvdpsxds 3687; P9BE-NEXT: blr 3688; P9LE: xxmrghd 3689; P9LE-NEXT: xvcvdpsxds 3690; P9LE-NEXT: blr 3691; P8BE: xxmrghd 3692; P8BE-NEXT: xvcvdpsxds 3693; P8BE-NEXT: blr 3694; P8LE: xxmrghd 3695; P8LE-NEXT: xvcvdpsxds 3696; P8LE-NEXT: blr 3697} 3698 3699; Function Attrs: norecurse nounwind readnone 3700define <2 x i64> @fromDiffConstsConvdtoll() { 3701entry: 3702 ret <2 x i64> <i64 24, i64 234> 3703; P9BE-LABEL: fromDiffConstsConvdtoll 3704; P9LE-LABEL: fromDiffConstsConvdtoll 3705; P8BE-LABEL: fromDiffConstsConvdtoll 3706; P8LE-LABEL: fromDiffConstsConvdtoll 3707; P9BE: lxv 3708; P9BE: blr 3709; P9LE: lxv 3710; P9LE: blr 3711; P8BE: lxvd2x 3712; P8BE: blr 3713; P8LE: lxvd2x 3714; P8LE: blr 3715} 3716 3717; Function Attrs: norecurse nounwind readonly 3718define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 3719entry: 3720 %0 = bitcast double* %ptr to <2 x double>* 3721 %1 = load <2 x double>, <2 x double>* %0, align 8 3722 %2 = fptosi <2 x double> %1 to <2 x i64> 3723 ret <2 x i64> %2 3724; P9BE-LABEL: fromDiffMemConsAConvdtoll 3725; P9LE-LABEL: fromDiffMemConsAConvdtoll 3726; P8BE-LABEL: fromDiffMemConsAConvdtoll 3727; P8LE-LABEL: fromDiffMemConsAConvdtoll 3728; P9BE: lxv 3729; P9BE-NEXT: xvcvdpsxds v2 3730; P9BE-NEXT: blr 3731; P9LE: lxv 3732; P9LE-NEXT: xvcvdpsxds v2 3733; P9LE-NEXT: blr 3734; P8BE: lxvd2x 3735; P8BE-NEXT: xvcvdpsxds v2 3736; P8BE-NEXT: blr 3737; P8LE: lxvd2x 3738; P8LE: xxswapd 3739; P8LE-NEXT: xvcvdpsxds v2 3740; P8LE-NEXT: blr 3741} 3742 3743; Function Attrs: norecurse nounwind readonly 3744define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 3745entry: 3746 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3747 %0 = load double, double* %arrayidx, align 8 3748 %conv = fptosi double %0 to i64 3749 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3750 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3751 %1 = load double, double* %arrayidx1, align 8 3752 %conv2 = fptosi double %1 to i64 3753 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 3754 ret <2 x i64> %vecinit3 3755; P9BE-LABEL: fromDiffMemConsDConvdtoll 3756; P9LE-LABEL: fromDiffMemConsDConvdtoll 3757; P8BE-LABEL: fromDiffMemConsDConvdtoll 3758; P8LE-LABEL: fromDiffMemConsDConvdtoll 3759; P9BE: lxv 3760; P9BE-NEXT: xxswapd 3761; P9BE-NEXT: xvcvdpsxds v2 3762; P9BE-NEXT: blr 3763; P9LE: lxv 3764; P9LE-NEXT: xxswapd 3765; P9LE-NEXT: xvcvdpsxds v2 3766; P9LE-NEXT: blr 3767; P8BE: lxvd2x 3768; P8BE-NEXT: xxswapd 3769; P8BE-NEXT: xvcvdpsxds v2 3770; P8BE-NEXT: blr 3771; P8LE: lxvd2x 3772; P8LE-NEXT: xvcvdpsxds v2 3773; P8LE-NEXT: blr 3774} 3775 3776; Function Attrs: norecurse nounwind readonly 3777define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3778entry: 3779 %idxprom = sext i32 %elem to i64 3780 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3781 %0 = load double, double* %arrayidx, align 8 3782 %conv = fptosi double %0 to i64 3783 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3784 %add = add nsw i32 %elem, 1 3785 %idxprom1 = sext i32 %add to i64 3786 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3787 %1 = load double, double* %arrayidx2, align 8 3788 %conv3 = fptosi double %1 to i64 3789 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3790 ret <2 x i64> %vecinit4 3791; P9BE-LABEL: fromDiffMemVarAConvdtoll 3792; P9LE-LABEL: fromDiffMemVarAConvdtoll 3793; P8BE-LABEL: fromDiffMemVarAConvdtoll 3794; P8LE-LABEL: fromDiffMemVarAConvdtoll 3795; P9BE: sldi 3796; P9BE: lxvx 3797; P9BE-NEXT: xvcvdpsxds v2 3798; P9BE-NEXT: blr 3799; P9LE: sldi 3800; P9LE: lxvx 3801; P9LE-NEXT: xvcvdpsxds v2 3802; P9LE-NEXT: blr 3803; P8BE: sldi 3804; P8BE: lxvd2x 3805; P8BE-NEXT: xvcvdpsxds v2 3806; P8BE-NEXT: blr 3807; P8LE: sldi 3808; P8LE: lxvd2x 3809; P8LE-NEXT: xxswapd 3810; P8LE-NEXT: xvcvdpsxds v2 3811; P8LE-NEXT: blr 3812} 3813 3814; Function Attrs: norecurse nounwind readonly 3815define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 3816entry: 3817 %idxprom = sext i32 %elem to i64 3818 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3819 %0 = load double, double* %arrayidx, align 8 3820 %conv = fptosi double %0 to i64 3821 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 3822 %sub = add nsw i32 %elem, -1 3823 %idxprom1 = sext i32 %sub to i64 3824 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3825 %1 = load double, double* %arrayidx2, align 8 3826 %conv3 = fptosi double %1 to i64 3827 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 3828 ret <2 x i64> %vecinit4 3829; P9BE-LABEL: fromDiffMemVarDConvdtoll 3830; P9LE-LABEL: fromDiffMemVarDConvdtoll 3831; P8BE-LABEL: fromDiffMemVarDConvdtoll 3832; P8LE-LABEL: fromDiffMemVarDConvdtoll 3833; P9BE: sldi 3834; P9BE: lxv 3835; P9BE-NEXT: xxswapd 3836; P9BE-NEXT: xvcvdpsxds v2 3837; P9BE-NEXT: blr 3838; P9LE: sldi 3839; P9LE: lxv 3840; P9LE-NEXT: xxswapd 3841; P9LE-NEXT: xvcvdpsxds v2 3842; P9LE-NEXT: blr 3843; P8BE: sldi 3844; P8BE: lxvd2x 3845; P8BE-NEXT: xxswapd 3846; P8BE-NEXT: xvcvdpsxds v2 3847; P8BE-NEXT: blr 3848; P8LE: sldi 3849; P8LE: lxvd2x 3850; P8LE-NEXT: xvcvdpsxds v2 3851; P8LE-NEXT: blr 3852} 3853 3854; Function Attrs: norecurse nounwind readnone 3855define <2 x i64> @spltRegValConvdtoll(double %val) { 3856entry: 3857 %conv = fptosi double %val to i64 3858 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3859 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3860 ret <2 x i64> %splat.splat 3861; P9BE-LABEL: spltRegValConvdtoll 3862; P9LE-LABEL: spltRegValConvdtoll 3863; P8BE-LABEL: spltRegValConvdtoll 3864; P8LE-LABEL: spltRegValConvdtoll 3865; P9BE: xscvdpsxds 3866; P9BE-NEXT: xxspltd v2 3867; P9BE-NEXT: blr 3868; P9LE: xscvdpsxds 3869; P9LE-NEXT: xxspltd v2 3870; P9LE-NEXT: blr 3871; P8BE: xscvdpsxds 3872; P8BE-NEXT: xxspltd v2 3873; P8BE-NEXT: blr 3874; P8LE: xscvdpsxds 3875; P8LE-NEXT: xxspltd v2 3876; P8LE-NEXT: blr 3877} 3878 3879; Function Attrs: norecurse nounwind readonly 3880define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 3881entry: 3882 %0 = load double, double* %ptr, align 8 3883 %conv = fptosi double %0 to i64 3884 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 3885 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 3886 ret <2 x i64> %splat.splat 3887; P9BE-LABEL: spltMemValConvdtoll 3888; P9LE-LABEL: spltMemValConvdtoll 3889; P8BE-LABEL: spltMemValConvdtoll 3890; P8LE-LABEL: spltMemValConvdtoll 3891; P9BE: lxvdsx 3892; P9BE-NEXT: xvcvdpsxds 3893; P9BE-NEXT: blr 3894; P9LE: lxvdsx 3895; P9LE-NEXT: xvcvdpsxds 3896; P9LE-NEXT: blr 3897; P8BE: lxvdsx 3898; P8BE-NEXT: xvcvdpsxds 3899; P8BE-NEXT: blr 3900; P8LE: lxvdsx 3901; P8LE-NEXT: xvcvdpsxds 3902; P8LE-NEXT: blr 3903} 3904 3905; Function Attrs: norecurse nounwind readnone 3906define <2 x i64> @allZeroull() { 3907entry: 3908 ret <2 x i64> zeroinitializer 3909; P9BE-LABEL: allZeroull 3910; P9LE-LABEL: allZeroull 3911; P8BE-LABEL: allZeroull 3912; P8LE-LABEL: allZeroull 3913; P9BE: xxlxor v2, v2, v2 3914; P9BE: blr 3915; P9LE: xxlxor v2, v2, v2 3916; P9LE: blr 3917; P8BE: xxlxor v2, v2, v2 3918; P8BE: blr 3919; P8LE: xxlxor v2, v2, v2 3920; P8LE: blr 3921} 3922 3923; Function Attrs: norecurse nounwind readnone 3924define <2 x i64> @allOneull() { 3925entry: 3926 ret <2 x i64> <i64 -1, i64 -1> 3927; P9BE-LABEL: allOneull 3928; P9LE-LABEL: allOneull 3929; P8BE-LABEL: allOneull 3930; P8LE-LABEL: allOneull 3931; P9BE: xxspltib v2, 255 3932; P9BE: blr 3933; P9LE: xxspltib v2, 255 3934; P9LE: blr 3935; P8BE: vspltisb v2, -1 3936; P8BE: blr 3937; P8LE: vspltisb v2, -1 3938; P8LE: blr 3939} 3940 3941; Function Attrs: norecurse nounwind readnone 3942define <2 x i64> @spltConst1ull() { 3943entry: 3944 ret <2 x i64> <i64 1, i64 1> 3945; P9BE-LABEL: spltConst1ull 3946; P9LE-LABEL: spltConst1ull 3947; P8BE-LABEL: spltConst1ull 3948; P8LE-LABEL: spltConst1ull 3949; P9BE: lxv 3950; P9BE: blr 3951; P9LE: lxv 3952; P9LE: blr 3953; P8BE: lxvd2x 3954; P8BE: blr 3955; P8LE: lxvd2x 3956; P8LE: blr 3957} 3958 3959; Function Attrs: norecurse nounwind readnone 3960define <2 x i64> @spltConst16kull() { 3961entry: 3962 ret <2 x i64> <i64 32767, i64 32767> 3963; P9BE-LABEL: spltConst16kull 3964; P9LE-LABEL: spltConst16kull 3965; P8BE-LABEL: spltConst16kull 3966; P8LE-LABEL: spltConst16kull 3967; P9BE: lxv 3968; P9BE: blr 3969; P9LE: lxv 3970; P9LE: blr 3971; P8BE: lxvd2x 3972; P8BE: blr 3973; P8LE: lxvd2x 3974; P8LE: blr 3975} 3976 3977; Function Attrs: norecurse nounwind readnone 3978define <2 x i64> @spltConst32kull() { 3979entry: 3980 ret <2 x i64> <i64 65535, i64 65535> 3981; P9BE-LABEL: spltConst32kull 3982; P9LE-LABEL: spltConst32kull 3983; P8BE-LABEL: spltConst32kull 3984; P8LE-LABEL: spltConst32kull 3985; P9BE: lxv 3986; P9BE: blr 3987; P9LE: lxv 3988; P9LE: blr 3989; P8BE: lxvd2x 3990; P8BE: blr 3991; P8LE: lxvd2x 3992; P8LE: blr 3993} 3994 3995; Function Attrs: norecurse nounwind readnone 3996define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 3997entry: 3998 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3999 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4000 ret <2 x i64> %vecinit1 4001; P9BE-LABEL: fromRegsull 4002; P9LE-LABEL: fromRegsull 4003; P8BE-LABEL: fromRegsull 4004; P8LE-LABEL: fromRegsull 4005; P9BE: mtvsrdd v2, r3, r4 4006; P9BE: blr 4007; P9LE: mtvsrdd v2, r4, r3 4008; P9LE: blr 4009; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4010; P8BE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4011; P8BE: xxmrghd v2 4012; P8BE: blr 4013; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r3 4014; P8LE-DAG: mtvsrd {{[vsf0-9]+}}, r4 4015; P8LE: xxmrghd v2 4016; P8LE: blr 4017} 4018 4019; Function Attrs: norecurse nounwind readnone 4020define <2 x i64> @fromDiffConstsull() { 4021entry: 4022 ret <2 x i64> <i64 242, i64 -113> 4023; P9BE-LABEL: fromDiffConstsull 4024; P9LE-LABEL: fromDiffConstsull 4025; P8BE-LABEL: fromDiffConstsull 4026; P8LE-LABEL: fromDiffConstsull 4027; P9BE: lxv 4028; P9BE: blr 4029; P9LE: lxv 4030; P9LE: blr 4031; P8BE: lxvd2x 4032; P8BE: blr 4033; P8LE: lxvd2x 4034; P8LE: blr 4035} 4036 4037; Function Attrs: norecurse nounwind readonly 4038define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 4039entry: 4040 %0 = load i64, i64* %arr, align 8 4041 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4042 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4043 %1 = load i64, i64* %arrayidx1, align 8 4044 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4045 ret <2 x i64> %vecinit2 4046; P9BE-LABEL: fromDiffMemConsAull 4047; P9LE-LABEL: fromDiffMemConsAull 4048; P8BE-LABEL: fromDiffMemConsAull 4049; P8LE-LABEL: fromDiffMemConsAull 4050; P9BE: lxv v2 4051; P9BE: blr 4052; P9LE: lxv v2 4053; P9LE: blr 4054; P8BE: lxvd2x v2 4055; P8BE: blr 4056; P8LE: lxvd2x 4057; P8LE: xxswapd v2 4058; P8LE: blr 4059} 4060 4061; Function Attrs: norecurse nounwind readonly 4062define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 4063entry: 4064 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4065 %0 = load i64, i64* %arrayidx, align 8 4066 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4067 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4068 %1 = load i64, i64* %arrayidx1, align 8 4069 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4070 ret <2 x i64> %vecinit2 4071; P9BE-LABEL: fromDiffMemConsDull 4072; P9LE-LABEL: fromDiffMemConsDull 4073; P8BE-LABEL: fromDiffMemConsDull 4074; P8LE-LABEL: fromDiffMemConsDull 4075; P9BE: lxv v2 4076; P9BE: blr 4077; P9LE: lxv 4078; P9LE: xxswapd v2 4079; P9LE: blr 4080; P8BE: lxvd2x 4081; P8BE: xxswapd v2 4082; P8BE-NEXT: blr 4083; P8LE: lxvd2x v2 4084; P8LE-NEXT: blr 4085} 4086 4087; Function Attrs: norecurse nounwind readonly 4088define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 4089entry: 4090 %idxprom = sext i32 %elem to i64 4091 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4092 %0 = load i64, i64* %arrayidx, align 8 4093 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4094 %add = add nsw i32 %elem, 1 4095 %idxprom1 = sext i32 %add to i64 4096 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4097 %1 = load i64, i64* %arrayidx2, align 8 4098 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4099 ret <2 x i64> %vecinit3 4100; P9BE-LABEL: fromDiffMemVarAull 4101; P9LE-LABEL: fromDiffMemVarAull 4102; P8BE-LABEL: fromDiffMemVarAull 4103; P8LE-LABEL: fromDiffMemVarAull 4104; P9BE: sldi 4105; P9BE: lxvx v2 4106; P9BE-NEXT: blr 4107; P9LE: sldi 4108; P9LE: lxvx v2 4109; P9LE-NEXT: blr 4110; P8BE: sldi 4111; P8BE: lxvd2x v2 4112; P8BE-NEXT: blr 4113; P8LE: sldi 4114; P8LE: lxvd2x 4115; P8LE: xxswapd v2 4116; P8LE-NEXT: blr 4117} 4118 4119; Function Attrs: norecurse nounwind readonly 4120define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 4121entry: 4122 %idxprom = sext i32 %elem to i64 4123 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4124 %0 = load i64, i64* %arrayidx, align 8 4125 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4126 %sub = add nsw i32 %elem, -1 4127 %idxprom1 = sext i32 %sub to i64 4128 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4129 %1 = load i64, i64* %arrayidx2, align 8 4130 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4131 ret <2 x i64> %vecinit3 4132; P9BE-LABEL: fromDiffMemVarDull 4133; P9LE-LABEL: fromDiffMemVarDull 4134; P8BE-LABEL: fromDiffMemVarDull 4135; P8LE-LABEL: fromDiffMemVarDull 4136; P9BE: sldi 4137; P9BE: lxv 4138; P9BE: xxswapd v2 4139; P9BE-NEXT: blr 4140; P9LE: sldi 4141; P9LE: lxv 4142; P9LE: xxswapd v2 4143; P9LE-NEXT: blr 4144; P8BE: sldi 4145; P8BE: lxvd2x 4146; P8BE: xxswapd v2 4147; P8BE-NEXT: blr 4148; P8LE: sldi 4149; P8LE: lxvd2x v2 4150; P8LE-NEXT: blr 4151} 4152 4153; Function Attrs: norecurse nounwind readonly 4154define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 4155entry: 4156 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4157 %0 = load i64, i64* %arrayidx, align 8 4158 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4159 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4160 %1 = load i64, i64* %arrayidx1, align 8 4161 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4162 ret <2 x i64> %vecinit2 4163; P9BE-LABEL: fromRandMemConsull 4164; P9LE-LABEL: fromRandMemConsull 4165; P8BE-LABEL: fromRandMemConsull 4166; P8LE-LABEL: fromRandMemConsull 4167; P9BE: ld 4168; P9BE: ld 4169; P9BE: mtvsrdd v2 4170; P9BE-NEXT: blr 4171; P9LE: ld 4172; P9LE: ld 4173; P9LE: mtvsrdd v2 4174; P9LE-NEXT: blr 4175; P8BE: ld 4176; P8BE: ld 4177; P8BE-DAG: mtvsrd 4178; P8BE-DAG: mtvsrd 4179; P8BE: xxmrghd v2 4180; P8BE-NEXT: blr 4181; P8LE: ld 4182; P8LE: ld 4183; P8LE-DAG: mtvsrd 4184; P8LE-DAG: mtvsrd 4185; P8LE: xxmrghd v2 4186; P8LE-NEXT: blr 4187} 4188 4189; Function Attrs: norecurse nounwind readonly 4190define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 4191entry: 4192 %add = add nsw i32 %elem, 4 4193 %idxprom = sext i32 %add to i64 4194 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4195 %0 = load i64, i64* %arrayidx, align 8 4196 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4197 %add1 = add nsw i32 %elem, 1 4198 %idxprom2 = sext i32 %add1 to i64 4199 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4200 %1 = load i64, i64* %arrayidx3, align 8 4201 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4202 ret <2 x i64> %vecinit4 4203; P9BE-LABEL: fromRandMemVarull 4204; P9LE-LABEL: fromRandMemVarull 4205; P8BE-LABEL: fromRandMemVarull 4206; P8LE-LABEL: fromRandMemVarull 4207; P9BE: sldi 4208; P9BE: ld 4209; P9BE: ld 4210; P9BE: mtvsrdd v2 4211; P9BE-NEXT: blr 4212; P9LE: sldi 4213; P9LE: ld 4214; P9LE: ld 4215; P9LE: mtvsrdd v2 4216; P9LE-NEXT: blr 4217; P8BE: sldi 4218; P8BE: ld 4219; P8BE: ld 4220; P8BE: mtvsrd 4221; P8BE: mtvsrd 4222; P8BE: xxmrghd v2 4223; P8BE-NEXT: blr 4224; P8LE: sldi 4225; P8LE: ld 4226; P8LE: ld 4227; P8LE: mtvsrd 4228; P8LE: mtvsrd 4229; P8LE: xxmrghd v2 4230; P8LE-NEXT: blr 4231} 4232 4233; Function Attrs: norecurse nounwind readnone 4234define <2 x i64> @spltRegValull(i64 %val) { 4235entry: 4236 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4237 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4238 ret <2 x i64> %splat.splat 4239; P9BE-LABEL: spltRegValull 4240; P9LE-LABEL: spltRegValull 4241; P8BE-LABEL: spltRegValull 4242; P8LE-LABEL: spltRegValull 4243; P9BE: mtvsrdd v2, r3, r3 4244; P9BE-NEXT: blr 4245; P9LE: mtvsrdd v2, r3, r3 4246; P9LE-NEXT: blr 4247; P8BE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4248; P8BE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4249; P8BE-NEXT: blr 4250; P8LE: mtvsrd {{[vsf]+}}[[REG1:[0-9]+]], r3 4251; P8LE: xxspltd v2, {{[vsf]+}}[[REG1]], 0 4252; P8LE-NEXT: blr 4253} 4254 4255; Function Attrs: norecurse nounwind readonly 4256define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 4257entry: 4258 %0 = load i64, i64* %ptr, align 8 4259 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4260 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4261 ret <2 x i64> %splat.splat 4262; P9BE-LABEL: spltMemValull 4263; P9LE-LABEL: spltMemValull 4264; P8BE-LABEL: spltMemValull 4265; P8LE-LABEL: spltMemValull 4266; P9BE: lxvdsx v2 4267; P9BE-NEXT: blr 4268; P9LE: lxvdsx v2 4269; P9LE-NEXT: blr 4270; P8BE: lxvdsx v2 4271; P8BE-NEXT: blr 4272; P8LE: lxvdsx v2 4273; P8LE-NEXT: blr 4274} 4275 4276; Function Attrs: norecurse nounwind readnone 4277define <2 x i64> @spltCnstConvftoull() { 4278entry: 4279 ret <2 x i64> <i64 4, i64 4> 4280; P9BE-LABEL: spltCnstConvftoull 4281; P9LE-LABEL: spltCnstConvftoull 4282; P8BE-LABEL: spltCnstConvftoull 4283; P8LE-LABEL: spltCnstConvftoull 4284; P9BE: lxv 4285; P9BE: blr 4286; P9LE: lxv 4287; P9LE: blr 4288; P8BE: lxvd2x 4289; P8BE: blr 4290; P8LE: lxvd2x 4291; P8LE: blr 4292} 4293 4294; Function Attrs: norecurse nounwind readnone 4295define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 4296entry: 4297 %conv = fptoui float %a to i64 4298 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4299 %conv1 = fptoui float %b to i64 4300 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4301 ret <2 x i64> %vecinit2 4302; P9BE-LABEL: fromRegsConvftoull 4303; P9LE-LABEL: fromRegsConvftoull 4304; P8BE-LABEL: fromRegsConvftoull 4305; P8LE-LABEL: fromRegsConvftoull 4306; P9BE: xxmrghd 4307; P9BE: xvcvdpuxds v2 4308; P9BE-NEXT: blr 4309; P9LE: xxmrghd 4310; P9LE: xvcvdpuxds v2 4311; P9LE-NEXT: blr 4312; P8BE: xxmrghd 4313; P8BE: xvcvdpuxds v2 4314; P8BE-NEXT: blr 4315; P8LE: xxmrghd 4316; P8LE: xvcvdpuxds v2 4317; P8LE-NEXT: blr 4318} 4319 4320; Function Attrs: norecurse nounwind readnone 4321define <2 x i64> @fromDiffConstsConvftoull() { 4322entry: 4323 ret <2 x i64> <i64 24, i64 234> 4324; P9BE-LABEL: fromDiffConstsConvftoull 4325; P9LE-LABEL: fromDiffConstsConvftoull 4326; P8BE-LABEL: fromDiffConstsConvftoull 4327; P8LE-LABEL: fromDiffConstsConvftoull 4328; P9BE: lxvx v2 4329; P9BE: blr 4330; P9LE: lxvx v2 4331; P9LE: blr 4332; P8BE: lxvd2x v2 4333; P8BE: blr 4334; P8LE: lxvd2x 4335; P8LE: xxswapd v2 4336; P8LE: blr 4337} 4338 4339; Function Attrs: norecurse nounwind readonly 4340define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 4341entry: 4342 %0 = load float, float* %ptr, align 4 4343 %conv = fptoui float %0 to i64 4344 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4345 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4346 %1 = load float, float* %arrayidx1, align 4 4347 %conv2 = fptoui float %1 to i64 4348 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4349 ret <2 x i64> %vecinit3 4350; P9BE-LABEL: fromDiffMemConsAConvftoull 4351; P9LE-LABEL: fromDiffMemConsAConvftoull 4352; P8BE-LABEL: fromDiffMemConsAConvftoull 4353; P8LE-LABEL: fromDiffMemConsAConvftoull 4354; P9BE: lfs 4355; P9BE: lfs 4356; P9BE: xxmrghd 4357; P9BE-NEXT: xvcvdpuxds v2 4358; P9BE-NEXT: blr 4359; P9LE: lfs 4360; P9LE: lfs 4361; P9LE: xxmrghd 4362; P9LE-NEXT: xvcvdpuxds v2 4363; P9LE-NEXT: blr 4364; P8BE: lfs 4365; P8BE: lfs 4366; P8BE: xxmrghd 4367; P8BE-NEXT: xvcvdpuxds v2 4368; P8BE-NEXT: blr 4369; P8LE: lfs 4370; P8LE: lfs 4371; P8LE: xxmrghd 4372; P8LE-NEXT: xvcvdpuxds v2 4373; P8LE-NEXT: blr 4374} 4375 4376; Function Attrs: norecurse nounwind readonly 4377define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 4378entry: 4379 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4380 %0 = load float, float* %arrayidx, align 4 4381 %conv = fptoui float %0 to i64 4382 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4383 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4384 %1 = load float, float* %arrayidx1, align 4 4385 %conv2 = fptoui float %1 to i64 4386 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4387 ret <2 x i64> %vecinit3 4388; P9BE-LABEL: fromDiffMemConsDConvftoull 4389; P9LE-LABEL: fromDiffMemConsDConvftoull 4390; P8BE-LABEL: fromDiffMemConsDConvftoull 4391; P8LE-LABEL: fromDiffMemConsDConvftoull 4392; P9BE: lfs 4393; P9BE: lfs 4394; P9BE: xxmrghd 4395; P9BE-NEXT: xvcvdpuxds v2 4396; P9BE-NEXT: blr 4397; P9LE: lfs 4398; P9LE: lfs 4399; P9LE: xxmrghd 4400; P9LE-NEXT: xvcvdpuxds v2 4401; P9LE-NEXT: blr 4402; P8BE: lfs 4403; P8BE: lfs 4404; P8BE: xxmrghd 4405; P8BE-NEXT: xvcvdpuxds v2 4406; P8BE-NEXT: blr 4407; P8LE: lfs 4408; P8LE: lfs 4409; P8LE: xxmrghd 4410; P8LE-NEXT: xvcvdpuxds v2 4411; P8LE-NEXT: blr 4412} 4413 4414; Function Attrs: norecurse nounwind readonly 4415define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4416entry: 4417 %idxprom = sext i32 %elem to i64 4418 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4419 %0 = load float, float* %arrayidx, align 4 4420 %conv = fptoui float %0 to i64 4421 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4422 %add = add nsw i32 %elem, 1 4423 %idxprom1 = sext i32 %add to i64 4424 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4425 %1 = load float, float* %arrayidx2, align 4 4426 %conv3 = fptoui float %1 to i64 4427 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4428 ret <2 x i64> %vecinit4 4429; P9BE-LABEL: fromDiffMemVarAConvftoull 4430; P9LE-LABEL: fromDiffMemVarAConvftoull 4431; P8BE-LABEL: fromDiffMemVarAConvftoull 4432; P8LE-LABEL: fromDiffMemVarAConvftoull 4433; P9BE: sldi 4434; P9BE: lfsux 4435; P9BE: lfs 4436; P9BE: xxmrghd 4437; P9BE-NEXT: xvcvdpuxds v2 4438; P9BE-NEXT: blr 4439; P9LE: sldi 4440; P9LE: lfsux 4441; P9LE: lfs 4442; P9LE: xxmrghd 4443; P9LE-NEXT: xvcvdpuxds v2 4444; P9LE-NEXT: blr 4445; P8BE: sldi 4446; P8BE: lfsux 4447; P8BE: lfs 4448; P8BE: xxmrghd 4449; P8BE-NEXT: xvcvdpuxds v2 4450; P8BE-NEXT: blr 4451; P8LE: sldi 4452; P8LE: lfsux 4453; P8LE: lfs 4454; P8LE: xxmrghd 4455; P8LE-NEXT: xvcvdpuxds v2 4456; P8LE-NEXT: blr 4457} 4458 4459; Function Attrs: norecurse nounwind readonly 4460define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 4461entry: 4462 %idxprom = sext i32 %elem to i64 4463 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4464 %0 = load float, float* %arrayidx, align 4 4465 %conv = fptoui float %0 to i64 4466 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4467 %sub = add nsw i32 %elem, -1 4468 %idxprom1 = sext i32 %sub to i64 4469 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4470 %1 = load float, float* %arrayidx2, align 4 4471 %conv3 = fptoui float %1 to i64 4472 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4473 ret <2 x i64> %vecinit4 4474; P9BE-LABEL: fromDiffMemVarDConvftoull 4475; P9LE-LABEL: fromDiffMemVarDConvftoull 4476; P8BE-LABEL: fromDiffMemVarDConvftoull 4477; P8LE-LABEL: fromDiffMemVarDConvftoull 4478; P9BE: sldi 4479; P9BE: lfsux 4480; P9BE: lfs 4481; P9BE: xxmrghd 4482; P9BE-NEXT: xvcvdpuxds v2 4483; P9BE-NEXT: blr 4484; P9LE: sldi 4485; P9LE: lfsux 4486; P9LE: lfs 4487; P9LE: xxmrghd 4488; P9LE-NEXT: xvcvdpuxds v2 4489; P9LE-NEXT: blr 4490; P8BE: sldi 4491; P8BE: lfsux 4492; P8BE: lfs 4493; P8BE: xxmrghd 4494; P8BE-NEXT: xvcvdpuxds v2 4495; P8BE-NEXT: blr 4496; P8LE: sldi 4497; P8LE: lfsux 4498; P8LE: lfs 4499; P8LE: xxmrghd 4500; P8LE-NEXT: xvcvdpuxds v2 4501; P8LE-NEXT: blr 4502} 4503 4504; Function Attrs: norecurse nounwind readnone 4505define <2 x i64> @spltRegValConvftoull(float %val) { 4506entry: 4507 %conv = fptoui float %val to i64 4508 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4509 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4510 ret <2 x i64> %splat.splat 4511; P9BE-LABEL: spltRegValConvftoull 4512; P9LE-LABEL: spltRegValConvftoull 4513; P8BE-LABEL: spltRegValConvftoull 4514; P8LE-LABEL: spltRegValConvftoull 4515; P9BE: xscvdpuxds 4516; P9BE-NEXT: xxspltd v2 4517; P9BE-NEXT: blr 4518; P9LE: xscvdpuxds 4519; P9LE-NEXT: xxspltd v2 4520; P9LE-NEXT: blr 4521; P8BE: xscvdpuxds 4522; P8BE-NEXT: xxspltd v2 4523; P8BE-NEXT: blr 4524; P8LE: xscvdpuxds 4525; P8LE-NEXT: xxspltd v2 4526; P8LE-NEXT: blr 4527} 4528 4529; Function Attrs: norecurse nounwind readonly 4530define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 4531entry: 4532 %0 = load float, float* %ptr, align 4 4533 %conv = fptoui float %0 to i64 4534 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4535 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4536 ret <2 x i64> %splat.splat 4537; P9BE-LABEL: spltMemValConvftoull 4538; P9LE-LABEL: spltMemValConvftoull 4539; P8BE-LABEL: spltMemValConvftoull 4540; P8LE-LABEL: spltMemValConvftoull 4541; P9BE: lfs 4542; P9BE-NEXT: xscvdpuxds 4543; P9BE-NEXT: xxspltd v2 4544; P9BE-NEXT: blr 4545; P9LE: lfs 4546; P9LE-NEXT: xscvdpuxds 4547; P9LE-NEXT: xxspltd v2 4548; P9LE-NEXT: blr 4549; P8BE: lfs 4550; P8BE-NEXT: xscvdpuxds 4551; P8BE-NEXT: xxspltd v2 4552; P8BE-NEXT: blr 4553; P8LE: lfs 4554; P8LE-NEXT: xscvdpuxds 4555; P8LE-NEXT: xxspltd v2 4556; P8LE-NEXT: blr 4557} 4558 4559; Function Attrs: norecurse nounwind readnone 4560define <2 x i64> @spltCnstConvdtoull() { 4561entry: 4562 ret <2 x i64> <i64 4, i64 4> 4563; P9BE-LABEL: spltCnstConvdtoull 4564; P9LE-LABEL: spltCnstConvdtoull 4565; P8BE-LABEL: spltCnstConvdtoull 4566; P8LE-LABEL: spltCnstConvdtoull 4567; P9BE: lxv 4568; P9BE: blr 4569; P9LE: lxv 4570; P9LE: blr 4571; P8BE: lxvd2x 4572; P8BE: blr 4573; P8LE: lxvd2x 4574; P8LE: blr 4575} 4576 4577; Function Attrs: norecurse nounwind readnone 4578define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 4579entry: 4580 %conv = fptoui double %a to i64 4581 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4582 %conv1 = fptoui double %b to i64 4583 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4584 ret <2 x i64> %vecinit2 4585; P9BE-LABEL: fromRegsConvdtoull 4586; P9LE-LABEL: fromRegsConvdtoull 4587; P8BE-LABEL: fromRegsConvdtoull 4588; P8LE-LABEL: fromRegsConvdtoull 4589; P9BE: xxmrghd 4590; P9BE-NEXT: xvcvdpuxds 4591; P9BE-NEXT: blr 4592; P9LE: xxmrghd 4593; P9LE-NEXT: xvcvdpuxds 4594; P9LE-NEXT: blr 4595; P8BE: xxmrghd 4596; P8BE-NEXT: xvcvdpuxds 4597; P8BE-NEXT: blr 4598; P8LE: xxmrghd 4599; P8LE-NEXT: xvcvdpuxds 4600; P8LE-NEXT: blr 4601} 4602 4603; Function Attrs: norecurse nounwind readnone 4604define <2 x i64> @fromDiffConstsConvdtoull() { 4605entry: 4606 ret <2 x i64> <i64 24, i64 234> 4607; P9BE-LABEL: fromDiffConstsConvdtoull 4608; P9LE-LABEL: fromDiffConstsConvdtoull 4609; P8BE-LABEL: fromDiffConstsConvdtoull 4610; P8LE-LABEL: fromDiffConstsConvdtoull 4611; P9BE: lxv 4612; P9BE: blr 4613; P9LE: lxv 4614; P9LE: blr 4615; P8BE: lxvd2x 4616; P8BE: blr 4617; P8LE: lxvd2x 4618; P8LE: blr 4619} 4620 4621; Function Attrs: norecurse nounwind readonly 4622define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 4623entry: 4624 %0 = bitcast double* %ptr to <2 x double>* 4625 %1 = load <2 x double>, <2 x double>* %0, align 8 4626 %2 = fptoui <2 x double> %1 to <2 x i64> 4627 ret <2 x i64> %2 4628; P9BE-LABEL: fromDiffMemConsAConvdtoull 4629; P9LE-LABEL: fromDiffMemConsAConvdtoull 4630; P8BE-LABEL: fromDiffMemConsAConvdtoull 4631; P8LE-LABEL: fromDiffMemConsAConvdtoull 4632; P9BE: lxv 4633; P9BE-NEXT: xvcvdpuxds v2 4634; P9BE-NEXT: blr 4635; P9LE: lxv 4636; P9LE-NEXT: xvcvdpuxds v2 4637; P9LE-NEXT: blr 4638; P8BE: lxvd2x 4639; P8BE-NEXT: xvcvdpuxds v2 4640; P8BE-NEXT: blr 4641; P8LE: lxvd2x 4642; P8LE: xxswapd 4643; P8LE-NEXT: xvcvdpuxds v2 4644; P8LE-NEXT: blr 4645} 4646 4647; Function Attrs: norecurse nounwind readonly 4648define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 4649entry: 4650 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4651 %0 = load double, double* %arrayidx, align 8 4652 %conv = fptoui double %0 to i64 4653 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4654 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4655 %1 = load double, double* %arrayidx1, align 8 4656 %conv2 = fptoui double %1 to i64 4657 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4658 ret <2 x i64> %vecinit3 4659; P9BE-LABEL: fromDiffMemConsDConvdtoull 4660; P9LE-LABEL: fromDiffMemConsDConvdtoull 4661; P8BE-LABEL: fromDiffMemConsDConvdtoull 4662; P8LE-LABEL: fromDiffMemConsDConvdtoull 4663; P9BE: lxv 4664; P9BE-NEXT: xxswapd 4665; P9BE-NEXT: xvcvdpuxds v2 4666; P9BE-NEXT: blr 4667; P9LE: lxv 4668; P9LE-NEXT: xxswapd 4669; P9LE-NEXT: xvcvdpuxds v2 4670; P9LE-NEXT: blr 4671; P8BE: lxvd2x 4672; P8BE-NEXT: xxswapd 4673; P8BE-NEXT: xvcvdpuxds v2 4674; P8BE-NEXT: blr 4675; P8LE: lxvd2x 4676; P8LE-NEXT: xvcvdpuxds v2 4677; P8LE-NEXT: blr 4678} 4679 4680; Function Attrs: norecurse nounwind readonly 4681define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4682entry: 4683 %idxprom = sext i32 %elem to i64 4684 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4685 %0 = load double, double* %arrayidx, align 8 4686 %conv = fptoui double %0 to i64 4687 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4688 %add = add nsw i32 %elem, 1 4689 %idxprom1 = sext i32 %add to i64 4690 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4691 %1 = load double, double* %arrayidx2, align 8 4692 %conv3 = fptoui double %1 to i64 4693 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4694 ret <2 x i64> %vecinit4 4695; P9BE-LABEL: fromDiffMemVarAConvdtoull 4696; P9LE-LABEL: fromDiffMemVarAConvdtoull 4697; P8BE-LABEL: fromDiffMemVarAConvdtoull 4698; P8LE-LABEL: fromDiffMemVarAConvdtoull 4699; P9BE: sldi 4700; P9BE: lxvx 4701; P9BE-NEXT: xvcvdpuxds v2 4702; P9BE-NEXT: blr 4703; P9LE: sldi 4704; P9LE: lxvx 4705; P9LE-NEXT: xvcvdpuxds v2 4706; P9LE-NEXT: blr 4707; P8BE: sldi 4708; P8BE: lxvd2x 4709; P8BE-NEXT: xvcvdpuxds v2 4710; P8BE-NEXT: blr 4711; P8LE: sldi 4712; P8LE: lxvd2x 4713; P8LE-NEXT: xxswapd 4714; P8LE-NEXT: xvcvdpuxds v2 4715; P8LE-NEXT: blr 4716} 4717 4718; Function Attrs: norecurse nounwind readonly 4719define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 4720entry: 4721 %idxprom = sext i32 %elem to i64 4722 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4723 %0 = load double, double* %arrayidx, align 8 4724 %conv = fptoui double %0 to i64 4725 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4726 %sub = add nsw i32 %elem, -1 4727 %idxprom1 = sext i32 %sub to i64 4728 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4729 %1 = load double, double* %arrayidx2, align 8 4730 %conv3 = fptoui double %1 to i64 4731 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4732 ret <2 x i64> %vecinit4 4733; P9BE-LABEL: fromDiffMemVarDConvdtoull 4734; P9LE-LABEL: fromDiffMemVarDConvdtoull 4735; P8BE-LABEL: fromDiffMemVarDConvdtoull 4736; P8LE-LABEL: fromDiffMemVarDConvdtoull 4737; P9BE: sldi 4738; P9BE: lxv 4739; P9BE-NEXT: xxswapd 4740; P9BE-NEXT: xvcvdpuxds v2 4741; P9BE-NEXT: blr 4742; P9LE: sldi 4743; P9LE: lxv 4744; P9LE-NEXT: xxswapd 4745; P9LE-NEXT: xvcvdpuxds v2 4746; P9LE-NEXT: blr 4747; P8BE: sldi 4748; P8BE: lxvd2x 4749; P8BE-NEXT: xxswapd 4750; P8BE-NEXT: xvcvdpuxds v2 4751; P8BE-NEXT: blr 4752; P8LE: sldi 4753; P8LE: lxvd2x 4754; P8LE-NEXT: xvcvdpuxds v2 4755; P8LE-NEXT: blr 4756} 4757 4758; Function Attrs: norecurse nounwind readnone 4759define <2 x i64> @spltRegValConvdtoull(double %val) { 4760entry: 4761 %conv = fptoui double %val to i64 4762 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4763 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4764 ret <2 x i64> %splat.splat 4765; P9BE-LABEL: spltRegValConvdtoull 4766; P9LE-LABEL: spltRegValConvdtoull 4767; P8BE-LABEL: spltRegValConvdtoull 4768; P8LE-LABEL: spltRegValConvdtoull 4769; P9BE: xscvdpuxds 4770; P9BE-NEXT: xxspltd v2 4771; P9BE-NEXT: blr 4772; P9LE: xscvdpuxds 4773; P9LE-NEXT: xxspltd v2 4774; P9LE-NEXT: blr 4775; P8BE: xscvdpuxds 4776; P8BE-NEXT: xxspltd v2 4777; P8BE-NEXT: blr 4778; P8LE: xscvdpuxds 4779; P8LE-NEXT: xxspltd v2 4780; P8LE-NEXT: blr 4781} 4782 4783; Function Attrs: norecurse nounwind readonly 4784define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 4785entry: 4786 %0 = load double, double* %ptr, align 8 4787 %conv = fptoui double %0 to i64 4788 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4789 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4790 ret <2 x i64> %splat.splat 4791; P9BE-LABEL: spltMemValConvdtoull 4792; P9LE-LABEL: spltMemValConvdtoull 4793; P8BE-LABEL: spltMemValConvdtoull 4794; P8LE-LABEL: spltMemValConvdtoull 4795; P9BE: lxvdsx 4796; P9BE-NEXT: xvcvdpuxds 4797; P9BE-NEXT: blr 4798; P9LE: lxvdsx 4799; P9LE-NEXT: xvcvdpuxds 4800; P9LE-NEXT: blr 4801; P8BE: lxvdsx 4802; P8BE-NEXT: xvcvdpuxds 4803; P8BE-NEXT: blr 4804; P8LE: lxvdsx 4805; P8LE-NEXT: xvcvdpuxds 4806; P8LE-NEXT: blr 4807} 4808