1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck -allow-deprecated-dag-overlap %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int allOnei() { // 51; return (vector int)-1; // 52;} // 53;// P8: vspltisw 1 // 54;// P9: vspltisw 1 // 55;vector int spltConst1i() { // 56; return (vector int)1; // 57;} // 58;// P8: vspltisw -15; vsrw // 59;// P9: vspltisw -15; vsrw // 60;vector int spltConst16ki() { // 61; return (vector int)((1<<15) - 1); // 62;} // 63;// P8: vspltisw -16; vsrw // 64;// P9: vspltisw -16; vsrw // 65;vector int spltConst32ki() { // 66; return (vector int)((1<<16) - 1); // 67;} // 68;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 69;// P9: 2 x mtvsrdd, vmrgow // 70;vector int fromRegsi(int a, int b, int c, int d) { // 71; return (vector int){ a, b, c, d }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx (or even lxv) // 75;vector int fromDiffConstsi() { // 76; return (vector int) { 242, -113, 889, 19 }; // 77;} // 78;// P8: lxvd2x, xxswapd // 79;// P9: lxvx // 80;vector int fromDiffMemConsAi(int *arr) { // 81; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 82;} // 83;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 84;// P9: 2 x lxvx, vperm // 85;vector int fromDiffMemConsDi(int *arr) { // 86; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 87;} // 88;// P8: sldi 2, lxvd2x, xxswapd // 89;// P9: sldi 2, lxvx // 90;vector int fromDiffMemVarAi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 92;} // 93;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 94;// P9: sldi 2, 2 x lxvx, vperm // 95;vector int fromDiffMemVarDi(int *arr, int elem) { // 96; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 97;} // 98;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemConsi(int *arr) { // 101; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 102;} // 103;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 104;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 105;vector int fromRandMemVari(int *arr, int elem) { // 106; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 107;} // 108;// P8: mtvsrwz, xxspltw // 109;// P9: mtvsrws // 110;vector int spltRegVali(int val) { // 111; return (vector int) val; // 112;} // 113;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 114;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 115;vector int spltMemVali(int *ptr) { // 116; return (vector int)*ptr; // 117;} // 118;// P8: vspltisw // 119;// P9: vspltisw // 120;vector int spltCnstConvftoi() { // 121; return (vector int) 4.74f; // 122;} // 123;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 124;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 125;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 126; return (vector int) { a, b, c, d }; // 127;} // 128;// P8: lxvd2x, xxswapd // 129;// P9: lxvx (even lxv) // 130;vector int fromDiffConstsConvftoi() { // 131; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 132;} // 133;// P8: lxvd2x, xxswapd, xvcvspsxws // 134;// P9: lxvx, xvcvspsxws // 135;vector int fromDiffMemConsAConvftoi(float *ptr) { // 136; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 137;} // 138;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 139;// P9: 2 x lxvx, vperm, xvcvspsxws // 140;vector int fromDiffMemConsDConvftoi(float *ptr) { // 141; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 142;} // 143;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 144;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 145;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 146;// sldi 2, load, xvcvspuxws // 147;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 148; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 149;} // 150;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 151;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 152;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 153;// sldi 2, 2 x load, vperm, xvcvspuxws // 154;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 155; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 156;} // 157;// P8: xscvdpsxws, xxspltw // 158;// P9: xscvdpsxws, xxspltw // 159;vector int spltRegValConvftoi(float val) { // 160; return (vector int) val; // 161;} // 162;// P8: lxsspx, xscvdpsxws, xxspltw // 163;// P9: lxvwsx, xvcvspsxws // 164;vector int spltMemValConvftoi(float *ptr) { // 165; return (vector int)*ptr; // 166;} // 167;// P8: vspltisw // 168;// P9: vspltisw // 169;vector int spltCnstConvdtoi() { // 170; return (vector int) 4.74; // 171;} // 172;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 173;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 174;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 175; return (vector int) { a, b, c, d }; // 176;} // 177;// P8: lxvd2x, xxswapd // 178;// P9: lxvx (even lxv) // 179;vector int fromDiffConstsConvdtoi() { // 180; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 181;} // 182;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 185; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 186;} // 187;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 190; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 196;} // 197;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 198;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 199;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 200; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 201;} // 202;// P8: xscvdpsxws, xxspltw // 203;// P9: xscvdpsxws, xxspltw // 204;vector int spltRegValConvdtoi(double val) { // 205; return (vector int) val; // 206;} // 207;// P8: lxsdx, xscvdpsxws, xxspltw // 208;// P9: lxssp, xscvdpsxws, xxspltw // 209;vector int spltMemValConvdtoi(double *ptr) { // 210; return (vector int)*ptr; // 211;} // 212;/*=================================== int ===================================*/ 213;/*=============================== unsigned int ==============================*/ 214;// P8: xxlxor // 215;// P9: xxlxor // 216;vector unsigned int allZeroui() { // 217; return (vector unsigned int)0; // 218;} // 219;// P8: vspltisb -1 // 220;// P9: xxspltisb 255 // 221;vector unsigned int allOneui() { // 222; return (vector unsigned int)-1; // 223;} // 224;// P8: vspltisw 1 // 225;// P9: vspltisw 1 // 226;vector unsigned int spltConst1ui() { // 227; return (vector unsigned int)1; // 228;} // 229;// P8: vspltisw -15; vsrw // 230;// P9: vspltisw -15; vsrw // 231;vector unsigned int spltConst16kui() { // 232; return (vector unsigned int)((1<<15) - 1); // 233;} // 234;// P8: vspltisw -16; vsrw // 235;// P9: vspltisw -16; vsrw // 236;vector unsigned int spltConst32kui() { // 237; return (vector unsigned int)((1<<16) - 1); // 238;} // 239;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 240;// P9: 2 x mtvsrdd, vmrgow // 241;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 242; unsigned int c, unsigned int d) { // 243; return (vector unsigned int){ a, b, c, d }; // 244;} // 245;// P8: lxvd2x, xxswapd // 246;// P9: lxvx (or even lxv) // 247;vector unsigned int fromDiffConstsui() { // 248; return (vector unsigned int) { 242, -113, 889, 19 }; // 249;} // 250;// P8: lxvd2x, xxswapd // 251;// P9: lxvx // 252;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 253; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 254;} // 255;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 256;// P9: 2 x lxvx, vperm // 257;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 258; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 259;} // 260;// P8: sldi 2, lxvd2x, xxswapd // 261;// P9: sldi 2, lxvx // 262;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 263; return (vector unsigned int) { arr[elem], arr[elem+1], // 264; arr[elem+2], arr[elem+3] }; // 265;} // 266;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 267;// P9: sldi 2, 2 x lxvx, vperm // 268;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 269; return (vector unsigned int) { arr[elem], arr[elem-1], // 270; arr[elem-2], arr[elem-3] }; // 271;} // 272;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 273;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 274;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 275; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 276;} // 277;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 278;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 279;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 280; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 281; arr[elem+2], arr[elem+8] }; // 282;} // 283;// P8: mtvsrwz, xxspltw // 284;// P9: mtvsrws // 285;vector unsigned int spltRegValui(unsigned int val) { // 286; return (vector unsigned int) val; // 287;} // 288;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 289;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 290;vector unsigned int spltMemValui(unsigned int *ptr) { // 291; return (vector unsigned int)*ptr; // 292;} // 293;// P8: vspltisw // 294;// P9: vspltisw // 295;vector unsigned int spltCnstConvftoui() { // 296; return (vector unsigned int) 4.74f; // 297;} // 298;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 299;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 300;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 301; return (vector unsigned int) { a, b, c, d }; // 302;} // 303;// P8: lxvd2x, xxswapd // 304;// P9: lxvx (even lxv) // 305;vector unsigned int fromDiffConstsConvftoui() { // 306; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 307;} // 308;// P8: lxvd2x, xxswapd, xvcvspuxws // 309;// P9: lxvx, xvcvspuxws // 310;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 311; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 312;} // 313;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 314;// P9: 2 x lxvx, vperm, xvcvspuxws // 315;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 316; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 317;} // 318;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 319;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 320;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 321;// sldi 2, load, xvcvspuxws // 322;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 323; return (vector unsigned int) { arr[elem], arr[elem+1], // 324; arr[elem+2], arr[elem+3] }; // 325;} // 326;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 327;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 328;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 329;// sldi 2, 2 x load, vperm, xvcvspuxws // 330;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 331; return (vector unsigned int) { arr[elem], arr[elem-1], // 332; arr[elem-2], arr[elem-3] }; // 333;} // 334;// P8: xscvdpuxws, xxspltw // 335;// P9: xscvdpuxws, xxspltw // 336;vector unsigned int spltRegValConvftoui(float val) { // 337; return (vector unsigned int) val; // 338;} // 339;// P8: lxsspx, xscvdpuxws, xxspltw // 340;// P9: lxvwsx, xvcvspuxws // 341;vector unsigned int spltMemValConvftoui(float *ptr) { // 342; return (vector unsigned int)*ptr; // 343;} // 344;// P8: vspltisw // 345;// P9: vspltisw // 346;vector unsigned int spltCnstConvdtoui() { // 347; return (vector unsigned int) 4.74; // 348;} // 349;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 350;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 351;vector unsigned int fromRegsConvdtoui(double a, double b, // 352; double c, double d) { // 353; return (vector unsigned int) { a, b, c, d }; // 354;} // 355;// P8: lxvd2x, xxswapd // 356;// P9: lxvx (even lxv) // 357;vector unsigned int fromDiffConstsConvdtoui() { // 358; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 359;} // 360;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 363; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 364;} // 365;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 366;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 368; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 369;} // 370;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 371;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 372;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 373; return (vector unsigned int) { arr[elem], arr[elem+1], // 374; arr[elem+2], arr[elem+3] }; // 375;} // 376;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 377;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 378;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 379; return (vector unsigned int) { arr[elem], arr[elem-1], // 380; arr[elem-2], arr[elem-3] }; // 381;} // 382;// P8: xscvdpuxws, xxspltw // 383;// P9: xscvdpuxws, xxspltw // 384;vector unsigned int spltRegValConvdtoui(double val) { // 385; return (vector unsigned int) val; // 386;} // 387;// P8: lxsspx, xscvdpuxws, xxspltw // 388;// P9: lfd, xscvdpuxws, xxspltw // 389;vector unsigned int spltMemValConvdtoui(double *ptr) { // 390; return (vector unsigned int)*ptr; // 391;} // 392;/*=============================== unsigned int ==============================*/ 393;/*=============================== long long =================================*/ 394;// P8: xxlxor // 395;// P9: xxlxor // 396;vector long long allZeroll() { // 397; return (vector long long)0; // 398;} // 399;// P8: vspltisb -1 // 400;// P9: xxspltisb 255 // 401;vector long long allOnell() { // 402; return (vector long long)-1; // 403;} // 404;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 405;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 406;vector long long spltConst1ll() { // 407; return (vector long long)1; // 408;} // 409;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 410;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 411;vector long long spltConst16kll() { // 412; return (vector long long)((1<<15) - 1); // 413;} // 414;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 415;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 416;vector long long spltConst32kll() { // 417; return (vector long long)((1<<16) - 1); // 418;} // 419;// P8: 2 x mtvsrd, xxmrghd // 420;// P9: mtvsrdd // 421;vector long long fromRegsll(long long a, long long b) { // 422; return (vector long long){ a, b }; // 423;} // 424;// P8: lxvd2x, xxswapd // 425;// P9: lxvx (or even lxv) // 426;vector long long fromDiffConstsll() { // 427; return (vector long long) { 242, -113 }; // 428;} // 429;// P8: lxvd2x, xxswapd // 430;// P9: lxvx // 431;vector long long fromDiffMemConsAll(long long *arr) { // 432; return (vector long long) { arr[0], arr[1] }; // 433;} // 434;// P8: lxvd2x // 435;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 436;vector long long fromDiffMemConsDll(long long *arr) { // 437; return (vector long long) { arr[3], arr[2] }; // 438;} // 439;// P8: sldi 3, lxvd2x, xxswapd // 440;// P9: sldi 3, lxvx // 441;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem], arr[elem+1] }; // 443;} // 444;// P8: sldi 3, lxvd2x // 445;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 446;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 447; return (vector long long) { arr[elem], arr[elem-1] }; // 448;} // 449;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 450;// P9: 2 x ld, mtvsrdd // 451;vector long long fromRandMemConsll(long long *arr) { // 452; return (vector long long) { arr[4], arr[18] }; // 453;} // 454;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 455;// P9: sldi 3, add, 2 x ld, mtvsrdd // 456;vector long long fromRandMemVarll(long long *arr, int elem) { // 457; return (vector long long) { arr[elem+4], arr[elem+1] }; // 458;} // 459;// P8: mtvsrd, xxspltd // 460;// P9: mtvsrdd // 461;vector long long spltRegValll(long long val) { // 462; return (vector long long) val; // 463;} // 464;// P8: lxvdsx // 465;// P9: lxvdsx // 466;vector long long spltMemValll(long long *ptr) { // 467; return (vector long long)*ptr; // 468;} // 469;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 470;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 471;vector long long spltCnstConvftoll() { // 472; return (vector long long) 4.74f; // 473;} // 474;// P8: xxmrghd, xvcvdpsxds // 475;// P9: xxmrghd, xvcvdpsxds // 476;vector long long fromRegsConvftoll(float a, float b) { // 477; return (vector long long) { a, b }; // 478;} // 479;// P8: lxvd2x, xxswapd // 480;// P9: lxvx (even lxv) // 481;vector long long fromDiffConstsConvftoll() { // 482; return (vector long long) { 24.46f, 234.f }; // 483;} // 484;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 487; return (vector long long) { ptr[0], ptr[1] }; // 488;} // 489;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 490;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 491;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 492; return (vector long long) { ptr[3], ptr[2] }; // 493;} // 494;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 495;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 496;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 497; return (vector long long) { arr[elem], arr[elem+1] }; // 498;} // 499;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 500;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 501;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 502; return (vector long long) { arr[elem], arr[elem-1] }; // 503;} // 504;// P8: xscvdpsxds, xxspltd // 505;// P9: xscvdpsxds, xxspltd // 506;vector long long spltRegValConvftoll(float val) { // 507; return (vector long long) val; // 508;} // 509;// P8: lxsspx, xscvdpsxds, xxspltd // 510;// P9: lfs, xscvdpsxds, xxspltd // 511;vector long long spltMemValConvftoll(float *ptr) { // 512; return (vector long long)*ptr; // 513;} // 514;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 515;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 516;vector long long spltCnstConvdtoll() { // 517; return (vector long long) 4.74; // 518;} // 519;// P8: xxmrghd, xvcvdpsxds // 520;// P9: xxmrghd, xvcvdpsxds // 521;vector long long fromRegsConvdtoll(double a, double b) { // 522; return (vector long long) { a, b }; // 523;} // 524;// P8: lxvd2x, xxswapd // 525;// P9: lxvx (even lxv) // 526;vector long long fromDiffConstsConvdtoll() { // 527; return (vector long long) { 24.46, 234. }; // 528;} // 529;// P8: lxvd2x, xxswapd, xvcvdpsxds // 530;// P9: lxvx, xvcvdpsxds // 531;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 532; return (vector long long) { ptr[0], ptr[1] }; // 533;} // 534;// P8: lxvd2x, xvcvdpsxds // 535;// P9: lxvx, xxswapd, xvcvdpsxds // 536;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 537; return (vector long long) { ptr[3], ptr[2] }; // 538;} // 539;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 540;// P9: sldi 3, lxvx, xvcvdpsxds // 541;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 542; return (vector long long) { arr[elem], arr[elem+1] }; // 543;} // 544;// P8: sldi 3, lxvd2x, xvcvdpsxds // 545;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 546;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 547; return (vector long long) { arr[elem], arr[elem-1] }; // 548;} // 549;// P8: xscvdpsxds, xxspltd // 550;// P9: xscvdpsxds, xxspltd // 551;vector long long spltRegValConvdtoll(double val) { // 552; return (vector long long) val; // 553;} // 554;// P8: lxvdsx, xvcvdpsxds // 555;// P9: lxvdsx, xvcvdpsxds // 556;vector long long spltMemValConvdtoll(double *ptr) { // 557; return (vector long long)*ptr; // 558;} // 559;/*=============================== long long =================================*/ 560;/*========================== unsigned long long =============================*/ 561;// P8: xxlxor // 562;// P9: xxlxor // 563;vector unsigned long long allZeroull() { // 564; return (vector unsigned long long)0; // 565;} // 566;// P8: vspltisb -1 // 567;// P9: xxspltisb 255 // 568;vector unsigned long long allOneull() { // 569; return (vector unsigned long long)-1; // 570;} // 571;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 572;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 573;vector unsigned long long spltConst1ull() { // 574; return (vector unsigned long long)1; // 575;} // 576;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 577;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 578;vector unsigned long long spltConst16kull() { // 579; return (vector unsigned long long)((1<<15) - 1); // 580;} // 581;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 582;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 583;vector unsigned long long spltConst32kull() { // 584; return (vector unsigned long long)((1<<16) - 1); // 585;} // 586;// P8: 2 x mtvsrd, xxmrghd // 587;// P9: mtvsrdd // 588;vector unsigned long long fromRegsull(unsigned long long a, // 589; unsigned long long b) { // 590; return (vector unsigned long long){ a, b }; // 591;} // 592;// P8: lxvd2x, xxswapd // 593;// P9: lxvx (or even lxv) // 594;vector unsigned long long fromDiffConstsull() { // 595; return (vector unsigned long long) { 242, -113 }; // 596;} // 597;// P8: lxvd2x, xxswapd // 598;// P9: lxvx // 599;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 600; return (vector unsigned long long) { arr[0], arr[1] }; // 601;} // 602;// P8: lxvd2x // 603;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 604;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 605; return (vector unsigned long long) { arr[3], arr[2] }; // 606;} // 607;// P8: sldi 3, lxvd2x, xxswapd // 608;// P9: sldi 3, lxvx // 609;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 610; int elem) { // 611; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 612;} // 613;// P8: sldi 3, lxvd2x // 614;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 615;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 616; int elem) { // 617; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 618;} // 619;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 620;// P9: 2 x ld, mtvsrdd // 621;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 622; return (vector unsigned long long) { arr[4], arr[18] }; // 623;} // 624;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 625;// P9: sldi 3, add, 2 x ld, mtvsrdd // 626;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 627; int elem) { // 628; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 629;} // 630;// P8: mtvsrd, xxspltd // 631;// P9: mtvsrdd // 632;vector unsigned long long spltRegValull(unsigned long long val) { // 633; return (vector unsigned long long) val; // 634;} // 635;// P8: lxvdsx // 636;// P9: lxvdsx // 637;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 638; return (vector unsigned long long)*ptr; // 639;} // 640;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 641;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 642;vector unsigned long long spltCnstConvftoull() { // 643; return (vector unsigned long long) 4.74f; // 644;} // 645;// P8: xxmrghd, xvcvdpuxds // 646;// P9: xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromRegsConvftoull(float a, float b) { // 648; return (vector unsigned long long) { a, b }; // 649;} // 650;// P8: lxvd2x, xxswapd // 651;// P9: lxvx (even lxv) // 652;vector unsigned long long fromDiffConstsConvftoull() { // 653; return (vector unsigned long long) { 24.46f, 234.f }; // 654;} // 655;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 656;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 657;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 658; return (vector unsigned long long) { ptr[0], ptr[1] }; // 659;} // 660;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 661;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 662;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 663; return (vector unsigned long long) { ptr[3], ptr[2] }; // 664;} // 665;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 666;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 667;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 668; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 669;} // 670;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 671;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 673; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 674;} // 675;// P8: xscvdpuxds, xxspltd // 676;// P9: xscvdpuxds, xxspltd // 677;vector unsigned long long spltRegValConvftoull(float val) { // 678; return (vector unsigned long long) val; // 679;} // 680;// P8: lxsspx, xscvdpuxds, xxspltd // 681;// P9: lfs, xscvdpuxds, xxspltd // 682;vector unsigned long long spltMemValConvftoull(float *ptr) { // 683; return (vector unsigned long long)*ptr; // 684;} // 685;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 686;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 687;vector unsigned long long spltCnstConvdtoull() { // 688; return (vector unsigned long long) 4.74; // 689;} // 690;// P8: xxmrghd, xvcvdpuxds // 691;// P9: xxmrghd, xvcvdpuxds // 692;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 693; return (vector unsigned long long) { a, b }; // 694;} // 695;// P8: lxvd2x, xxswapd // 696;// P9: lxvx (even lxv) // 697;vector unsigned long long fromDiffConstsConvdtoull() { // 698; return (vector unsigned long long) { 24.46, 234. }; // 699;} // 700;// P8: lxvd2x, xxswapd, xvcvdpuxds // 701;// P9: lxvx, xvcvdpuxds // 702;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 703; return (vector unsigned long long) { ptr[0], ptr[1] }; // 704;} // 705;// P8: lxvd2x, xvcvdpuxds // 706;// P9: lxvx, xxswapd, xvcvdpuxds // 707;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 708; return (vector unsigned long long) { ptr[3], ptr[2] }; // 709;} // 710;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 711;// P9: sldi 3, lxvx, xvcvdpuxds // 712;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 713; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 714;} // 715;// P8: sldi 3, lxvd2x, xvcvdpuxds // 716;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 717;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 718; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 719;} // 720;// P8: xscvdpuxds, xxspltd // 721;// P9: xscvdpuxds, xxspltd // 722;vector unsigned long long spltRegValConvdtoull(double val) { // 723; return (vector unsigned long long) val; // 724;} // 725;// P8: lxvdsx, xvcvdpuxds // 726;// P9: lxvdsx, xvcvdpuxds // 727;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 728; return (vector unsigned long long)*ptr; // 729;} // 730;/*========================== unsigned long long ==============================*/ 731 732; Function Attrs: norecurse nounwind readnone 733define <4 x i32> @allZeroi() { 734; P9BE-LABEL: allZeroi: 735; P9BE: # %bb.0: # %entry 736; P9BE-NEXT: xxlxor v2, v2, v2 737; P9BE-NEXT: blr 738; 739; P9LE-LABEL: allZeroi: 740; P9LE: # %bb.0: # %entry 741; P9LE-NEXT: xxlxor v2, v2, v2 742; P9LE-NEXT: blr 743; 744; P8BE-LABEL: allZeroi: 745; P8BE: # %bb.0: # %entry 746; P8BE-NEXT: xxlxor v2, v2, v2 747; P8BE-NEXT: blr 748; 749; P8LE-LABEL: allZeroi: 750; P8LE: # %bb.0: # %entry 751; P8LE-NEXT: xxlxor v2, v2, v2 752; P8LE-NEXT: blr 753entry: 754 ret <4 x i32> zeroinitializer 755} 756 757; Function Attrs: norecurse nounwind readnone 758define <4 x i32> @allOnei() { 759; P9BE-LABEL: allOnei: 760; P9BE: # %bb.0: # %entry 761; P9BE-NEXT: xxspltib v2, 255 762; P9BE-NEXT: blr 763; 764; P9LE-LABEL: allOnei: 765; P9LE: # %bb.0: # %entry 766; P9LE-NEXT: xxspltib v2, 255 767; P9LE-NEXT: blr 768; 769; P8BE-LABEL: allOnei: 770; P8BE: # %bb.0: # %entry 771; P8BE-NEXT: vspltisb v2, -1 772; P8BE-NEXT: blr 773; 774; P8LE-LABEL: allOnei: 775; P8LE: # %bb.0: # %entry 776; P8LE-NEXT: vspltisb v2, -1 777; P8LE-NEXT: blr 778entry: 779 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 780} 781 782; Function Attrs: norecurse nounwind readnone 783define <4 x i32> @spltConst1i() { 784; P9BE-LABEL: spltConst1i: 785; P9BE: # %bb.0: # %entry 786; P9BE-NEXT: vspltisw v2, 1 787; P9BE-NEXT: blr 788; 789; P9LE-LABEL: spltConst1i: 790; P9LE: # %bb.0: # %entry 791; P9LE-NEXT: vspltisw v2, 1 792; P9LE-NEXT: blr 793; 794; P8BE-LABEL: spltConst1i: 795; P8BE: # %bb.0: # %entry 796; P8BE-NEXT: vspltisw v2, 1 797; P8BE-NEXT: blr 798; 799; P8LE-LABEL: spltConst1i: 800; P8LE: # %bb.0: # %entry 801; P8LE-NEXT: vspltisw v2, 1 802; P8LE-NEXT: blr 803entry: 804 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 805} 806 807; Function Attrs: norecurse nounwind readnone 808define <4 x i32> @spltConst16ki() { 809; P9BE-LABEL: spltConst16ki: 810; P9BE: # %bb.0: # %entry 811; P9BE-NEXT: vspltisw v2, -15 812; P9BE-NEXT: vsrw v2, v2, v2 813; P9BE-NEXT: blr 814; 815; P9LE-LABEL: spltConst16ki: 816; P9LE: # %bb.0: # %entry 817; P9LE-NEXT: vspltisw v2, -15 818; P9LE-NEXT: vsrw v2, v2, v2 819; P9LE-NEXT: blr 820; 821; P8BE-LABEL: spltConst16ki: 822; P8BE: # %bb.0: # %entry 823; P8BE-NEXT: vspltisw v2, -15 824; P8BE-NEXT: vsrw v2, v2, v2 825; P8BE-NEXT: blr 826; 827; P8LE-LABEL: spltConst16ki: 828; P8LE: # %bb.0: # %entry 829; P8LE-NEXT: vspltisw v2, -15 830; P8LE-NEXT: vsrw v2, v2, v2 831; P8LE-NEXT: blr 832entry: 833 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 834} 835 836; Function Attrs: norecurse nounwind readnone 837define <4 x i32> @spltConst32ki() { 838; P9BE-LABEL: spltConst32ki: 839; P9BE: # %bb.0: # %entry 840; P9BE-NEXT: vspltisw v2, -16 841; P9BE-NEXT: vsrw v2, v2, v2 842; P9BE-NEXT: blr 843; 844; P9LE-LABEL: spltConst32ki: 845; P9LE: # %bb.0: # %entry 846; P9LE-NEXT: vspltisw v2, -16 847; P9LE-NEXT: vsrw v2, v2, v2 848; P9LE-NEXT: blr 849; 850; P8BE-LABEL: spltConst32ki: 851; P8BE: # %bb.0: # %entry 852; P8BE-NEXT: vspltisw v2, -16 853; P8BE-NEXT: vsrw v2, v2, v2 854; P8BE-NEXT: blr 855; 856; P8LE-LABEL: spltConst32ki: 857; P8LE: # %bb.0: # %entry 858; P8LE-NEXT: vspltisw v2, -16 859; P8LE-NEXT: vsrw v2, v2, v2 860; P8LE-NEXT: blr 861entry: 862 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 863} 864 865; Function Attrs: norecurse nounwind readnone 866define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 867; P9BE-LABEL: fromRegsi: 868; P9BE: # %bb.0: # %entry 869; P9BE-NEXT: rldimi r6, r5, 32, 0 870; P9BE-NEXT: rldimi r4, r3, 32, 0 871; P9BE-NEXT: mtvsrdd v2, r4, r6 872; P9BE-NEXT: blr 873; 874; P9LE-LABEL: fromRegsi: 875; P9LE: # %bb.0: # %entry 876; P9LE-NEXT: rldimi r3, r4, 32, 0 877; P9LE-NEXT: rldimi r5, r6, 32, 0 878; P9LE-NEXT: mtvsrdd v2, r5, r3 879; P9LE-NEXT: blr 880; 881; P8BE-LABEL: fromRegsi: 882; P8BE: # %bb.0: # %entry 883; P8BE-NEXT: rldimi r6, r5, 32, 0 884; P8BE-NEXT: rldimi r4, r3, 32, 0 885; P8BE-NEXT: mtvsrd f0, r6 886; P8BE-NEXT: mtvsrd f1, r4 887; P8BE-NEXT: xxmrghd v2, vs1, vs0 888; P8BE-NEXT: blr 889; 890; P8LE-LABEL: fromRegsi: 891; P8LE: # %bb.0: # %entry 892; P8LE-NEXT: rldimi r3, r4, 32, 0 893; P8LE-NEXT: rldimi r5, r6, 32, 0 894; P8LE-NEXT: mtvsrd f0, r3 895; P8LE-NEXT: mtvsrd f1, r5 896; P8LE-NEXT: xxmrghd v2, vs1, vs0 897; P8LE-NEXT: blr 898entry: 899 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 900 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 901 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 902 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 903 ret <4 x i32> %vecinit3 904} 905 906; Function Attrs: norecurse nounwind readnone 907define <4 x i32> @fromDiffConstsi() { 908; P9BE-LABEL: fromDiffConstsi: 909; P9BE: # %bb.0: # %entry 910; P9BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 911; P9BE-NEXT: addi r3, r3, .LCPI6_0@toc@l 912; P9BE-NEXT: lxvx v2, 0, r3 913; P9BE-NEXT: blr 914; 915; P9LE-LABEL: fromDiffConstsi: 916; P9LE: # %bb.0: # %entry 917; P9LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 918; P9LE-NEXT: addi r3, r3, .LCPI6_0@toc@l 919; P9LE-NEXT: lxvx v2, 0, r3 920; P9LE-NEXT: blr 921; 922; P8BE-LABEL: fromDiffConstsi: 923; P8BE: # %bb.0: # %entry 924; P8BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 925; P8BE-NEXT: addi r3, r3, .LCPI6_0@toc@l 926; P8BE-NEXT: lxvw4x v2, 0, r3 927; P8BE-NEXT: blr 928; 929; P8LE-LABEL: fromDiffConstsi: 930; P8LE: # %bb.0: # %entry 931; P8LE-NEXT: addis r3, r2, .LCPI6_0@toc@ha 932; P8LE-NEXT: addi r3, r3, .LCPI6_0@toc@l 933; P8LE-NEXT: lvx v2, 0, r3 934; P8LE-NEXT: blr 935entry: 936 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 937} 938 939; Function Attrs: norecurse nounwind readonly 940define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 941; P9BE-LABEL: fromDiffMemConsAi: 942; P9BE: # %bb.0: # %entry 943; P9BE-NEXT: lxv v2, 0(r3) 944; P9BE-NEXT: blr 945; 946; P9LE-LABEL: fromDiffMemConsAi: 947; P9LE: # %bb.0: # %entry 948; P9LE-NEXT: lxv v2, 0(r3) 949; P9LE-NEXT: blr 950; 951; P8BE-LABEL: fromDiffMemConsAi: 952; P8BE: # %bb.0: # %entry 953; P8BE-NEXT: lxvw4x v2, 0, r3 954; P8BE-NEXT: blr 955; 956; P8LE-LABEL: fromDiffMemConsAi: 957; P8LE: # %bb.0: # %entry 958; P8LE-NEXT: lxvd2x vs0, 0, r3 959; P8LE-NEXT: xxswapd v2, vs0 960; P8LE-NEXT: blr 961entry: 962 %0 = load i32, i32* %arr, align 4 963 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 964 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 965 %1 = load i32, i32* %arrayidx1, align 4 966 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 967 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 968 %2 = load i32, i32* %arrayidx3, align 4 969 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 970 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 971 %3 = load i32, i32* %arrayidx5, align 4 972 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 973 ret <4 x i32> %vecinit6 974} 975 976; Function Attrs: norecurse nounwind readonly 977define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 978; P9BE-LABEL: fromDiffMemConsDi: 979; P9BE: # %bb.0: # %entry 980; P9BE-NEXT: lxv v2, 0(r3) 981; P9BE-NEXT: addis r3, r2, .LCPI8_0@toc@ha 982; P9BE-NEXT: addi r3, r3, .LCPI8_0@toc@l 983; P9BE-NEXT: lxvx v3, 0, r3 984; P9BE-NEXT: vperm v2, v2, v2, v3 985; P9BE-NEXT: blr 986; 987; P9LE-LABEL: fromDiffMemConsDi: 988; P9LE: # %bb.0: # %entry 989; P9LE-NEXT: lxvw4x v2, 0, r3 990; P9LE-NEXT: blr 991; 992; P8BE-LABEL: fromDiffMemConsDi: 993; P8BE: # %bb.0: # %entry 994; P8BE-NEXT: addis r4, r2, .LCPI8_0@toc@ha 995; P8BE-NEXT: lxvw4x v2, 0, r3 996; P8BE-NEXT: addi r4, r4, .LCPI8_0@toc@l 997; P8BE-NEXT: lxvw4x v3, 0, r4 998; P8BE-NEXT: vperm v2, v2, v2, v3 999; P8BE-NEXT: blr 1000; 1001; P8LE-LABEL: fromDiffMemConsDi: 1002; P8LE: # %bb.0: # %entry 1003; P8LE-NEXT: lxvw4x v2, 0, r3 1004; P8LE-NEXT: blr 1005entry: 1006 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 1007 %0 = load i32, i32* %arrayidx, align 4 1008 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1009 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 1010 %1 = load i32, i32* %arrayidx1, align 4 1011 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1012 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 1013 %2 = load i32, i32* %arrayidx3, align 4 1014 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1015 %3 = load i32, i32* %arr, align 4 1016 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1017 ret <4 x i32> %vecinit6 1018} 1019 1020; Function Attrs: norecurse nounwind readonly 1021define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 1022; P9BE-LABEL: fromDiffMemVarAi: 1023; P9BE: # %bb.0: # %entry 1024; P9BE-NEXT: sldi r4, r4, 2 1025; P9BE-NEXT: lxvx v2, r3, r4 1026; P9BE-NEXT: blr 1027; 1028; P9LE-LABEL: fromDiffMemVarAi: 1029; P9LE: # %bb.0: # %entry 1030; P9LE-NEXT: sldi r4, r4, 2 1031; P9LE-NEXT: lxvx v2, r3, r4 1032; P9LE-NEXT: blr 1033; 1034; P8BE-LABEL: fromDiffMemVarAi: 1035; P8BE: # %bb.0: # %entry 1036; P8BE-NEXT: sldi r4, r4, 2 1037; P8BE-NEXT: lxvw4x v2, r3, r4 1038; P8BE-NEXT: blr 1039; 1040; P8LE-LABEL: fromDiffMemVarAi: 1041; P8LE: # %bb.0: # %entry 1042; P8LE-NEXT: sldi r4, r4, 2 1043; P8LE-NEXT: lxvd2x vs0, r3, r4 1044; P8LE-NEXT: xxswapd v2, vs0 1045; P8LE-NEXT: blr 1046entry: 1047 %idxprom = sext i32 %elem to i64 1048 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1049 %0 = load i32, i32* %arrayidx, align 4 1050 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1051 %add = add nsw i32 %elem, 1 1052 %idxprom1 = sext i32 %add to i64 1053 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1054 %1 = load i32, i32* %arrayidx2, align 4 1055 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1056 %add4 = add nsw i32 %elem, 2 1057 %idxprom5 = sext i32 %add4 to i64 1058 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1059 %2 = load i32, i32* %arrayidx6, align 4 1060 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1061 %add8 = add nsw i32 %elem, 3 1062 %idxprom9 = sext i32 %add8 to i64 1063 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1064 %3 = load i32, i32* %arrayidx10, align 4 1065 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1066 ret <4 x i32> %vecinit11 1067} 1068 1069; Function Attrs: norecurse nounwind readonly 1070define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1071; P9BE-LABEL: fromDiffMemVarDi: 1072; P9BE: # %bb.0: # %entry 1073; P9BE-NEXT: sldi r4, r4, 2 1074; P9BE-NEXT: add r3, r3, r4 1075; P9BE-NEXT: addi r3, r3, -12 1076; P9BE-NEXT: lxvx v2, 0, r3 1077; P9BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha 1078; P9BE-NEXT: addi r3, r3, .LCPI10_0@toc@l 1079; P9BE-NEXT: lxvx v3, 0, r3 1080; P9BE-NEXT: vperm v2, v2, v2, v3 1081; P9BE-NEXT: blr 1082; 1083; P9LE-LABEL: fromDiffMemVarDi: 1084; P9LE: # %bb.0: # %entry 1085; P9LE-NEXT: sldi r4, r4, 2 1086; P9LE-NEXT: add r3, r3, r4 1087; P9LE-NEXT: addi r3, r3, -12 1088; P9LE-NEXT: lxvx v2, 0, r3 1089; P9LE-NEXT: addis r3, r2, .LCPI10_0@toc@ha 1090; P9LE-NEXT: addi r3, r3, .LCPI10_0@toc@l 1091; P9LE-NEXT: lxvx v3, 0, r3 1092; P9LE-NEXT: vperm v2, v2, v2, v3 1093; P9LE-NEXT: blr 1094; 1095; P8BE-LABEL: fromDiffMemVarDi: 1096; P8BE: # %bb.0: # %entry 1097; P8BE-NEXT: sldi r4, r4, 2 1098; P8BE-NEXT: addis r5, r2, .LCPI10_0@toc@ha 1099; P8BE-NEXT: add r3, r3, r4 1100; P8BE-NEXT: addi r4, r5, .LCPI10_0@toc@l 1101; P8BE-NEXT: addi r3, r3, -12 1102; P8BE-NEXT: lxvw4x v3, 0, r4 1103; P8BE-NEXT: lxvw4x v2, 0, r3 1104; P8BE-NEXT: vperm v2, v2, v2, v3 1105; P8BE-NEXT: blr 1106; 1107; P8LE-LABEL: fromDiffMemVarDi: 1108; P8LE: # %bb.0: # %entry 1109; P8LE-NEXT: sldi r4, r4, 2 1110; P8LE-NEXT: addis r5, r2, .LCPI10_0@toc@ha 1111; P8LE-NEXT: add r3, r3, r4 1112; P8LE-NEXT: addi r3, r3, -12 1113; P8LE-NEXT: lxvd2x vs0, 0, r3 1114; P8LE-NEXT: addi r3, r5, .LCPI10_0@toc@l 1115; P8LE-NEXT: lvx v3, 0, r3 1116; P8LE-NEXT: xxswapd v2, vs0 1117; P8LE-NEXT: vperm v2, v2, v2, v3 1118; P8LE-NEXT: blr 1119entry: 1120 %idxprom = sext i32 %elem to i64 1121 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1122 %0 = load i32, i32* %arrayidx, align 4 1123 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1124 %sub = add nsw i32 %elem, -1 1125 %idxprom1 = sext i32 %sub to i64 1126 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1127 %1 = load i32, i32* %arrayidx2, align 4 1128 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1129 %sub4 = add nsw i32 %elem, -2 1130 %idxprom5 = sext i32 %sub4 to i64 1131 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1132 %2 = load i32, i32* %arrayidx6, align 4 1133 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1134 %sub8 = add nsw i32 %elem, -3 1135 %idxprom9 = sext i32 %sub8 to i64 1136 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1137 %3 = load i32, i32* %arrayidx10, align 4 1138 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1139 ret <4 x i32> %vecinit11 1140} 1141 1142; Function Attrs: norecurse nounwind readonly 1143define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1144; P9BE-LABEL: fromRandMemConsi: 1145; P9BE: # %bb.0: # %entry 1146; P9BE-NEXT: lwz r4, 16(r3) 1147; P9BE-NEXT: lwz r5, 72(r3) 1148; P9BE-NEXT: lwz r6, 8(r3) 1149; P9BE-NEXT: lwz r3, 352(r3) 1150; P9BE-NEXT: rldimi r3, r6, 32, 0 1151; P9BE-NEXT: rldimi r5, r4, 32, 0 1152; P9BE-NEXT: mtvsrdd v2, r5, r3 1153; P9BE-NEXT: blr 1154; 1155; P9LE-LABEL: fromRandMemConsi: 1156; P9LE: # %bb.0: # %entry 1157; P9LE-NEXT: lwz r4, 16(r3) 1158; P9LE-NEXT: lwz r5, 72(r3) 1159; P9LE-NEXT: lwz r6, 8(r3) 1160; P9LE-NEXT: lwz r3, 352(r3) 1161; P9LE-NEXT: rldimi r4, r5, 32, 0 1162; P9LE-NEXT: rldimi r6, r3, 32, 0 1163; P9LE-NEXT: mtvsrdd v2, r6, r4 1164; P9LE-NEXT: blr 1165; 1166; P8BE-LABEL: fromRandMemConsi: 1167; P8BE: # %bb.0: # %entry 1168; P8BE-NEXT: lwz r4, 8(r3) 1169; P8BE-NEXT: lwz r5, 352(r3) 1170; P8BE-NEXT: lwz r6, 16(r3) 1171; P8BE-NEXT: lwz r3, 72(r3) 1172; P8BE-NEXT: rldimi r5, r4, 32, 0 1173; P8BE-NEXT: rldimi r3, r6, 32, 0 1174; P8BE-NEXT: mtvsrd f0, r5 1175; P8BE-NEXT: mtvsrd f1, r3 1176; P8BE-NEXT: xxmrghd v2, vs1, vs0 1177; P8BE-NEXT: blr 1178; 1179; P8LE-LABEL: fromRandMemConsi: 1180; P8LE: # %bb.0: # %entry 1181; P8LE-NEXT: lwz r4, 16(r3) 1182; P8LE-NEXT: lwz r5, 72(r3) 1183; P8LE-NEXT: lwz r6, 8(r3) 1184; P8LE-NEXT: lwz r3, 352(r3) 1185; P8LE-NEXT: rldimi r4, r5, 32, 0 1186; P8LE-NEXT: rldimi r6, r3, 32, 0 1187; P8LE-NEXT: mtvsrd f0, r4 1188; P8LE-NEXT: mtvsrd f1, r6 1189; P8LE-NEXT: xxmrghd v2, vs1, vs0 1190; P8LE-NEXT: blr 1191entry: 1192 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1193 %0 = load i32, i32* %arrayidx, align 4 1194 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1195 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1196 %1 = load i32, i32* %arrayidx1, align 4 1197 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1198 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1199 %2 = load i32, i32* %arrayidx3, align 4 1200 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1201 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1202 %3 = load i32, i32* %arrayidx5, align 4 1203 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1204 ret <4 x i32> %vecinit6 1205} 1206 1207; Function Attrs: norecurse nounwind readonly 1208define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1209; P9BE-LABEL: fromRandMemVari: 1210; P9BE: # %bb.0: # %entry 1211; P9BE-NEXT: sldi r4, r4, 2 1212; P9BE-NEXT: add r3, r3, r4 1213; P9BE-NEXT: lwz r4, 16(r3) 1214; P9BE-NEXT: lwz r5, 4(r3) 1215; P9BE-NEXT: lwz r6, 8(r3) 1216; P9BE-NEXT: lwz r3, 32(r3) 1217; P9BE-NEXT: rldimi r3, r6, 32, 0 1218; P9BE-NEXT: rldimi r5, r4, 32, 0 1219; P9BE-NEXT: mtvsrdd v2, r5, r3 1220; P9BE-NEXT: blr 1221; 1222; P9LE-LABEL: fromRandMemVari: 1223; P9LE: # %bb.0: # %entry 1224; P9LE-NEXT: sldi r4, r4, 2 1225; P9LE-NEXT: add r3, r3, r4 1226; P9LE-NEXT: lwz r4, 16(r3) 1227; P9LE-NEXT: lwz r5, 4(r3) 1228; P9LE-NEXT: lwz r6, 8(r3) 1229; P9LE-NEXT: lwz r3, 32(r3) 1230; P9LE-NEXT: rldimi r4, r5, 32, 0 1231; P9LE-NEXT: rldimi r6, r3, 32, 0 1232; P9LE-NEXT: mtvsrdd v2, r6, r4 1233; P9LE-NEXT: blr 1234; 1235; P8BE-LABEL: fromRandMemVari: 1236; P8BE: # %bb.0: # %entry 1237; P8BE-NEXT: sldi r4, r4, 2 1238; P8BE-NEXT: add r3, r3, r4 1239; P8BE-NEXT: lwz r4, 8(r3) 1240; P8BE-NEXT: lwz r5, 32(r3) 1241; P8BE-NEXT: lwz r6, 16(r3) 1242; P8BE-NEXT: lwz r3, 4(r3) 1243; P8BE-NEXT: rldimi r5, r4, 32, 0 1244; P8BE-NEXT: rldimi r3, r6, 32, 0 1245; P8BE-NEXT: mtvsrd f0, r5 1246; P8BE-NEXT: mtvsrd f1, r3 1247; P8BE-NEXT: xxmrghd v2, vs1, vs0 1248; P8BE-NEXT: blr 1249; 1250; P8LE-LABEL: fromRandMemVari: 1251; P8LE: # %bb.0: # %entry 1252; P8LE-NEXT: sldi r4, r4, 2 1253; P8LE-NEXT: add r3, r3, r4 1254; P8LE-NEXT: lwz r4, 16(r3) 1255; P8LE-NEXT: lwz r5, 4(r3) 1256; P8LE-NEXT: lwz r6, 8(r3) 1257; P8LE-NEXT: lwz r3, 32(r3) 1258; P8LE-NEXT: rldimi r4, r5, 32, 0 1259; P8LE-NEXT: rldimi r6, r3, 32, 0 1260; P8LE-NEXT: mtvsrd f0, r4 1261; P8LE-NEXT: mtvsrd f1, r6 1262; P8LE-NEXT: xxmrghd v2, vs1, vs0 1263; P8LE-NEXT: blr 1264entry: 1265 %add = add nsw i32 %elem, 4 1266 %idxprom = sext i32 %add to i64 1267 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1268 %0 = load i32, i32* %arrayidx, align 4 1269 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1270 %add1 = add nsw i32 %elem, 1 1271 %idxprom2 = sext i32 %add1 to i64 1272 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1273 %1 = load i32, i32* %arrayidx3, align 4 1274 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1275 %add5 = add nsw i32 %elem, 2 1276 %idxprom6 = sext i32 %add5 to i64 1277 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1278 %2 = load i32, i32* %arrayidx7, align 4 1279 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1280 %add9 = add nsw i32 %elem, 8 1281 %idxprom10 = sext i32 %add9 to i64 1282 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1283 %3 = load i32, i32* %arrayidx11, align 4 1284 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1285 ret <4 x i32> %vecinit12 1286} 1287 1288; Function Attrs: norecurse nounwind readnone 1289define <4 x i32> @spltRegVali(i32 signext %val) { 1290; P9BE-LABEL: spltRegVali: 1291; P9BE: # %bb.0: # %entry 1292; P9BE-NEXT: mtvsrws v2, r3 1293; P9BE-NEXT: blr 1294; 1295; P9LE-LABEL: spltRegVali: 1296; P9LE: # %bb.0: # %entry 1297; P9LE-NEXT: mtvsrws v2, r3 1298; P9LE-NEXT: blr 1299; 1300; P8BE-LABEL: spltRegVali: 1301; P8BE: # %bb.0: # %entry 1302; P8BE-NEXT: mtvsrwz f0, r3 1303; P8BE-NEXT: xxspltw v2, vs0, 1 1304; P8BE-NEXT: blr 1305; 1306; P8LE-LABEL: spltRegVali: 1307; P8LE: # %bb.0: # %entry 1308; P8LE-NEXT: mtvsrwz f0, r3 1309; P8LE-NEXT: xxspltw v2, vs0, 1 1310; P8LE-NEXT: blr 1311entry: 1312 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1313 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1314 ret <4 x i32> %splat.splat 1315} 1316 1317; Function Attrs: norecurse nounwind readonly 1318define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1319; P9BE-LABEL: spltMemVali: 1320; P9BE: # %bb.0: # %entry 1321; P9BE-NEXT: lfiwzx f0, 0, r3 1322; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 1323; P9BE-NEXT: xxspltw v2, vs0, 0 1324; P9BE-NEXT: blr 1325; 1326; P9LE-LABEL: spltMemVali: 1327; P9LE: # %bb.0: # %entry 1328; P9LE-NEXT: lfiwzx f0, 0, r3 1329; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 1330; P9LE-NEXT: xxspltw v2, vs0, 3 1331; P9LE-NEXT: blr 1332; 1333; P8BE-LABEL: spltMemVali: 1334; P8BE: # %bb.0: # %entry 1335; P8BE-NEXT: lfiwzx f0, 0, r3 1336; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 1337; P8BE-NEXT: xxspltw v2, vs0, 0 1338; P8BE-NEXT: blr 1339; 1340; P8LE-LABEL: spltMemVali: 1341; P8LE: # %bb.0: # %entry 1342; P8LE-NEXT: lfiwzx f0, 0, r3 1343; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 1344; P8LE-NEXT: xxspltw v2, vs0, 3 1345; P8LE-NEXT: blr 1346entry: 1347 %0 = load i32, i32* %ptr, align 4 1348 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1349 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1350 ret <4 x i32> %splat.splat 1351} 1352 1353; Function Attrs: norecurse nounwind readnone 1354define <4 x i32> @spltCnstConvftoi() { 1355; P9BE-LABEL: spltCnstConvftoi: 1356; P9BE: # %bb.0: # %entry 1357; P9BE-NEXT: vspltisw v2, 4 1358; P9BE-NEXT: blr 1359; 1360; P9LE-LABEL: spltCnstConvftoi: 1361; P9LE: # %bb.0: # %entry 1362; P9LE-NEXT: vspltisw v2, 4 1363; P9LE-NEXT: blr 1364; 1365; P8BE-LABEL: spltCnstConvftoi: 1366; P8BE: # %bb.0: # %entry 1367; P8BE-NEXT: vspltisw v2, 4 1368; P8BE-NEXT: blr 1369; 1370; P8LE-LABEL: spltCnstConvftoi: 1371; P8LE: # %bb.0: # %entry 1372; P8LE-NEXT: vspltisw v2, 4 1373; P8LE-NEXT: blr 1374entry: 1375 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1376} 1377 1378; Function Attrs: norecurse nounwind readnone 1379define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1380; P9BE-LABEL: fromRegsConvftoi: 1381; P9BE: # %bb.0: # %entry 1382; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1383; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1384; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1385; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1386; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1387; P9BE-NEXT: xvcvdpsxws v2, vs0 1388; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1389; P9BE-NEXT: xvcvdpsxws v3, vs0 1390; P9BE-NEXT: vmrgew v2, v3, v2 1391; P9BE-NEXT: blr 1392; 1393; P9LE-LABEL: fromRegsConvftoi: 1394; P9LE: # %bb.0: # %entry 1395; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1396; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1397; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1398; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1399; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1400; P9LE-NEXT: xvcvdpsxws v2, vs0 1401; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1402; P9LE-NEXT: xvcvdpsxws v3, vs0 1403; P9LE-NEXT: vmrgew v2, v3, v2 1404; P9LE-NEXT: blr 1405; 1406; P8BE-LABEL: fromRegsConvftoi: 1407; P8BE: # %bb.0: # %entry 1408; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1409; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1410; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1411; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1412; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1413; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1414; P8BE-NEXT: xvcvdpsxws v2, vs0 1415; P8BE-NEXT: xvcvdpsxws v3, vs1 1416; P8BE-NEXT: vmrgew v2, v3, v2 1417; P8BE-NEXT: blr 1418; 1419; P8LE-LABEL: fromRegsConvftoi: 1420; P8LE: # %bb.0: # %entry 1421; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1422; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1423; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1424; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1425; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1426; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1427; P8LE-NEXT: xvcvdpsxws v2, vs0 1428; P8LE-NEXT: xvcvdpsxws v3, vs1 1429; P8LE-NEXT: vmrgew v2, v3, v2 1430; P8LE-NEXT: blr 1431entry: 1432 %conv = fptosi float %a to i32 1433 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1434 %conv1 = fptosi float %b to i32 1435 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1436 %conv3 = fptosi float %c to i32 1437 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1438 %conv5 = fptosi float %d to i32 1439 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1440 ret <4 x i32> %vecinit6 1441} 1442 1443; Function Attrs: norecurse nounwind readnone 1444define <4 x i32> @fromDiffConstsConvftoi() { 1445; P9BE-LABEL: fromDiffConstsConvftoi: 1446; P9BE: # %bb.0: # %entry 1447; P9BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1448; P9BE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1449; P9BE-NEXT: lxvx v2, 0, r3 1450; P9BE-NEXT: blr 1451; 1452; P9LE-LABEL: fromDiffConstsConvftoi: 1453; P9LE: # %bb.0: # %entry 1454; P9LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1455; P9LE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1456; P9LE-NEXT: lxvx v2, 0, r3 1457; P9LE-NEXT: blr 1458; 1459; P8BE-LABEL: fromDiffConstsConvftoi: 1460; P8BE: # %bb.0: # %entry 1461; P8BE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1462; P8BE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1463; P8BE-NEXT: lxvw4x v2, 0, r3 1464; P8BE-NEXT: blr 1465; 1466; P8LE-LABEL: fromDiffConstsConvftoi: 1467; P8LE: # %bb.0: # %entry 1468; P8LE-NEXT: addis r3, r2, .LCPI17_0@toc@ha 1469; P8LE-NEXT: addi r3, r3, .LCPI17_0@toc@l 1470; P8LE-NEXT: lvx v2, 0, r3 1471; P8LE-NEXT: blr 1472entry: 1473 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1474} 1475 1476; Function Attrs: norecurse nounwind readonly 1477define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1478; P9BE-LABEL: fromDiffMemConsAConvftoi: 1479; P9BE: # %bb.0: # %entry 1480; P9BE-NEXT: lxv vs0, 0(r3) 1481; P9BE-NEXT: xvcvspsxws v2, vs0 1482; P9BE-NEXT: blr 1483; 1484; P9LE-LABEL: fromDiffMemConsAConvftoi: 1485; P9LE: # %bb.0: # %entry 1486; P9LE-NEXT: lxv vs0, 0(r3) 1487; P9LE-NEXT: xvcvspsxws v2, vs0 1488; P9LE-NEXT: blr 1489; 1490; P8BE-LABEL: fromDiffMemConsAConvftoi: 1491; P8BE: # %bb.0: # %entry 1492; P8BE-NEXT: lxvw4x vs0, 0, r3 1493; P8BE-NEXT: xvcvspsxws v2, vs0 1494; P8BE-NEXT: blr 1495; 1496; P8LE-LABEL: fromDiffMemConsAConvftoi: 1497; P8LE: # %bb.0: # %entry 1498; P8LE-NEXT: lxvd2x vs0, 0, r3 1499; P8LE-NEXT: xxswapd v2, vs0 1500; P8LE-NEXT: xvcvspsxws v2, v2 1501; P8LE-NEXT: blr 1502entry: 1503 %0 = bitcast float* %ptr to <4 x float>* 1504 %1 = load <4 x float>, <4 x float>* %0, align 4 1505 %2 = fptosi <4 x float> %1 to <4 x i32> 1506 ret <4 x i32> %2 1507} 1508 1509; Function Attrs: norecurse nounwind readonly 1510define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1511; P9BE-LABEL: fromDiffMemConsDConvftoi: 1512; P9BE: # %bb.0: # %entry 1513; P9BE-NEXT: lxv v2, 0(r3) 1514; P9BE-NEXT: addis r3, r2, .LCPI19_0@toc@ha 1515; P9BE-NEXT: addi r3, r3, .LCPI19_0@toc@l 1516; P9BE-NEXT: lxvx v3, 0, r3 1517; P9BE-NEXT: vperm v2, v2, v2, v3 1518; P9BE-NEXT: xvcvspsxws v2, v2 1519; P9BE-NEXT: blr 1520; 1521; P9LE-LABEL: fromDiffMemConsDConvftoi: 1522; P9LE: # %bb.0: # %entry 1523; P9LE-NEXT: lxv v2, 0(r3) 1524; P9LE-NEXT: addis r3, r2, .LCPI19_0@toc@ha 1525; P9LE-NEXT: addi r3, r3, .LCPI19_0@toc@l 1526; P9LE-NEXT: lxvx v3, 0, r3 1527; P9LE-NEXT: vperm v2, v2, v2, v3 1528; P9LE-NEXT: xvcvspsxws v2, v2 1529; P9LE-NEXT: blr 1530; 1531; P8BE-LABEL: fromDiffMemConsDConvftoi: 1532; P8BE: # %bb.0: # %entry 1533; P8BE-NEXT: addis r4, r2, .LCPI19_0@toc@ha 1534; P8BE-NEXT: lxvw4x v2, 0, r3 1535; P8BE-NEXT: addi r4, r4, .LCPI19_0@toc@l 1536; P8BE-NEXT: lxvw4x v3, 0, r4 1537; P8BE-NEXT: vperm v2, v2, v2, v3 1538; P8BE-NEXT: xvcvspsxws v2, v2 1539; P8BE-NEXT: blr 1540; 1541; P8LE-LABEL: fromDiffMemConsDConvftoi: 1542; P8LE: # %bb.0: # %entry 1543; P8LE-NEXT: lxvd2x vs0, 0, r3 1544; P8LE-NEXT: addis r4, r2, .LCPI19_0@toc@ha 1545; P8LE-NEXT: addi r3, r4, .LCPI19_0@toc@l 1546; P8LE-NEXT: lvx v2, 0, r3 1547; P8LE-NEXT: xxswapd v3, vs0 1548; P8LE-NEXT: vperm v2, v3, v3, v2 1549; P8LE-NEXT: xvcvspsxws v2, v2 1550; P8LE-NEXT: blr 1551entry: 1552 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1553 %0 = load float, float* %arrayidx, align 4 1554 %conv = fptosi float %0 to i32 1555 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1556 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1557 %1 = load float, float* %arrayidx1, align 4 1558 %conv2 = fptosi float %1 to i32 1559 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1560 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1561 %2 = load float, float* %arrayidx4, align 4 1562 %conv5 = fptosi float %2 to i32 1563 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1564 %3 = load float, float* %ptr, align 4 1565 %conv8 = fptosi float %3 to i32 1566 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1567 ret <4 x i32> %vecinit9 1568} 1569 1570; Function Attrs: norecurse nounwind readonly 1571define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1572; P9BE-LABEL: fromDiffMemVarAConvftoi: 1573; P9BE: # %bb.0: # %entry 1574; P9BE-NEXT: sldi r4, r4, 2 1575; P9BE-NEXT: lfsux f0, r3, r4 1576; P9BE-NEXT: lfs f1, 12(r3) 1577; P9BE-NEXT: lfs f2, 4(r3) 1578; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1579; P9BE-NEXT: xvcvdpsp v2, vs1 1580; P9BE-NEXT: lfs f1, 8(r3) 1581; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1582; P9BE-NEXT: xvcvdpsp v3, vs0 1583; P9BE-NEXT: vmrgew v2, v3, v2 1584; P9BE-NEXT: xvcvspsxws v2, v2 1585; P9BE-NEXT: blr 1586; 1587; P9LE-LABEL: fromDiffMemVarAConvftoi: 1588; P9LE: # %bb.0: # %entry 1589; P9LE-NEXT: sldi r4, r4, 2 1590; P9LE-NEXT: lfsux f0, r3, r4 1591; P9LE-NEXT: lfs f1, 8(r3) 1592; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1593; P9LE-NEXT: lfs f1, 12(r3) 1594; P9LE-NEXT: xvcvdpsp v2, vs0 1595; P9LE-NEXT: lfs f0, 4(r3) 1596; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1597; P9LE-NEXT: xvcvdpsp v3, vs0 1598; P9LE-NEXT: vmrgew v2, v3, v2 1599; P9LE-NEXT: xvcvspsxws v2, v2 1600; P9LE-NEXT: blr 1601; 1602; P8BE-LABEL: fromDiffMemVarAConvftoi: 1603; P8BE: # %bb.0: # %entry 1604; P8BE-NEXT: sldi r4, r4, 2 1605; P8BE-NEXT: lfsux f0, r3, r4 1606; P8BE-NEXT: lfs f1, 12(r3) 1607; P8BE-NEXT: lfs f2, 4(r3) 1608; P8BE-NEXT: lfs f3, 8(r3) 1609; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1610; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1611; P8BE-NEXT: xvcvdpsp v2, vs1 1612; P8BE-NEXT: xvcvdpsp v3, vs0 1613; P8BE-NEXT: vmrgew v2, v3, v2 1614; P8BE-NEXT: xvcvspsxws v2, v2 1615; P8BE-NEXT: blr 1616; 1617; P8LE-LABEL: fromDiffMemVarAConvftoi: 1618; P8LE: # %bb.0: # %entry 1619; P8LE-NEXT: sldi r4, r4, 2 1620; P8LE-NEXT: lfsux f0, r3, r4 1621; P8LE-NEXT: lfs f1, 8(r3) 1622; P8LE-NEXT: lfs f2, 4(r3) 1623; P8LE-NEXT: lfs f3, 12(r3) 1624; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1625; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1626; P8LE-NEXT: xvcvdpsp v2, vs0 1627; P8LE-NEXT: xvcvdpsp v3, vs1 1628; P8LE-NEXT: vmrgew v2, v3, v2 1629; P8LE-NEXT: xvcvspsxws v2, v2 1630; P8LE-NEXT: blr 1631entry: 1632 %idxprom = sext i32 %elem to i64 1633 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1634 %0 = load float, float* %arrayidx, align 4 1635 %conv = fptosi float %0 to i32 1636 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1637 %add = add nsw i32 %elem, 1 1638 %idxprom1 = sext i32 %add to i64 1639 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1640 %1 = load float, float* %arrayidx2, align 4 1641 %conv3 = fptosi float %1 to i32 1642 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1643 %add5 = add nsw i32 %elem, 2 1644 %idxprom6 = sext i32 %add5 to i64 1645 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1646 %2 = load float, float* %arrayidx7, align 4 1647 %conv8 = fptosi float %2 to i32 1648 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1649 %add10 = add nsw i32 %elem, 3 1650 %idxprom11 = sext i32 %add10 to i64 1651 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1652 %3 = load float, float* %arrayidx12, align 4 1653 %conv13 = fptosi float %3 to i32 1654 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1655 ret <4 x i32> %vecinit14 1656; FIXME: implement finding consecutive loads with pre-inc 1657} 1658 1659; Function Attrs: norecurse nounwind readonly 1660define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1661; P9BE-LABEL: fromDiffMemVarDConvftoi: 1662; P9BE: # %bb.0: # %entry 1663; P9BE-NEXT: sldi r4, r4, 2 1664; P9BE-NEXT: lfsux f0, r3, r4 1665; P9BE-NEXT: lfs f1, -12(r3) 1666; P9BE-NEXT: lfs f2, -4(r3) 1667; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1668; P9BE-NEXT: xvcvdpsp v2, vs1 1669; P9BE-NEXT: lfs f1, -8(r3) 1670; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1671; P9BE-NEXT: xvcvdpsp v3, vs0 1672; P9BE-NEXT: vmrgew v2, v3, v2 1673; P9BE-NEXT: xvcvspsxws v2, v2 1674; P9BE-NEXT: blr 1675; 1676; P9LE-LABEL: fromDiffMemVarDConvftoi: 1677; P9LE: # %bb.0: # %entry 1678; P9LE-NEXT: sldi r4, r4, 2 1679; P9LE-NEXT: lfsux f0, r3, r4 1680; P9LE-NEXT: lfs f1, -8(r3) 1681; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1682; P9LE-NEXT: lfs f1, -12(r3) 1683; P9LE-NEXT: xvcvdpsp v2, vs0 1684; P9LE-NEXT: lfs f0, -4(r3) 1685; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1686; P9LE-NEXT: xvcvdpsp v3, vs0 1687; P9LE-NEXT: vmrgew v2, v3, v2 1688; P9LE-NEXT: xvcvspsxws v2, v2 1689; P9LE-NEXT: blr 1690; 1691; P8BE-LABEL: fromDiffMemVarDConvftoi: 1692; P8BE: # %bb.0: # %entry 1693; P8BE-NEXT: sldi r4, r4, 2 1694; P8BE-NEXT: lfsux f0, r3, r4 1695; P8BE-NEXT: lfs f1, -12(r3) 1696; P8BE-NEXT: lfs f2, -4(r3) 1697; P8BE-NEXT: lfs f3, -8(r3) 1698; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1699; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1700; P8BE-NEXT: xvcvdpsp v2, vs1 1701; P8BE-NEXT: xvcvdpsp v3, vs0 1702; P8BE-NEXT: vmrgew v2, v3, v2 1703; P8BE-NEXT: xvcvspsxws v2, v2 1704; P8BE-NEXT: blr 1705; 1706; P8LE-LABEL: fromDiffMemVarDConvftoi: 1707; P8LE: # %bb.0: # %entry 1708; P8LE-NEXT: sldi r4, r4, 2 1709; P8LE-NEXT: lfsux f0, r3, r4 1710; P8LE-NEXT: lfs f1, -8(r3) 1711; P8LE-NEXT: lfs f2, -4(r3) 1712; P8LE-NEXT: lfs f3, -12(r3) 1713; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1714; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1715; P8LE-NEXT: xvcvdpsp v2, vs0 1716; P8LE-NEXT: xvcvdpsp v3, vs1 1717; P8LE-NEXT: vmrgew v2, v3, v2 1718; P8LE-NEXT: xvcvspsxws v2, v2 1719; P8LE-NEXT: blr 1720entry: 1721 %idxprom = sext i32 %elem to i64 1722 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1723 %0 = load float, float* %arrayidx, align 4 1724 %conv = fptosi float %0 to i32 1725 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1726 %sub = add nsw i32 %elem, -1 1727 %idxprom1 = sext i32 %sub to i64 1728 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1729 %1 = load float, float* %arrayidx2, align 4 1730 %conv3 = fptosi float %1 to i32 1731 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1732 %sub5 = add nsw i32 %elem, -2 1733 %idxprom6 = sext i32 %sub5 to i64 1734 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1735 %2 = load float, float* %arrayidx7, align 4 1736 %conv8 = fptosi float %2 to i32 1737 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1738 %sub10 = add nsw i32 %elem, -3 1739 %idxprom11 = sext i32 %sub10 to i64 1740 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1741 %3 = load float, float* %arrayidx12, align 4 1742 %conv13 = fptosi float %3 to i32 1743 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1744 ret <4 x i32> %vecinit14 1745; FIXME: implement finding consecutive loads with pre-inc 1746} 1747 1748; Function Attrs: norecurse nounwind readnone 1749define <4 x i32> @spltRegValConvftoi(float %val) { 1750; P9BE-LABEL: spltRegValConvftoi: 1751; P9BE: # %bb.0: # %entry 1752; P9BE-NEXT: xscvdpsxws f0, f1 1753; P9BE-NEXT: xxspltw v2, vs0, 1 1754; P9BE-NEXT: blr 1755; 1756; P9LE-LABEL: spltRegValConvftoi: 1757; P9LE: # %bb.0: # %entry 1758; P9LE-NEXT: xscvdpsxws f0, f1 1759; P9LE-NEXT: xxspltw v2, vs0, 1 1760; P9LE-NEXT: blr 1761; 1762; P8BE-LABEL: spltRegValConvftoi: 1763; P8BE: # %bb.0: # %entry 1764; P8BE-NEXT: xscvdpsxws f0, f1 1765; P8BE-NEXT: xxspltw v2, vs0, 1 1766; P8BE-NEXT: blr 1767; 1768; P8LE-LABEL: spltRegValConvftoi: 1769; P8LE: # %bb.0: # %entry 1770; P8LE-NEXT: xscvdpsxws f0, f1 1771; P8LE-NEXT: xxspltw v2, vs0, 1 1772; P8LE-NEXT: blr 1773entry: 1774 %conv = fptosi float %val to i32 1775 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1776 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1777 ret <4 x i32> %splat.splat 1778} 1779 1780; Function Attrs: norecurse nounwind readonly 1781define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1782; P9BE-LABEL: spltMemValConvftoi: 1783; P9BE: # %bb.0: # %entry 1784; P9BE-NEXT: lxvwsx vs0, 0, r3 1785; P9BE-NEXT: xvcvspsxws v2, vs0 1786; P9BE-NEXT: blr 1787; 1788; P9LE-LABEL: spltMemValConvftoi: 1789; P9LE: # %bb.0: # %entry 1790; P9LE-NEXT: lxvwsx vs0, 0, r3 1791; P9LE-NEXT: xvcvspsxws v2, vs0 1792; P9LE-NEXT: blr 1793; 1794; P8BE-LABEL: spltMemValConvftoi: 1795; P8BE: # %bb.0: # %entry 1796; P8BE-NEXT: lfsx f0, 0, r3 1797; P8BE-NEXT: xscvdpsxws f0, f0 1798; P8BE-NEXT: xxspltw v2, vs0, 1 1799; P8BE-NEXT: blr 1800; 1801; P8LE-LABEL: spltMemValConvftoi: 1802; P8LE: # %bb.0: # %entry 1803; P8LE-NEXT: lfsx f0, 0, r3 1804; P8LE-NEXT: xscvdpsxws f0, f0 1805; P8LE-NEXT: xxspltw v2, vs0, 1 1806; P8LE-NEXT: blr 1807entry: 1808 %0 = load float, float* %ptr, align 4 1809 %conv = fptosi float %0 to i32 1810 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1811 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1812 ret <4 x i32> %splat.splat 1813} 1814 1815; Function Attrs: norecurse nounwind readnone 1816define <4 x i32> @spltCnstConvdtoi() { 1817; P9BE-LABEL: spltCnstConvdtoi: 1818; P9BE: # %bb.0: # %entry 1819; P9BE-NEXT: vspltisw v2, 4 1820; P9BE-NEXT: blr 1821; 1822; P9LE-LABEL: spltCnstConvdtoi: 1823; P9LE: # %bb.0: # %entry 1824; P9LE-NEXT: vspltisw v2, 4 1825; P9LE-NEXT: blr 1826; 1827; P8BE-LABEL: spltCnstConvdtoi: 1828; P8BE: # %bb.0: # %entry 1829; P8BE-NEXT: vspltisw v2, 4 1830; P8BE-NEXT: blr 1831; 1832; P8LE-LABEL: spltCnstConvdtoi: 1833; P8LE: # %bb.0: # %entry 1834; P8LE-NEXT: vspltisw v2, 4 1835; P8LE-NEXT: blr 1836entry: 1837 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1838} 1839 1840; Function Attrs: norecurse nounwind readnone 1841define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1842; P9BE-LABEL: fromRegsConvdtoi: 1843; P9BE: # %bb.0: # %entry 1844; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1845; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1846; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1847; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1848; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1849; P9BE-NEXT: xvcvdpsxws v2, vs0 1850; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1851; P9BE-NEXT: xvcvdpsxws v3, vs0 1852; P9BE-NEXT: vmrgew v2, v3, v2 1853; P9BE-NEXT: blr 1854; 1855; P9LE-LABEL: fromRegsConvdtoi: 1856; P9LE: # %bb.0: # %entry 1857; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1858; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1859; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1860; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1861; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1862; P9LE-NEXT: xvcvdpsxws v2, vs0 1863; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1864; P9LE-NEXT: xvcvdpsxws v3, vs0 1865; P9LE-NEXT: vmrgew v2, v3, v2 1866; P9LE-NEXT: blr 1867; 1868; P8BE-LABEL: fromRegsConvdtoi: 1869; P8BE: # %bb.0: # %entry 1870; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1871; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1872; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1873; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1874; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1875; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1876; P8BE-NEXT: xvcvdpsxws v2, vs0 1877; P8BE-NEXT: xvcvdpsxws v3, vs1 1878; P8BE-NEXT: vmrgew v2, v3, v2 1879; P8BE-NEXT: blr 1880; 1881; P8LE-LABEL: fromRegsConvdtoi: 1882; P8LE: # %bb.0: # %entry 1883; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1884; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1885; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1886; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1887; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1888; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1889; P8LE-NEXT: xvcvdpsxws v2, vs0 1890; P8LE-NEXT: xvcvdpsxws v3, vs1 1891; P8LE-NEXT: vmrgew v2, v3, v2 1892; P8LE-NEXT: blr 1893entry: 1894 %conv = fptosi double %a to i32 1895 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1896 %conv1 = fptosi double %b to i32 1897 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1898 %conv3 = fptosi double %c to i32 1899 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1900 %conv5 = fptosi double %d to i32 1901 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1902 ret <4 x i32> %vecinit6 1903} 1904 1905; Function Attrs: norecurse nounwind readnone 1906define <4 x i32> @fromDiffConstsConvdtoi() { 1907; P9BE-LABEL: fromDiffConstsConvdtoi: 1908; P9BE: # %bb.0: # %entry 1909; P9BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1910; P9BE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1911; P9BE-NEXT: lxvx v2, 0, r3 1912; P9BE-NEXT: blr 1913; 1914; P9LE-LABEL: fromDiffConstsConvdtoi: 1915; P9LE: # %bb.0: # %entry 1916; P9LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1917; P9LE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1918; P9LE-NEXT: lxvx v2, 0, r3 1919; P9LE-NEXT: blr 1920; 1921; P8BE-LABEL: fromDiffConstsConvdtoi: 1922; P8BE: # %bb.0: # %entry 1923; P8BE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1924; P8BE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1925; P8BE-NEXT: lxvw4x v2, 0, r3 1926; P8BE-NEXT: blr 1927; 1928; P8LE-LABEL: fromDiffConstsConvdtoi: 1929; P8LE: # %bb.0: # %entry 1930; P8LE-NEXT: addis r3, r2, .LCPI26_0@toc@ha 1931; P8LE-NEXT: addi r3, r3, .LCPI26_0@toc@l 1932; P8LE-NEXT: lvx v2, 0, r3 1933; P8LE-NEXT: blr 1934entry: 1935 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1936} 1937 1938; Function Attrs: norecurse nounwind readonly 1939define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1940; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1941; P9BE: # %bb.0: # %entry 1942; P9BE-NEXT: lxv vs0, 0(r3) 1943; P9BE-NEXT: lxv vs1, 16(r3) 1944; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1945; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1946; P9BE-NEXT: xvcvdpsxws v2, vs2 1947; P9BE-NEXT: xvcvdpsxws v3, vs0 1948; P9BE-NEXT: vmrgew v2, v3, v2 1949; P9BE-NEXT: blr 1950; 1951; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1952; P9LE: # %bb.0: # %entry 1953; P9LE-NEXT: lxv vs0, 0(r3) 1954; P9LE-NEXT: lxv vs1, 16(r3) 1955; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1956; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1957; P9LE-NEXT: xvcvdpsxws v2, vs2 1958; P9LE-NEXT: xvcvdpsxws v3, vs0 1959; P9LE-NEXT: vmrgew v2, v3, v2 1960; P9LE-NEXT: blr 1961; 1962; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1963; P8BE: # %bb.0: # %entry 1964; P8BE-NEXT: li r4, 16 1965; P8BE-NEXT: lxvd2x vs0, 0, r3 1966; P8BE-NEXT: lxvd2x vs1, r3, r4 1967; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1968; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1969; P8BE-NEXT: xvcvdpsxws v2, vs2 1970; P8BE-NEXT: xvcvdpsxws v3, vs0 1971; P8BE-NEXT: vmrgew v2, v3, v2 1972; P8BE-NEXT: blr 1973; 1974; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1975; P8LE: # %bb.0: # %entry 1976; P8LE-NEXT: li r4, 16 1977; P8LE-NEXT: lxvd2x vs0, 0, r3 1978; P8LE-NEXT: lxvd2x vs1, r3, r4 1979; P8LE-NEXT: xxswapd vs0, vs0 1980; P8LE-NEXT: xxswapd vs1, vs1 1981; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1982; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1983; P8LE-NEXT: xvcvdpsxws v2, vs2 1984; P8LE-NEXT: xvcvdpsxws v3, vs0 1985; P8LE-NEXT: vmrgew v2, v3, v2 1986; P8LE-NEXT: blr 1987entry: 1988 %0 = bitcast double* %ptr to <2 x double>* 1989 %1 = load <2 x double>, <2 x double>* %0, align 8 1990 %2 = fptosi <2 x double> %1 to <2 x i32> 1991 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1992 %3 = bitcast double* %arrayidx4 to <2 x double>* 1993 %4 = load <2 x double>, <2 x double>* %3, align 8 1994 %5 = fptosi <2 x double> %4 to <2 x i32> 1995 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1996 ret <4 x i32> %vecinit9 1997} 1998 1999; Function Attrs: norecurse nounwind readonly 2000define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 2001; P9BE-LABEL: fromDiffMemConsDConvdtoi: 2002; P9BE: # %bb.0: # %entry 2003; P9BE-NEXT: lfd f0, 24(r3) 2004; P9BE-NEXT: lfd f1, 16(r3) 2005; P9BE-NEXT: lfd f2, 8(r3) 2006; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2007; P9BE-NEXT: lfd f3, 0(r3) 2008; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2009; P9BE-NEXT: xvcvdpsxws v2, vs1 2010; P9BE-NEXT: xvcvdpsxws v3, vs0 2011; P9BE-NEXT: vmrgew v2, v3, v2 2012; P9BE-NEXT: blr 2013; 2014; P9LE-LABEL: fromDiffMemConsDConvdtoi: 2015; P9LE: # %bb.0: # %entry 2016; P9LE-NEXT: lfd f0, 24(r3) 2017; P9LE-NEXT: lfd f2, 8(r3) 2018; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2019; P9LE-NEXT: lfd f1, 16(r3) 2020; P9LE-NEXT: lfd f3, 0(r3) 2021; P9LE-NEXT: xvcvdpsxws v2, vs0 2022; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2023; P9LE-NEXT: xvcvdpsxws v3, vs0 2024; P9LE-NEXT: vmrgew v2, v3, v2 2025; P9LE-NEXT: blr 2026; 2027; P8BE-LABEL: fromDiffMemConsDConvdtoi: 2028; P8BE: # %bb.0: # %entry 2029; P8BE-NEXT: lfdx f3, 0, r3 2030; P8BE-NEXT: lfd f0, 24(r3) 2031; P8BE-NEXT: lfd f1, 8(r3) 2032; P8BE-NEXT: lfd f2, 16(r3) 2033; P8BE-NEXT: xxmrghd vs0, vs0, vs1 2034; P8BE-NEXT: xxmrghd vs1, vs2, vs3 2035; P8BE-NEXT: xvcvdpsxws v2, vs0 2036; P8BE-NEXT: xvcvdpsxws v3, vs1 2037; P8BE-NEXT: vmrgew v2, v2, v3 2038; P8BE-NEXT: blr 2039; 2040; P8LE-LABEL: fromDiffMemConsDConvdtoi: 2041; P8LE: # %bb.0: # %entry 2042; P8LE-NEXT: lfdx f3, 0, r3 2043; P8LE-NEXT: lfd f0, 24(r3) 2044; P8LE-NEXT: lfd f1, 8(r3) 2045; P8LE-NEXT: lfd f2, 16(r3) 2046; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2047; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2048; P8LE-NEXT: xvcvdpsxws v2, vs0 2049; P8LE-NEXT: xvcvdpsxws v3, vs1 2050; P8LE-NEXT: vmrgew v2, v3, v2 2051; P8LE-NEXT: blr 2052entry: 2053 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 2054 %0 = load double, double* %arrayidx, align 8 2055 %conv = fptosi double %0 to i32 2056 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2057 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 2058 %1 = load double, double* %arrayidx1, align 8 2059 %conv2 = fptosi double %1 to i32 2060 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2061 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 2062 %2 = load double, double* %arrayidx4, align 8 2063 %conv5 = fptosi double %2 to i32 2064 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2065 %3 = load double, double* %ptr, align 8 2066 %conv8 = fptosi double %3 to i32 2067 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2068 ret <4 x i32> %vecinit9 2069} 2070 2071; Function Attrs: norecurse nounwind readonly 2072define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2073; P9BE-LABEL: fromDiffMemVarAConvdtoi: 2074; P9BE: # %bb.0: # %entry 2075; P9BE-NEXT: sldi r4, r4, 3 2076; P9BE-NEXT: lfdux f0, r3, r4 2077; P9BE-NEXT: lfd f1, 8(r3) 2078; P9BE-NEXT: lfd f2, 16(r3) 2079; P9BE-NEXT: lfd f3, 24(r3) 2080; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2081; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2082; P9BE-NEXT: xvcvdpsxws v2, vs1 2083; P9BE-NEXT: xvcvdpsxws v3, vs0 2084; P9BE-NEXT: vmrgew v2, v3, v2 2085; P9BE-NEXT: blr 2086; 2087; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2088; P9LE: # %bb.0: # %entry 2089; P9LE-NEXT: sldi r4, r4, 3 2090; P9LE-NEXT: lfdux f0, r3, r4 2091; P9LE-NEXT: lfd f2, 16(r3) 2092; P9LE-NEXT: lfd f1, 8(r3) 2093; P9LE-NEXT: lfd f3, 24(r3) 2094; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2095; P9LE-NEXT: xvcvdpsxws v2, vs0 2096; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2097; P9LE-NEXT: xvcvdpsxws v3, vs0 2098; P9LE-NEXT: vmrgew v2, v3, v2 2099; P9LE-NEXT: blr 2100; 2101; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2102; P8BE: # %bb.0: # %entry 2103; P8BE-NEXT: sldi r4, r4, 3 2104; P8BE-NEXT: lfdux f0, r3, r4 2105; P8BE-NEXT: lfd f1, 8(r3) 2106; P8BE-NEXT: lfd f2, 24(r3) 2107; P8BE-NEXT: lfd f3, 16(r3) 2108; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2109; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2110; P8BE-NEXT: xvcvdpsxws v2, vs1 2111; P8BE-NEXT: xvcvdpsxws v3, vs0 2112; P8BE-NEXT: vmrgew v2, v3, v2 2113; P8BE-NEXT: blr 2114; 2115; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2116; P8LE: # %bb.0: # %entry 2117; P8LE-NEXT: sldi r4, r4, 3 2118; P8LE-NEXT: lfdux f0, r3, r4 2119; P8LE-NEXT: lfd f1, 16(r3) 2120; P8LE-NEXT: lfd f2, 8(r3) 2121; P8LE-NEXT: lfd f3, 24(r3) 2122; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2123; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2124; P8LE-NEXT: xvcvdpsxws v2, vs0 2125; P8LE-NEXT: xvcvdpsxws v3, vs1 2126; P8LE-NEXT: vmrgew v2, v3, v2 2127; P8LE-NEXT: blr 2128entry: 2129 %idxprom = sext i32 %elem to i64 2130 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2131 %0 = load double, double* %arrayidx, align 8 2132 %conv = fptosi double %0 to i32 2133 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2134 %add = add nsw i32 %elem, 1 2135 %idxprom1 = sext i32 %add to i64 2136 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2137 %1 = load double, double* %arrayidx2, align 8 2138 %conv3 = fptosi double %1 to i32 2139 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2140 %add5 = add nsw i32 %elem, 2 2141 %idxprom6 = sext i32 %add5 to i64 2142 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2143 %2 = load double, double* %arrayidx7, align 8 2144 %conv8 = fptosi double %2 to i32 2145 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2146 %add10 = add nsw i32 %elem, 3 2147 %idxprom11 = sext i32 %add10 to i64 2148 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2149 %3 = load double, double* %arrayidx12, align 8 2150 %conv13 = fptosi double %3 to i32 2151 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2152 ret <4 x i32> %vecinit14 2153} 2154 2155; Function Attrs: norecurse nounwind readonly 2156define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2157; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2158; P9BE: # %bb.0: # %entry 2159; P9BE-NEXT: sldi r4, r4, 3 2160; P9BE-NEXT: lfdux f0, r3, r4 2161; P9BE-NEXT: lfd f1, -8(r3) 2162; P9BE-NEXT: lfd f2, -16(r3) 2163; P9BE-NEXT: lfd f3, -24(r3) 2164; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2165; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2166; P9BE-NEXT: xvcvdpsxws v2, vs1 2167; P9BE-NEXT: xvcvdpsxws v3, vs0 2168; P9BE-NEXT: vmrgew v2, v3, v2 2169; P9BE-NEXT: blr 2170; 2171; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2172; P9LE: # %bb.0: # %entry 2173; P9LE-NEXT: sldi r4, r4, 3 2174; P9LE-NEXT: lfdux f0, r3, r4 2175; P9LE-NEXT: lfd f2, -16(r3) 2176; P9LE-NEXT: lfd f1, -8(r3) 2177; P9LE-NEXT: lfd f3, -24(r3) 2178; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2179; P9LE-NEXT: xvcvdpsxws v2, vs0 2180; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2181; P9LE-NEXT: xvcvdpsxws v3, vs0 2182; P9LE-NEXT: vmrgew v2, v3, v2 2183; P9LE-NEXT: blr 2184; 2185; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2186; P8BE: # %bb.0: # %entry 2187; P8BE-NEXT: sldi r4, r4, 3 2188; P8BE-NEXT: lfdux f0, r3, r4 2189; P8BE-NEXT: lfd f1, -8(r3) 2190; P8BE-NEXT: lfd f2, -24(r3) 2191; P8BE-NEXT: lfd f3, -16(r3) 2192; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2193; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2194; P8BE-NEXT: xvcvdpsxws v2, vs1 2195; P8BE-NEXT: xvcvdpsxws v3, vs0 2196; P8BE-NEXT: vmrgew v2, v3, v2 2197; P8BE-NEXT: blr 2198; 2199; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2200; P8LE: # %bb.0: # %entry 2201; P8LE-NEXT: sldi r4, r4, 3 2202; P8LE-NEXT: lfdux f0, r3, r4 2203; P8LE-NEXT: lfd f1, -16(r3) 2204; P8LE-NEXT: lfd f2, -8(r3) 2205; P8LE-NEXT: lfd f3, -24(r3) 2206; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2207; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2208; P8LE-NEXT: xvcvdpsxws v2, vs0 2209; P8LE-NEXT: xvcvdpsxws v3, vs1 2210; P8LE-NEXT: vmrgew v2, v3, v2 2211; P8LE-NEXT: blr 2212entry: 2213 %idxprom = sext i32 %elem to i64 2214 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2215 %0 = load double, double* %arrayidx, align 8 2216 %conv = fptosi double %0 to i32 2217 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2218 %sub = add nsw i32 %elem, -1 2219 %idxprom1 = sext i32 %sub to i64 2220 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2221 %1 = load double, double* %arrayidx2, align 8 2222 %conv3 = fptosi double %1 to i32 2223 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2224 %sub5 = add nsw i32 %elem, -2 2225 %idxprom6 = sext i32 %sub5 to i64 2226 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2227 %2 = load double, double* %arrayidx7, align 8 2228 %conv8 = fptosi double %2 to i32 2229 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2230 %sub10 = add nsw i32 %elem, -3 2231 %idxprom11 = sext i32 %sub10 to i64 2232 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2233 %3 = load double, double* %arrayidx12, align 8 2234 %conv13 = fptosi double %3 to i32 2235 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2236 ret <4 x i32> %vecinit14 2237} 2238 2239; Function Attrs: norecurse nounwind readnone 2240define <4 x i32> @spltRegValConvdtoi(double %val) { 2241; P9BE-LABEL: spltRegValConvdtoi: 2242; P9BE: # %bb.0: # %entry 2243; P9BE-NEXT: xscvdpsxws f0, f1 2244; P9BE-NEXT: xxspltw v2, vs0, 1 2245; P9BE-NEXT: blr 2246; 2247; P9LE-LABEL: spltRegValConvdtoi: 2248; P9LE: # %bb.0: # %entry 2249; P9LE-NEXT: xscvdpsxws f0, f1 2250; P9LE-NEXT: xxspltw v2, vs0, 1 2251; P9LE-NEXT: blr 2252; 2253; P8BE-LABEL: spltRegValConvdtoi: 2254; P8BE: # %bb.0: # %entry 2255; P8BE-NEXT: xscvdpsxws f0, f1 2256; P8BE-NEXT: xxspltw v2, vs0, 1 2257; P8BE-NEXT: blr 2258; 2259; P8LE-LABEL: spltRegValConvdtoi: 2260; P8LE: # %bb.0: # %entry 2261; P8LE-NEXT: xscvdpsxws f0, f1 2262; P8LE-NEXT: xxspltw v2, vs0, 1 2263; P8LE-NEXT: blr 2264entry: 2265 %conv = fptosi double %val to i32 2266 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2267 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2268 ret <4 x i32> %splat.splat 2269} 2270 2271; Function Attrs: norecurse nounwind readonly 2272define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2273; P9BE-LABEL: spltMemValConvdtoi: 2274; P9BE: # %bb.0: # %entry 2275; P9BE-NEXT: lfd f0, 0(r3) 2276; P9BE-NEXT: xscvdpsxws f0, f0 2277; P9BE-NEXT: xxspltw v2, vs0, 1 2278; P9BE-NEXT: blr 2279; 2280; P9LE-LABEL: spltMemValConvdtoi: 2281; P9LE: # %bb.0: # %entry 2282; P9LE-NEXT: lfd f0, 0(r3) 2283; P9LE-NEXT: xscvdpsxws f0, f0 2284; P9LE-NEXT: xxspltw v2, vs0, 1 2285; P9LE-NEXT: blr 2286; 2287; P8BE-LABEL: spltMemValConvdtoi: 2288; P8BE: # %bb.0: # %entry 2289; P8BE-NEXT: lfdx f0, 0, r3 2290; P8BE-NEXT: xscvdpsxws f0, f0 2291; P8BE-NEXT: xxspltw v2, vs0, 1 2292; P8BE-NEXT: blr 2293; 2294; P8LE-LABEL: spltMemValConvdtoi: 2295; P8LE: # %bb.0: # %entry 2296; P8LE-NEXT: lfdx f0, 0, r3 2297; P8LE-NEXT: xscvdpsxws f0, f0 2298; P8LE-NEXT: xxspltw v2, vs0, 1 2299; P8LE-NEXT: blr 2300entry: 2301 %0 = load double, double* %ptr, align 8 2302 %conv = fptosi double %0 to i32 2303 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2304 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2305 ret <4 x i32> %splat.splat 2306} 2307; Function Attrs: norecurse nounwind readnone 2308define <4 x i32> @allZeroui() { 2309; P9BE-LABEL: allZeroui: 2310; P9BE: # %bb.0: # %entry 2311; P9BE-NEXT: xxlxor v2, v2, v2 2312; P9BE-NEXT: blr 2313; 2314; P9LE-LABEL: allZeroui: 2315; P9LE: # %bb.0: # %entry 2316; P9LE-NEXT: xxlxor v2, v2, v2 2317; P9LE-NEXT: blr 2318; 2319; P8BE-LABEL: allZeroui: 2320; P8BE: # %bb.0: # %entry 2321; P8BE-NEXT: xxlxor v2, v2, v2 2322; P8BE-NEXT: blr 2323; 2324; P8LE-LABEL: allZeroui: 2325; P8LE: # %bb.0: # %entry 2326; P8LE-NEXT: xxlxor v2, v2, v2 2327; P8LE-NEXT: blr 2328entry: 2329 ret <4 x i32> zeroinitializer 2330} 2331 2332; Function Attrs: norecurse nounwind readnone 2333define <4 x i32> @allOneui() { 2334; P9BE-LABEL: allOneui: 2335; P9BE: # %bb.0: # %entry 2336; P9BE-NEXT: xxspltib v2, 255 2337; P9BE-NEXT: blr 2338; 2339; P9LE-LABEL: allOneui: 2340; P9LE: # %bb.0: # %entry 2341; P9LE-NEXT: xxspltib v2, 255 2342; P9LE-NEXT: blr 2343; 2344; P8BE-LABEL: allOneui: 2345; P8BE: # %bb.0: # %entry 2346; P8BE-NEXT: vspltisb v2, -1 2347; P8BE-NEXT: blr 2348; 2349; P8LE-LABEL: allOneui: 2350; P8LE: # %bb.0: # %entry 2351; P8LE-NEXT: vspltisb v2, -1 2352; P8LE-NEXT: blr 2353entry: 2354 ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> 2355} 2356 2357; Function Attrs: norecurse nounwind readnone 2358define <4 x i32> @spltConst1ui() { 2359; P9BE-LABEL: spltConst1ui: 2360; P9BE: # %bb.0: # %entry 2361; P9BE-NEXT: vspltisw v2, 1 2362; P9BE-NEXT: blr 2363; 2364; P9LE-LABEL: spltConst1ui: 2365; P9LE: # %bb.0: # %entry 2366; P9LE-NEXT: vspltisw v2, 1 2367; P9LE-NEXT: blr 2368; 2369; P8BE-LABEL: spltConst1ui: 2370; P8BE: # %bb.0: # %entry 2371; P8BE-NEXT: vspltisw v2, 1 2372; P8BE-NEXT: blr 2373; 2374; P8LE-LABEL: spltConst1ui: 2375; P8LE: # %bb.0: # %entry 2376; P8LE-NEXT: vspltisw v2, 1 2377; P8LE-NEXT: blr 2378entry: 2379 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2380} 2381 2382; Function Attrs: norecurse nounwind readnone 2383define <4 x i32> @spltConst16kui() { 2384; P9BE-LABEL: spltConst16kui: 2385; P9BE: # %bb.0: # %entry 2386; P9BE-NEXT: vspltisw v2, -15 2387; P9BE-NEXT: vsrw v2, v2, v2 2388; P9BE-NEXT: blr 2389; 2390; P9LE-LABEL: spltConst16kui: 2391; P9LE: # %bb.0: # %entry 2392; P9LE-NEXT: vspltisw v2, -15 2393; P9LE-NEXT: vsrw v2, v2, v2 2394; P9LE-NEXT: blr 2395; 2396; P8BE-LABEL: spltConst16kui: 2397; P8BE: # %bb.0: # %entry 2398; P8BE-NEXT: vspltisw v2, -15 2399; P8BE-NEXT: vsrw v2, v2, v2 2400; P8BE-NEXT: blr 2401; 2402; P8LE-LABEL: spltConst16kui: 2403; P8LE: # %bb.0: # %entry 2404; P8LE-NEXT: vspltisw v2, -15 2405; P8LE-NEXT: vsrw v2, v2, v2 2406; P8LE-NEXT: blr 2407entry: 2408 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2409} 2410 2411; Function Attrs: norecurse nounwind readnone 2412define <4 x i32> @spltConst32kui() { 2413; P9BE-LABEL: spltConst32kui: 2414; P9BE: # %bb.0: # %entry 2415; P9BE-NEXT: vspltisw v2, -16 2416; P9BE-NEXT: vsrw v2, v2, v2 2417; P9BE-NEXT: blr 2418; 2419; P9LE-LABEL: spltConst32kui: 2420; P9LE: # %bb.0: # %entry 2421; P9LE-NEXT: vspltisw v2, -16 2422; P9LE-NEXT: vsrw v2, v2, v2 2423; P9LE-NEXT: blr 2424; 2425; P8BE-LABEL: spltConst32kui: 2426; P8BE: # %bb.0: # %entry 2427; P8BE-NEXT: vspltisw v2, -16 2428; P8BE-NEXT: vsrw v2, v2, v2 2429; P8BE-NEXT: blr 2430; 2431; P8LE-LABEL: spltConst32kui: 2432; P8LE: # %bb.0: # %entry 2433; P8LE-NEXT: vspltisw v2, -16 2434; P8LE-NEXT: vsrw v2, v2, v2 2435; P8LE-NEXT: blr 2436entry: 2437 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2438} 2439 2440; Function Attrs: norecurse nounwind readnone 2441define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2442; P9BE-LABEL: fromRegsui: 2443; P9BE: # %bb.0: # %entry 2444; P9BE-NEXT: rldimi r6, r5, 32, 0 2445; P9BE-NEXT: rldimi r4, r3, 32, 0 2446; P9BE-NEXT: mtvsrdd v2, r4, r6 2447; P9BE-NEXT: blr 2448; 2449; P9LE-LABEL: fromRegsui: 2450; P9LE: # %bb.0: # %entry 2451; P9LE-NEXT: rldimi r3, r4, 32, 0 2452; P9LE-NEXT: rldimi r5, r6, 32, 0 2453; P9LE-NEXT: mtvsrdd v2, r5, r3 2454; P9LE-NEXT: blr 2455; 2456; P8BE-LABEL: fromRegsui: 2457; P8BE: # %bb.0: # %entry 2458; P8BE-NEXT: rldimi r6, r5, 32, 0 2459; P8BE-NEXT: rldimi r4, r3, 32, 0 2460; P8BE-NEXT: mtvsrd f0, r6 2461; P8BE-NEXT: mtvsrd f1, r4 2462; P8BE-NEXT: xxmrghd v2, vs1, vs0 2463; P8BE-NEXT: blr 2464; 2465; P8LE-LABEL: fromRegsui: 2466; P8LE: # %bb.0: # %entry 2467; P8LE-NEXT: rldimi r3, r4, 32, 0 2468; P8LE-NEXT: rldimi r5, r6, 32, 0 2469; P8LE-NEXT: mtvsrd f0, r3 2470; P8LE-NEXT: mtvsrd f1, r5 2471; P8LE-NEXT: xxmrghd v2, vs1, vs0 2472; P8LE-NEXT: blr 2473entry: 2474 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2475 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2476 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2477 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2478 ret <4 x i32> %vecinit3 2479} 2480 2481; Function Attrs: norecurse nounwind readnone 2482define <4 x i32> @fromDiffConstsui() { 2483; P9BE-LABEL: fromDiffConstsui: 2484; P9BE: # %bb.0: # %entry 2485; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2486; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2487; P9BE-NEXT: lxvx v2, 0, r3 2488; P9BE-NEXT: blr 2489; 2490; P9LE-LABEL: fromDiffConstsui: 2491; P9LE: # %bb.0: # %entry 2492; P9LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2493; P9LE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2494; P9LE-NEXT: lxvx v2, 0, r3 2495; P9LE-NEXT: blr 2496; 2497; P8BE-LABEL: fromDiffConstsui: 2498; P8BE: # %bb.0: # %entry 2499; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2500; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2501; P8BE-NEXT: lxvw4x v2, 0, r3 2502; P8BE-NEXT: blr 2503; 2504; P8LE-LABEL: fromDiffConstsui: 2505; P8LE: # %bb.0: # %entry 2506; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2507; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2508; P8LE-NEXT: lvx v2, 0, r3 2509; P8LE-NEXT: blr 2510entry: 2511 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2512} 2513 2514; Function Attrs: norecurse nounwind readonly 2515define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2516; P9BE-LABEL: fromDiffMemConsAui: 2517; P9BE: # %bb.0: # %entry 2518; P9BE-NEXT: lxv v2, 0(r3) 2519; P9BE-NEXT: blr 2520; 2521; P9LE-LABEL: fromDiffMemConsAui: 2522; P9LE: # %bb.0: # %entry 2523; P9LE-NEXT: lxv v2, 0(r3) 2524; P9LE-NEXT: blr 2525; 2526; P8BE-LABEL: fromDiffMemConsAui: 2527; P8BE: # %bb.0: # %entry 2528; P8BE-NEXT: lxvw4x v2, 0, r3 2529; P8BE-NEXT: blr 2530; 2531; P8LE-LABEL: fromDiffMemConsAui: 2532; P8LE: # %bb.0: # %entry 2533; P8LE-NEXT: lxvd2x vs0, 0, r3 2534; P8LE-NEXT: xxswapd v2, vs0 2535; P8LE-NEXT: blr 2536entry: 2537 %0 = load i32, i32* %arr, align 4 2538 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2539 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2540 %1 = load i32, i32* %arrayidx1, align 4 2541 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2542 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2543 %2 = load i32, i32* %arrayidx3, align 4 2544 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2545 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2546 %3 = load i32, i32* %arrayidx5, align 4 2547 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2548 ret <4 x i32> %vecinit6 2549} 2550 2551; Function Attrs: norecurse nounwind readonly 2552define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2553; P9BE-LABEL: fromDiffMemConsDui: 2554; P9BE: # %bb.0: # %entry 2555; P9BE-NEXT: lxv v2, 0(r3) 2556; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2557; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2558; P9BE-NEXT: lxvx v3, 0, r3 2559; P9BE-NEXT: vperm v2, v2, v2, v3 2560; P9BE-NEXT: blr 2561; 2562; P9LE-LABEL: fromDiffMemConsDui: 2563; P9LE: # %bb.0: # %entry 2564; P9LE-NEXT: lxvw4x v2, 0, r3 2565; P9LE-NEXT: blr 2566; 2567; P8BE-LABEL: fromDiffMemConsDui: 2568; P8BE: # %bb.0: # %entry 2569; P8BE-NEXT: addis r4, r2, .LCPI41_0@toc@ha 2570; P8BE-NEXT: lxvw4x v2, 0, r3 2571; P8BE-NEXT: addi r4, r4, .LCPI41_0@toc@l 2572; P8BE-NEXT: lxvw4x v3, 0, r4 2573; P8BE-NEXT: vperm v2, v2, v2, v3 2574; P8BE-NEXT: blr 2575; 2576; P8LE-LABEL: fromDiffMemConsDui: 2577; P8LE: # %bb.0: # %entry 2578; P8LE-NEXT: lxvw4x v2, 0, r3 2579; P8LE-NEXT: blr 2580entry: 2581 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2582 %0 = load i32, i32* %arrayidx, align 4 2583 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2584 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2585 %1 = load i32, i32* %arrayidx1, align 4 2586 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2587 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2588 %2 = load i32, i32* %arrayidx3, align 4 2589 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2590 %3 = load i32, i32* %arr, align 4 2591 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2592 ret <4 x i32> %vecinit6 2593} 2594 2595; Function Attrs: norecurse nounwind readonly 2596define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2597; P9BE-LABEL: fromDiffMemVarAui: 2598; P9BE: # %bb.0: # %entry 2599; P9BE-NEXT: sldi r4, r4, 2 2600; P9BE-NEXT: lxvx v2, r3, r4 2601; P9BE-NEXT: blr 2602; 2603; P9LE-LABEL: fromDiffMemVarAui: 2604; P9LE: # %bb.0: # %entry 2605; P9LE-NEXT: sldi r4, r4, 2 2606; P9LE-NEXT: lxvx v2, r3, r4 2607; P9LE-NEXT: blr 2608; 2609; P8BE-LABEL: fromDiffMemVarAui: 2610; P8BE: # %bb.0: # %entry 2611; P8BE-NEXT: sldi r4, r4, 2 2612; P8BE-NEXT: lxvw4x v2, r3, r4 2613; P8BE-NEXT: blr 2614; 2615; P8LE-LABEL: fromDiffMemVarAui: 2616; P8LE: # %bb.0: # %entry 2617; P8LE-NEXT: sldi r4, r4, 2 2618; P8LE-NEXT: lxvd2x vs0, r3, r4 2619; P8LE-NEXT: xxswapd v2, vs0 2620; P8LE-NEXT: blr 2621entry: 2622 %idxprom = sext i32 %elem to i64 2623 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2624 %0 = load i32, i32* %arrayidx, align 4 2625 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2626 %add = add nsw i32 %elem, 1 2627 %idxprom1 = sext i32 %add to i64 2628 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2629 %1 = load i32, i32* %arrayidx2, align 4 2630 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2631 %add4 = add nsw i32 %elem, 2 2632 %idxprom5 = sext i32 %add4 to i64 2633 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2634 %2 = load i32, i32* %arrayidx6, align 4 2635 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2636 %add8 = add nsw i32 %elem, 3 2637 %idxprom9 = sext i32 %add8 to i64 2638 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2639 %3 = load i32, i32* %arrayidx10, align 4 2640 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2641 ret <4 x i32> %vecinit11 2642} 2643 2644; Function Attrs: norecurse nounwind readonly 2645define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2646; P9BE-LABEL: fromDiffMemVarDui: 2647; P9BE: # %bb.0: # %entry 2648; P9BE-NEXT: sldi r4, r4, 2 2649; P9BE-NEXT: add r3, r3, r4 2650; P9BE-NEXT: addi r3, r3, -12 2651; P9BE-NEXT: lxvx v2, 0, r3 2652; P9BE-NEXT: addis r3, r2, .LCPI43_0@toc@ha 2653; P9BE-NEXT: addi r3, r3, .LCPI43_0@toc@l 2654; P9BE-NEXT: lxvx v3, 0, r3 2655; P9BE-NEXT: vperm v2, v2, v2, v3 2656; P9BE-NEXT: blr 2657; 2658; P9LE-LABEL: fromDiffMemVarDui: 2659; P9LE: # %bb.0: # %entry 2660; P9LE-NEXT: sldi r4, r4, 2 2661; P9LE-NEXT: add r3, r3, r4 2662; P9LE-NEXT: addi r3, r3, -12 2663; P9LE-NEXT: lxvx v2, 0, r3 2664; P9LE-NEXT: addis r3, r2, .LCPI43_0@toc@ha 2665; P9LE-NEXT: addi r3, r3, .LCPI43_0@toc@l 2666; P9LE-NEXT: lxvx v3, 0, r3 2667; P9LE-NEXT: vperm v2, v2, v2, v3 2668; P9LE-NEXT: blr 2669; 2670; P8BE-LABEL: fromDiffMemVarDui: 2671; P8BE: # %bb.0: # %entry 2672; P8BE-NEXT: sldi r4, r4, 2 2673; P8BE-NEXT: addis r5, r2, .LCPI43_0@toc@ha 2674; P8BE-NEXT: add r3, r3, r4 2675; P8BE-NEXT: addi r4, r5, .LCPI43_0@toc@l 2676; P8BE-NEXT: addi r3, r3, -12 2677; P8BE-NEXT: lxvw4x v3, 0, r4 2678; P8BE-NEXT: lxvw4x v2, 0, r3 2679; P8BE-NEXT: vperm v2, v2, v2, v3 2680; P8BE-NEXT: blr 2681; 2682; P8LE-LABEL: fromDiffMemVarDui: 2683; P8LE: # %bb.0: # %entry 2684; P8LE-NEXT: sldi r4, r4, 2 2685; P8LE-NEXT: addis r5, r2, .LCPI43_0@toc@ha 2686; P8LE-NEXT: add r3, r3, r4 2687; P8LE-NEXT: addi r3, r3, -12 2688; P8LE-NEXT: lxvd2x vs0, 0, r3 2689; P8LE-NEXT: addi r3, r5, .LCPI43_0@toc@l 2690; P8LE-NEXT: lvx v3, 0, r3 2691; P8LE-NEXT: xxswapd v2, vs0 2692; P8LE-NEXT: vperm v2, v2, v2, v3 2693; P8LE-NEXT: blr 2694entry: 2695 %idxprom = sext i32 %elem to i64 2696 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2697 %0 = load i32, i32* %arrayidx, align 4 2698 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2699 %sub = add nsw i32 %elem, -1 2700 %idxprom1 = sext i32 %sub to i64 2701 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2702 %1 = load i32, i32* %arrayidx2, align 4 2703 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2704 %sub4 = add nsw i32 %elem, -2 2705 %idxprom5 = sext i32 %sub4 to i64 2706 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2707 %2 = load i32, i32* %arrayidx6, align 4 2708 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2709 %sub8 = add nsw i32 %elem, -3 2710 %idxprom9 = sext i32 %sub8 to i64 2711 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2712 %3 = load i32, i32* %arrayidx10, align 4 2713 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2714 ret <4 x i32> %vecinit11 2715} 2716 2717; Function Attrs: norecurse nounwind readonly 2718define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2719; P9BE-LABEL: fromRandMemConsui: 2720; P9BE: # %bb.0: # %entry 2721; P9BE-NEXT: lwz r4, 16(r3) 2722; P9BE-NEXT: lwz r5, 72(r3) 2723; P9BE-NEXT: lwz r6, 8(r3) 2724; P9BE-NEXT: lwz r3, 352(r3) 2725; P9BE-NEXT: rldimi r3, r6, 32, 0 2726; P9BE-NEXT: rldimi r5, r4, 32, 0 2727; P9BE-NEXT: mtvsrdd v2, r5, r3 2728; P9BE-NEXT: blr 2729; 2730; P9LE-LABEL: fromRandMemConsui: 2731; P9LE: # %bb.0: # %entry 2732; P9LE-NEXT: lwz r4, 16(r3) 2733; P9LE-NEXT: lwz r5, 72(r3) 2734; P9LE-NEXT: lwz r6, 8(r3) 2735; P9LE-NEXT: lwz r3, 352(r3) 2736; P9LE-NEXT: rldimi r4, r5, 32, 0 2737; P9LE-NEXT: rldimi r6, r3, 32, 0 2738; P9LE-NEXT: mtvsrdd v2, r6, r4 2739; P9LE-NEXT: blr 2740; 2741; P8BE-LABEL: fromRandMemConsui: 2742; P8BE: # %bb.0: # %entry 2743; P8BE-NEXT: lwz r4, 8(r3) 2744; P8BE-NEXT: lwz r5, 352(r3) 2745; P8BE-NEXT: lwz r6, 16(r3) 2746; P8BE-NEXT: lwz r3, 72(r3) 2747; P8BE-NEXT: rldimi r5, r4, 32, 0 2748; P8BE-NEXT: rldimi r3, r6, 32, 0 2749; P8BE-NEXT: mtvsrd f0, r5 2750; P8BE-NEXT: mtvsrd f1, r3 2751; P8BE-NEXT: xxmrghd v2, vs1, vs0 2752; P8BE-NEXT: blr 2753; 2754; P8LE-LABEL: fromRandMemConsui: 2755; P8LE: # %bb.0: # %entry 2756; P8LE-NEXT: lwz r4, 16(r3) 2757; P8LE-NEXT: lwz r5, 72(r3) 2758; P8LE-NEXT: lwz r6, 8(r3) 2759; P8LE-NEXT: lwz r3, 352(r3) 2760; P8LE-NEXT: rldimi r4, r5, 32, 0 2761; P8LE-NEXT: rldimi r6, r3, 32, 0 2762; P8LE-NEXT: mtvsrd f0, r4 2763; P8LE-NEXT: mtvsrd f1, r6 2764; P8LE-NEXT: xxmrghd v2, vs1, vs0 2765; P8LE-NEXT: blr 2766entry: 2767 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2768 %0 = load i32, i32* %arrayidx, align 4 2769 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2770 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2771 %1 = load i32, i32* %arrayidx1, align 4 2772 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2773 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2774 %2 = load i32, i32* %arrayidx3, align 4 2775 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2776 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2777 %3 = load i32, i32* %arrayidx5, align 4 2778 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2779 ret <4 x i32> %vecinit6 2780} 2781 2782; Function Attrs: norecurse nounwind readonly 2783define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2784; P9BE-LABEL: fromRandMemVarui: 2785; P9BE: # %bb.0: # %entry 2786; P9BE-NEXT: sldi r4, r4, 2 2787; P9BE-NEXT: add r3, r3, r4 2788; P9BE-NEXT: lwz r4, 16(r3) 2789; P9BE-NEXT: lwz r5, 4(r3) 2790; P9BE-NEXT: lwz r6, 8(r3) 2791; P9BE-NEXT: lwz r3, 32(r3) 2792; P9BE-NEXT: rldimi r3, r6, 32, 0 2793; P9BE-NEXT: rldimi r5, r4, 32, 0 2794; P9BE-NEXT: mtvsrdd v2, r5, r3 2795; P9BE-NEXT: blr 2796; 2797; P9LE-LABEL: fromRandMemVarui: 2798; P9LE: # %bb.0: # %entry 2799; P9LE-NEXT: sldi r4, r4, 2 2800; P9LE-NEXT: add r3, r3, r4 2801; P9LE-NEXT: lwz r4, 16(r3) 2802; P9LE-NEXT: lwz r5, 4(r3) 2803; P9LE-NEXT: lwz r6, 8(r3) 2804; P9LE-NEXT: lwz r3, 32(r3) 2805; P9LE-NEXT: rldimi r4, r5, 32, 0 2806; P9LE-NEXT: rldimi r6, r3, 32, 0 2807; P9LE-NEXT: mtvsrdd v2, r6, r4 2808; P9LE-NEXT: blr 2809; 2810; P8BE-LABEL: fromRandMemVarui: 2811; P8BE: # %bb.0: # %entry 2812; P8BE-NEXT: sldi r4, r4, 2 2813; P8BE-NEXT: add r3, r3, r4 2814; P8BE-NEXT: lwz r4, 8(r3) 2815; P8BE-NEXT: lwz r5, 32(r3) 2816; P8BE-NEXT: lwz r6, 16(r3) 2817; P8BE-NEXT: lwz r3, 4(r3) 2818; P8BE-NEXT: rldimi r5, r4, 32, 0 2819; P8BE-NEXT: rldimi r3, r6, 32, 0 2820; P8BE-NEXT: mtvsrd f0, r5 2821; P8BE-NEXT: mtvsrd f1, r3 2822; P8BE-NEXT: xxmrghd v2, vs1, vs0 2823; P8BE-NEXT: blr 2824; 2825; P8LE-LABEL: fromRandMemVarui: 2826; P8LE: # %bb.0: # %entry 2827; P8LE-NEXT: sldi r4, r4, 2 2828; P8LE-NEXT: add r3, r3, r4 2829; P8LE-NEXT: lwz r4, 16(r3) 2830; P8LE-NEXT: lwz r5, 4(r3) 2831; P8LE-NEXT: lwz r6, 8(r3) 2832; P8LE-NEXT: lwz r3, 32(r3) 2833; P8LE-NEXT: rldimi r4, r5, 32, 0 2834; P8LE-NEXT: rldimi r6, r3, 32, 0 2835; P8LE-NEXT: mtvsrd f0, r4 2836; P8LE-NEXT: mtvsrd f1, r6 2837; P8LE-NEXT: xxmrghd v2, vs1, vs0 2838; P8LE-NEXT: blr 2839entry: 2840 %add = add nsw i32 %elem, 4 2841 %idxprom = sext i32 %add to i64 2842 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2843 %0 = load i32, i32* %arrayidx, align 4 2844 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2845 %add1 = add nsw i32 %elem, 1 2846 %idxprom2 = sext i32 %add1 to i64 2847 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2848 %1 = load i32, i32* %arrayidx3, align 4 2849 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2850 %add5 = add nsw i32 %elem, 2 2851 %idxprom6 = sext i32 %add5 to i64 2852 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2853 %2 = load i32, i32* %arrayidx7, align 4 2854 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2855 %add9 = add nsw i32 %elem, 8 2856 %idxprom10 = sext i32 %add9 to i64 2857 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2858 %3 = load i32, i32* %arrayidx11, align 4 2859 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2860 ret <4 x i32> %vecinit12 2861} 2862 2863; Function Attrs: norecurse nounwind readnone 2864define <4 x i32> @spltRegValui(i32 zeroext %val) { 2865; P9BE-LABEL: spltRegValui: 2866; P9BE: # %bb.0: # %entry 2867; P9BE-NEXT: mtvsrws v2, r3 2868; P9BE-NEXT: blr 2869; 2870; P9LE-LABEL: spltRegValui: 2871; P9LE: # %bb.0: # %entry 2872; P9LE-NEXT: mtvsrws v2, r3 2873; P9LE-NEXT: blr 2874; 2875; P8BE-LABEL: spltRegValui: 2876; P8BE: # %bb.0: # %entry 2877; P8BE-NEXT: mtvsrwz f0, r3 2878; P8BE-NEXT: xxspltw v2, vs0, 1 2879; P8BE-NEXT: blr 2880; 2881; P8LE-LABEL: spltRegValui: 2882; P8LE: # %bb.0: # %entry 2883; P8LE-NEXT: mtvsrwz f0, r3 2884; P8LE-NEXT: xxspltw v2, vs0, 1 2885; P8LE-NEXT: blr 2886entry: 2887 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2888 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2889 ret <4 x i32> %splat.splat 2890} 2891 2892; Function Attrs: norecurse nounwind readonly 2893define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2894; P9BE-LABEL: spltMemValui: 2895; P9BE: # %bb.0: # %entry 2896; P9BE-NEXT: lfiwzx f0, 0, r3 2897; P9BE-NEXT: xxsldwi vs0, f0, f0, 1 2898; P9BE-NEXT: xxspltw v2, vs0, 0 2899; P9BE-NEXT: blr 2900; 2901; P9LE-LABEL: spltMemValui: 2902; P9LE: # %bb.0: # %entry 2903; P9LE-NEXT: lfiwzx f0, 0, r3 2904; P9LE-NEXT: xxpermdi vs0, f0, f0, 2 2905; P9LE-NEXT: xxspltw v2, vs0, 3 2906; P9LE-NEXT: blr 2907; 2908; P8BE-LABEL: spltMemValui: 2909; P8BE: # %bb.0: # %entry 2910; P8BE-NEXT: lfiwzx f0, 0, r3 2911; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 2912; P8BE-NEXT: xxspltw v2, vs0, 0 2913; P8BE-NEXT: blr 2914; 2915; P8LE-LABEL: spltMemValui: 2916; P8LE: # %bb.0: # %entry 2917; P8LE-NEXT: lfiwzx f0, 0, r3 2918; P8LE-NEXT: xxpermdi vs0, f0, f0, 2 2919; P8LE-NEXT: xxspltw v2, vs0, 3 2920; P8LE-NEXT: blr 2921entry: 2922 %0 = load i32, i32* %ptr, align 4 2923 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2924 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2925 ret <4 x i32> %splat.splat 2926} 2927 2928; Function Attrs: norecurse nounwind readnone 2929define <4 x i32> @spltCnstConvftoui() { 2930; P9BE-LABEL: spltCnstConvftoui: 2931; P9BE: # %bb.0: # %entry 2932; P9BE-NEXT: vspltisw v2, 4 2933; P9BE-NEXT: blr 2934; 2935; P9LE-LABEL: spltCnstConvftoui: 2936; P9LE: # %bb.0: # %entry 2937; P9LE-NEXT: vspltisw v2, 4 2938; P9LE-NEXT: blr 2939; 2940; P8BE-LABEL: spltCnstConvftoui: 2941; P8BE: # %bb.0: # %entry 2942; P8BE-NEXT: vspltisw v2, 4 2943; P8BE-NEXT: blr 2944; 2945; P8LE-LABEL: spltCnstConvftoui: 2946; P8LE: # %bb.0: # %entry 2947; P8LE-NEXT: vspltisw v2, 4 2948; P8LE-NEXT: blr 2949entry: 2950 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2951} 2952 2953; Function Attrs: norecurse nounwind readnone 2954define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2955; P9BE-LABEL: fromRegsConvftoui: 2956; P9BE: # %bb.0: # %entry 2957; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2958; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2959; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2960; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2961; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2962; P9BE-NEXT: xvcvdpuxws v2, vs0 2963; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2964; P9BE-NEXT: xvcvdpuxws v3, vs0 2965; P9BE-NEXT: vmrgew v2, v3, v2 2966; P9BE-NEXT: blr 2967; 2968; P9LE-LABEL: fromRegsConvftoui: 2969; P9LE: # %bb.0: # %entry 2970; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2971; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2972; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2973; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2974; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2975; P9LE-NEXT: xvcvdpuxws v2, vs0 2976; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2977; P9LE-NEXT: xvcvdpuxws v3, vs0 2978; P9LE-NEXT: vmrgew v2, v3, v2 2979; P9LE-NEXT: blr 2980; 2981; P8BE-LABEL: fromRegsConvftoui: 2982; P8BE: # %bb.0: # %entry 2983; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2984; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2985; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2986; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2987; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2988; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2989; P8BE-NEXT: xvcvdpuxws v2, vs0 2990; P8BE-NEXT: xvcvdpuxws v3, vs1 2991; P8BE-NEXT: vmrgew v2, v3, v2 2992; P8BE-NEXT: blr 2993; 2994; P8LE-LABEL: fromRegsConvftoui: 2995; P8LE: # %bb.0: # %entry 2996; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2997; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2998; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2999; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3000; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3001; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3002; P8LE-NEXT: xvcvdpuxws v2, vs0 3003; P8LE-NEXT: xvcvdpuxws v3, vs1 3004; P8LE-NEXT: vmrgew v2, v3, v2 3005; P8LE-NEXT: blr 3006entry: 3007 %conv = fptoui float %a to i32 3008 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3009 %conv1 = fptoui float %b to i32 3010 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3011 %conv3 = fptoui float %c to i32 3012 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3013 %conv5 = fptoui float %d to i32 3014 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3015 ret <4 x i32> %vecinit6 3016} 3017 3018; Function Attrs: norecurse nounwind readnone 3019define <4 x i32> @fromDiffConstsConvftoui() { 3020; P9BE-LABEL: fromDiffConstsConvftoui: 3021; P9BE: # %bb.0: # %entry 3022; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3023; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3024; P9BE-NEXT: lxvx v2, 0, r3 3025; P9BE-NEXT: blr 3026; 3027; P9LE-LABEL: fromDiffConstsConvftoui: 3028; P9LE: # %bb.0: # %entry 3029; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3030; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3031; P9LE-NEXT: lxvx v2, 0, r3 3032; P9LE-NEXT: blr 3033; 3034; P8BE-LABEL: fromDiffConstsConvftoui: 3035; P8BE: # %bb.0: # %entry 3036; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3037; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3038; P8BE-NEXT: lxvw4x v2, 0, r3 3039; P8BE-NEXT: blr 3040; 3041; P8LE-LABEL: fromDiffConstsConvftoui: 3042; P8LE: # %bb.0: # %entry 3043; P8LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 3044; P8LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 3045; P8LE-NEXT: lvx v2, 0, r3 3046; P8LE-NEXT: blr 3047entry: 3048 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3049} 3050 3051; Function Attrs: norecurse nounwind readonly 3052define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 3053; P9BE-LABEL: fromDiffMemConsAConvftoui: 3054; P9BE: # %bb.0: # %entry 3055; P9BE-NEXT: lxv vs0, 0(r3) 3056; P9BE-NEXT: xvcvspuxws v2, vs0 3057; P9BE-NEXT: blr 3058; 3059; P9LE-LABEL: fromDiffMemConsAConvftoui: 3060; P9LE: # %bb.0: # %entry 3061; P9LE-NEXT: lxv vs0, 0(r3) 3062; P9LE-NEXT: xvcvspuxws v2, vs0 3063; P9LE-NEXT: blr 3064; 3065; P8BE-LABEL: fromDiffMemConsAConvftoui: 3066; P8BE: # %bb.0: # %entry 3067; P8BE-NEXT: lxvw4x vs0, 0, r3 3068; P8BE-NEXT: xvcvspuxws v2, vs0 3069; P8BE-NEXT: blr 3070; 3071; P8LE-LABEL: fromDiffMemConsAConvftoui: 3072; P8LE: # %bb.0: # %entry 3073; P8LE-NEXT: lxvd2x vs0, 0, r3 3074; P8LE-NEXT: xxswapd v2, vs0 3075; P8LE-NEXT: xvcvspuxws v2, v2 3076; P8LE-NEXT: blr 3077entry: 3078 %0 = bitcast float* %ptr to <4 x float>* 3079 %1 = load <4 x float>, <4 x float>* %0, align 4 3080 %2 = fptoui <4 x float> %1 to <4 x i32> 3081 ret <4 x i32> %2 3082} 3083 3084; Function Attrs: norecurse nounwind readonly 3085define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 3086; P9BE-LABEL: fromDiffMemConsDConvftoui: 3087; P9BE: # %bb.0: # %entry 3088; P9BE-NEXT: lxv v2, 0(r3) 3089; P9BE-NEXT: addis r3, r2, .LCPI52_0@toc@ha 3090; P9BE-NEXT: addi r3, r3, .LCPI52_0@toc@l 3091; P9BE-NEXT: lxvx v3, 0, r3 3092; P9BE-NEXT: vperm v2, v2, v2, v3 3093; P9BE-NEXT: xvcvspuxws v2, v2 3094; P9BE-NEXT: blr 3095; 3096; P9LE-LABEL: fromDiffMemConsDConvftoui: 3097; P9LE: # %bb.0: # %entry 3098; P9LE-NEXT: lxv v2, 0(r3) 3099; P9LE-NEXT: addis r3, r2, .LCPI52_0@toc@ha 3100; P9LE-NEXT: addi r3, r3, .LCPI52_0@toc@l 3101; P9LE-NEXT: lxvx v3, 0, r3 3102; P9LE-NEXT: vperm v2, v2, v2, v3 3103; P9LE-NEXT: xvcvspuxws v2, v2 3104; P9LE-NEXT: blr 3105; 3106; P8BE-LABEL: fromDiffMemConsDConvftoui: 3107; P8BE: # %bb.0: # %entry 3108; P8BE-NEXT: addis r4, r2, .LCPI52_0@toc@ha 3109; P8BE-NEXT: lxvw4x v2, 0, r3 3110; P8BE-NEXT: addi r4, r4, .LCPI52_0@toc@l 3111; P8BE-NEXT: lxvw4x v3, 0, r4 3112; P8BE-NEXT: vperm v2, v2, v2, v3 3113; P8BE-NEXT: xvcvspuxws v2, v2 3114; P8BE-NEXT: blr 3115; 3116; P8LE-LABEL: fromDiffMemConsDConvftoui: 3117; P8LE: # %bb.0: # %entry 3118; P8LE-NEXT: lxvd2x vs0, 0, r3 3119; P8LE-NEXT: addis r4, r2, .LCPI52_0@toc@ha 3120; P8LE-NEXT: addi r3, r4, .LCPI52_0@toc@l 3121; P8LE-NEXT: lvx v2, 0, r3 3122; P8LE-NEXT: xxswapd v3, vs0 3123; P8LE-NEXT: vperm v2, v3, v3, v2 3124; P8LE-NEXT: xvcvspuxws v2, v2 3125; P8LE-NEXT: blr 3126entry: 3127 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3128 %0 = load float, float* %arrayidx, align 4 3129 %conv = fptoui float %0 to i32 3130 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3131 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3132 %1 = load float, float* %arrayidx1, align 4 3133 %conv2 = fptoui float %1 to i32 3134 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3135 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3136 %2 = load float, float* %arrayidx4, align 4 3137 %conv5 = fptoui float %2 to i32 3138 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3139 %3 = load float, float* %ptr, align 4 3140 %conv8 = fptoui float %3 to i32 3141 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3142 ret <4 x i32> %vecinit9 3143} 3144 3145; Function Attrs: norecurse nounwind readonly 3146define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3147; P9BE-LABEL: fromDiffMemVarAConvftoui: 3148; P9BE: # %bb.0: # %entry 3149; P9BE-NEXT: sldi r4, r4, 2 3150; P9BE-NEXT: lfsux f0, r3, r4 3151; P9BE-NEXT: lfs f1, 12(r3) 3152; P9BE-NEXT: lfs f2, 4(r3) 3153; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3154; P9BE-NEXT: xvcvdpsp v2, vs1 3155; P9BE-NEXT: lfs f1, 8(r3) 3156; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3157; P9BE-NEXT: xvcvdpsp v3, vs0 3158; P9BE-NEXT: vmrgew v2, v3, v2 3159; P9BE-NEXT: xvcvspuxws v2, v2 3160; P9BE-NEXT: blr 3161; 3162; P9LE-LABEL: fromDiffMemVarAConvftoui: 3163; P9LE: # %bb.0: # %entry 3164; P9LE-NEXT: sldi r4, r4, 2 3165; P9LE-NEXT: lfsux f0, r3, r4 3166; P9LE-NEXT: lfs f1, 8(r3) 3167; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3168; P9LE-NEXT: lfs f1, 12(r3) 3169; P9LE-NEXT: xvcvdpsp v2, vs0 3170; P9LE-NEXT: lfs f0, 4(r3) 3171; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3172; P9LE-NEXT: xvcvdpsp v3, vs0 3173; P9LE-NEXT: vmrgew v2, v3, v2 3174; P9LE-NEXT: xvcvspuxws v2, v2 3175; P9LE-NEXT: blr 3176; 3177; P8BE-LABEL: fromDiffMemVarAConvftoui: 3178; P8BE: # %bb.0: # %entry 3179; P8BE-NEXT: sldi r4, r4, 2 3180; P8BE-NEXT: lfsux f0, r3, r4 3181; P8BE-NEXT: lfs f1, 12(r3) 3182; P8BE-NEXT: lfs f2, 4(r3) 3183; P8BE-NEXT: lfs f3, 8(r3) 3184; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3185; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3186; P8BE-NEXT: xvcvdpsp v2, vs1 3187; P8BE-NEXT: xvcvdpsp v3, vs0 3188; P8BE-NEXT: vmrgew v2, v3, v2 3189; P8BE-NEXT: xvcvspuxws v2, v2 3190; P8BE-NEXT: blr 3191; 3192; P8LE-LABEL: fromDiffMemVarAConvftoui: 3193; P8LE: # %bb.0: # %entry 3194; P8LE-NEXT: sldi r4, r4, 2 3195; P8LE-NEXT: lfsux f0, r3, r4 3196; P8LE-NEXT: lfs f1, 8(r3) 3197; P8LE-NEXT: lfs f2, 4(r3) 3198; P8LE-NEXT: lfs f3, 12(r3) 3199; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3200; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3201; P8LE-NEXT: xvcvdpsp v2, vs0 3202; P8LE-NEXT: xvcvdpsp v3, vs1 3203; P8LE-NEXT: vmrgew v2, v3, v2 3204; P8LE-NEXT: xvcvspuxws v2, v2 3205; P8LE-NEXT: blr 3206entry: 3207 %idxprom = sext i32 %elem to i64 3208 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3209 %0 = load float, float* %arrayidx, align 4 3210 %conv = fptoui float %0 to i32 3211 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3212 %add = add nsw i32 %elem, 1 3213 %idxprom1 = sext i32 %add to i64 3214 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3215 %1 = load float, float* %arrayidx2, align 4 3216 %conv3 = fptoui float %1 to i32 3217 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3218 %add5 = add nsw i32 %elem, 2 3219 %idxprom6 = sext i32 %add5 to i64 3220 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3221 %2 = load float, float* %arrayidx7, align 4 3222 %conv8 = fptoui float %2 to i32 3223 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3224 %add10 = add nsw i32 %elem, 3 3225 %idxprom11 = sext i32 %add10 to i64 3226 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3227 %3 = load float, float* %arrayidx12, align 4 3228 %conv13 = fptoui float %3 to i32 3229 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3230 ret <4 x i32> %vecinit14 3231; FIXME: implement finding consecutive loads with pre-inc 3232} 3233 3234; Function Attrs: norecurse nounwind readonly 3235define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3236; P9BE-LABEL: fromDiffMemVarDConvftoui: 3237; P9BE: # %bb.0: # %entry 3238; P9BE-NEXT: sldi r4, r4, 2 3239; P9BE-NEXT: lfsux f0, r3, r4 3240; P9BE-NEXT: lfs f1, -12(r3) 3241; P9BE-NEXT: lfs f2, -4(r3) 3242; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3243; P9BE-NEXT: xvcvdpsp v2, vs1 3244; P9BE-NEXT: lfs f1, -8(r3) 3245; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3246; P9BE-NEXT: xvcvdpsp v3, vs0 3247; P9BE-NEXT: vmrgew v2, v3, v2 3248; P9BE-NEXT: xvcvspuxws v2, v2 3249; P9BE-NEXT: blr 3250; 3251; P9LE-LABEL: fromDiffMemVarDConvftoui: 3252; P9LE: # %bb.0: # %entry 3253; P9LE-NEXT: sldi r4, r4, 2 3254; P9LE-NEXT: lfsux f0, r3, r4 3255; P9LE-NEXT: lfs f1, -8(r3) 3256; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3257; P9LE-NEXT: lfs f1, -12(r3) 3258; P9LE-NEXT: xvcvdpsp v2, vs0 3259; P9LE-NEXT: lfs f0, -4(r3) 3260; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3261; P9LE-NEXT: xvcvdpsp v3, vs0 3262; P9LE-NEXT: vmrgew v2, v3, v2 3263; P9LE-NEXT: xvcvspuxws v2, v2 3264; P9LE-NEXT: blr 3265; 3266; P8BE-LABEL: fromDiffMemVarDConvftoui: 3267; P8BE: # %bb.0: # %entry 3268; P8BE-NEXT: sldi r4, r4, 2 3269; P8BE-NEXT: lfsux f0, r3, r4 3270; P8BE-NEXT: lfs f1, -12(r3) 3271; P8BE-NEXT: lfs f2, -4(r3) 3272; P8BE-NEXT: lfs f3, -8(r3) 3273; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3274; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3275; P8BE-NEXT: xvcvdpsp v2, vs1 3276; P8BE-NEXT: xvcvdpsp v3, vs0 3277; P8BE-NEXT: vmrgew v2, v3, v2 3278; P8BE-NEXT: xvcvspuxws v2, v2 3279; P8BE-NEXT: blr 3280; 3281; P8LE-LABEL: fromDiffMemVarDConvftoui: 3282; P8LE: # %bb.0: # %entry 3283; P8LE-NEXT: sldi r4, r4, 2 3284; P8LE-NEXT: lfsux f0, r3, r4 3285; P8LE-NEXT: lfs f1, -8(r3) 3286; P8LE-NEXT: lfs f2, -4(r3) 3287; P8LE-NEXT: lfs f3, -12(r3) 3288; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3289; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3290; P8LE-NEXT: xvcvdpsp v2, vs0 3291; P8LE-NEXT: xvcvdpsp v3, vs1 3292; P8LE-NEXT: vmrgew v2, v3, v2 3293; P8LE-NEXT: xvcvspuxws v2, v2 3294; P8LE-NEXT: blr 3295entry: 3296 %idxprom = sext i32 %elem to i64 3297 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3298 %0 = load float, float* %arrayidx, align 4 3299 %conv = fptoui float %0 to i32 3300 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3301 %sub = add nsw i32 %elem, -1 3302 %idxprom1 = sext i32 %sub to i64 3303 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3304 %1 = load float, float* %arrayidx2, align 4 3305 %conv3 = fptoui float %1 to i32 3306 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3307 %sub5 = add nsw i32 %elem, -2 3308 %idxprom6 = sext i32 %sub5 to i64 3309 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3310 %2 = load float, float* %arrayidx7, align 4 3311 %conv8 = fptoui float %2 to i32 3312 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3313 %sub10 = add nsw i32 %elem, -3 3314 %idxprom11 = sext i32 %sub10 to i64 3315 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3316 %3 = load float, float* %arrayidx12, align 4 3317 %conv13 = fptoui float %3 to i32 3318 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3319 ret <4 x i32> %vecinit14 3320; FIXME: implement finding consecutive loads with pre-inc 3321} 3322 3323; Function Attrs: norecurse nounwind readnone 3324define <4 x i32> @spltRegValConvftoui(float %val) { 3325; P9BE-LABEL: spltRegValConvftoui: 3326; P9BE: # %bb.0: # %entry 3327; P9BE-NEXT: xscvdpuxws f0, f1 3328; P9BE-NEXT: xxspltw v2, vs0, 1 3329; P9BE-NEXT: blr 3330; 3331; P9LE-LABEL: spltRegValConvftoui: 3332; P9LE: # %bb.0: # %entry 3333; P9LE-NEXT: xscvdpuxws f0, f1 3334; P9LE-NEXT: xxspltw v2, vs0, 1 3335; P9LE-NEXT: blr 3336; 3337; P8BE-LABEL: spltRegValConvftoui: 3338; P8BE: # %bb.0: # %entry 3339; P8BE-NEXT: xscvdpuxws f0, f1 3340; P8BE-NEXT: xxspltw v2, vs0, 1 3341; P8BE-NEXT: blr 3342; 3343; P8LE-LABEL: spltRegValConvftoui: 3344; P8LE: # %bb.0: # %entry 3345; P8LE-NEXT: xscvdpuxws f0, f1 3346; P8LE-NEXT: xxspltw v2, vs0, 1 3347; P8LE-NEXT: blr 3348entry: 3349 %conv = fptoui float %val to i32 3350 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3351 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3352 ret <4 x i32> %splat.splat 3353} 3354 3355; Function Attrs: norecurse nounwind readonly 3356define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3357; P9BE-LABEL: spltMemValConvftoui: 3358; P9BE: # %bb.0: # %entry 3359; P9BE-NEXT: lxvwsx vs0, 0, r3 3360; P9BE-NEXT: xvcvspuxws v2, vs0 3361; P9BE-NEXT: blr 3362; 3363; P9LE-LABEL: spltMemValConvftoui: 3364; P9LE: # %bb.0: # %entry 3365; P9LE-NEXT: lxvwsx vs0, 0, r3 3366; P9LE-NEXT: xvcvspuxws v2, vs0 3367; P9LE-NEXT: blr 3368; 3369; P8BE-LABEL: spltMemValConvftoui: 3370; P8BE: # %bb.0: # %entry 3371; P8BE-NEXT: lfsx f0, 0, r3 3372; P8BE-NEXT: xscvdpuxws f0, f0 3373; P8BE-NEXT: xxspltw v2, vs0, 1 3374; P8BE-NEXT: blr 3375; 3376; P8LE-LABEL: spltMemValConvftoui: 3377; P8LE: # %bb.0: # %entry 3378; P8LE-NEXT: lfsx f0, 0, r3 3379; P8LE-NEXT: xscvdpuxws f0, f0 3380; P8LE-NEXT: xxspltw v2, vs0, 1 3381; P8LE-NEXT: blr 3382entry: 3383 %0 = load float, float* %ptr, align 4 3384 %conv = fptoui float %0 to i32 3385 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3386 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3387 ret <4 x i32> %splat.splat 3388} 3389 3390; Function Attrs: norecurse nounwind readnone 3391define <4 x i32> @spltCnstConvdtoui() { 3392; P9BE-LABEL: spltCnstConvdtoui: 3393; P9BE: # %bb.0: # %entry 3394; P9BE-NEXT: vspltisw v2, 4 3395; P9BE-NEXT: blr 3396; 3397; P9LE-LABEL: spltCnstConvdtoui: 3398; P9LE: # %bb.0: # %entry 3399; P9LE-NEXT: vspltisw v2, 4 3400; P9LE-NEXT: blr 3401; 3402; P8BE-LABEL: spltCnstConvdtoui: 3403; P8BE: # %bb.0: # %entry 3404; P8BE-NEXT: vspltisw v2, 4 3405; P8BE-NEXT: blr 3406; 3407; P8LE-LABEL: spltCnstConvdtoui: 3408; P8LE: # %bb.0: # %entry 3409; P8LE-NEXT: vspltisw v2, 4 3410; P8LE-NEXT: blr 3411entry: 3412 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3413} 3414 3415; Function Attrs: norecurse nounwind readnone 3416define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3417; P9BE-LABEL: fromRegsConvdtoui: 3418; P9BE: # %bb.0: # %entry 3419; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3420; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3421; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3422; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3423; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3424; P9BE-NEXT: xvcvdpuxws v2, vs0 3425; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3426; P9BE-NEXT: xvcvdpuxws v3, vs0 3427; P9BE-NEXT: vmrgew v2, v3, v2 3428; P9BE-NEXT: blr 3429; 3430; P9LE-LABEL: fromRegsConvdtoui: 3431; P9LE: # %bb.0: # %entry 3432; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3433; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3434; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3435; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3436; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3437; P9LE-NEXT: xvcvdpuxws v2, vs0 3438; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3439; P9LE-NEXT: xvcvdpuxws v3, vs0 3440; P9LE-NEXT: vmrgew v2, v3, v2 3441; P9LE-NEXT: blr 3442; 3443; P8BE-LABEL: fromRegsConvdtoui: 3444; P8BE: # %bb.0: # %entry 3445; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3446; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3447; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3448; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3449; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3450; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3451; P8BE-NEXT: xvcvdpuxws v2, vs0 3452; P8BE-NEXT: xvcvdpuxws v3, vs1 3453; P8BE-NEXT: vmrgew v2, v3, v2 3454; P8BE-NEXT: blr 3455; 3456; P8LE-LABEL: fromRegsConvdtoui: 3457; P8LE: # %bb.0: # %entry 3458; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3459; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3460; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3461; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3462; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3463; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3464; P8LE-NEXT: xvcvdpuxws v2, vs0 3465; P8LE-NEXT: xvcvdpuxws v3, vs1 3466; P8LE-NEXT: vmrgew v2, v3, v2 3467; P8LE-NEXT: blr 3468entry: 3469 %conv = fptoui double %a to i32 3470 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3471 %conv1 = fptoui double %b to i32 3472 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3473 %conv3 = fptoui double %c to i32 3474 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3475 %conv5 = fptoui double %d to i32 3476 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3477 ret <4 x i32> %vecinit6 3478} 3479 3480; Function Attrs: norecurse nounwind readnone 3481define <4 x i32> @fromDiffConstsConvdtoui() { 3482; P9BE-LABEL: fromDiffConstsConvdtoui: 3483; P9BE: # %bb.0: # %entry 3484; P9BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3485; P9BE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3486; P9BE-NEXT: lxvx v2, 0, r3 3487; P9BE-NEXT: blr 3488; 3489; P9LE-LABEL: fromDiffConstsConvdtoui: 3490; P9LE: # %bb.0: # %entry 3491; P9LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3492; P9LE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3493; P9LE-NEXT: lxvx v2, 0, r3 3494; P9LE-NEXT: blr 3495; 3496; P8BE-LABEL: fromDiffConstsConvdtoui: 3497; P8BE: # %bb.0: # %entry 3498; P8BE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3499; P8BE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3500; P8BE-NEXT: lxvw4x v2, 0, r3 3501; P8BE-NEXT: blr 3502; 3503; P8LE-LABEL: fromDiffConstsConvdtoui: 3504; P8LE: # %bb.0: # %entry 3505; P8LE-NEXT: addis r3, r2, .LCPI59_0@toc@ha 3506; P8LE-NEXT: addi r3, r3, .LCPI59_0@toc@l 3507; P8LE-NEXT: lvx v2, 0, r3 3508; P8LE-NEXT: blr 3509entry: 3510 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3511} 3512 3513; Function Attrs: norecurse nounwind readonly 3514define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3515; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3516; P9BE: # %bb.0: # %entry 3517; P9BE-NEXT: lxv vs0, 0(r3) 3518; P9BE-NEXT: lxv vs1, 16(r3) 3519; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3520; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3521; P9BE-NEXT: xvcvdpuxws v2, vs2 3522; P9BE-NEXT: xvcvdpuxws v3, vs0 3523; P9BE-NEXT: vmrgew v2, v3, v2 3524; P9BE-NEXT: blr 3525; 3526; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3527; P9LE: # %bb.0: # %entry 3528; P9LE-NEXT: lxv vs0, 0(r3) 3529; P9LE-NEXT: lxv vs1, 16(r3) 3530; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3531; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3532; P9LE-NEXT: xvcvdpuxws v2, vs2 3533; P9LE-NEXT: xvcvdpuxws v3, vs0 3534; P9LE-NEXT: vmrgew v2, v3, v2 3535; P9LE-NEXT: blr 3536; 3537; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3538; P8BE: # %bb.0: # %entry 3539; P8BE-NEXT: li r4, 16 3540; P8BE-NEXT: lxvd2x vs0, 0, r3 3541; P8BE-NEXT: lxvd2x vs1, r3, r4 3542; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3543; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3544; P8BE-NEXT: xvcvdpuxws v2, vs2 3545; P8BE-NEXT: xvcvdpuxws v3, vs0 3546; P8BE-NEXT: vmrgew v2, v3, v2 3547; P8BE-NEXT: blr 3548; 3549; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3550; P8LE: # %bb.0: # %entry 3551; P8LE-NEXT: li r4, 16 3552; P8LE-NEXT: lxvd2x vs0, 0, r3 3553; P8LE-NEXT: lxvd2x vs1, r3, r4 3554; P8LE-NEXT: xxswapd vs0, vs0 3555; P8LE-NEXT: xxswapd vs1, vs1 3556; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3557; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3558; P8LE-NEXT: xvcvdpuxws v2, vs2 3559; P8LE-NEXT: xvcvdpuxws v3, vs0 3560; P8LE-NEXT: vmrgew v2, v3, v2 3561; P8LE-NEXT: blr 3562entry: 3563 %0 = bitcast double* %ptr to <2 x double>* 3564 %1 = load <2 x double>, <2 x double>* %0, align 8 3565 %2 = fptoui <2 x double> %1 to <2 x i32> 3566 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3567 %3 = bitcast double* %arrayidx4 to <2 x double>* 3568 %4 = load <2 x double>, <2 x double>* %3, align 8 3569 %5 = fptoui <2 x double> %4 to <2 x i32> 3570 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3571 ret <4 x i32> %vecinit9 3572} 3573 3574; Function Attrs: norecurse nounwind readonly 3575define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3576; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3577; P9BE: # %bb.0: # %entry 3578; P9BE-NEXT: lfd f0, 24(r3) 3579; P9BE-NEXT: lfd f1, 16(r3) 3580; P9BE-NEXT: lfd f2, 8(r3) 3581; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3582; P9BE-NEXT: lfd f3, 0(r3) 3583; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3584; P9BE-NEXT: xvcvdpuxws v2, vs1 3585; P9BE-NEXT: xvcvdpuxws v3, vs0 3586; P9BE-NEXT: vmrgew v2, v3, v2 3587; P9BE-NEXT: blr 3588; 3589; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3590; P9LE: # %bb.0: # %entry 3591; P9LE-NEXT: lfd f0, 24(r3) 3592; P9LE-NEXT: lfd f2, 8(r3) 3593; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3594; P9LE-NEXT: lfd f1, 16(r3) 3595; P9LE-NEXT: lfd f3, 0(r3) 3596; P9LE-NEXT: xvcvdpuxws v2, vs0 3597; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3598; P9LE-NEXT: xvcvdpuxws v3, vs0 3599; P9LE-NEXT: vmrgew v2, v3, v2 3600; P9LE-NEXT: blr 3601; 3602; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3603; P8BE: # %bb.0: # %entry 3604; P8BE-NEXT: lfdx f3, 0, r3 3605; P8BE-NEXT: lfd f0, 24(r3) 3606; P8BE-NEXT: lfd f1, 8(r3) 3607; P8BE-NEXT: lfd f2, 16(r3) 3608; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3609; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3610; P8BE-NEXT: xvcvdpuxws v2, vs0 3611; P8BE-NEXT: xvcvdpuxws v3, vs1 3612; P8BE-NEXT: vmrgew v2, v2, v3 3613; P8BE-NEXT: blr 3614; 3615; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3616; P8LE: # %bb.0: # %entry 3617; P8LE-NEXT: lfdx f3, 0, r3 3618; P8LE-NEXT: lfd f0, 24(r3) 3619; P8LE-NEXT: lfd f1, 8(r3) 3620; P8LE-NEXT: lfd f2, 16(r3) 3621; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3622; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3623; P8LE-NEXT: xvcvdpuxws v2, vs0 3624; P8LE-NEXT: xvcvdpuxws v3, vs1 3625; P8LE-NEXT: vmrgew v2, v3, v2 3626; P8LE-NEXT: blr 3627entry: 3628 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3629 %0 = load double, double* %arrayidx, align 8 3630 %conv = fptoui double %0 to i32 3631 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3632 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3633 %1 = load double, double* %arrayidx1, align 8 3634 %conv2 = fptoui double %1 to i32 3635 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3636 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3637 %2 = load double, double* %arrayidx4, align 8 3638 %conv5 = fptoui double %2 to i32 3639 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3640 %3 = load double, double* %ptr, align 8 3641 %conv8 = fptoui double %3 to i32 3642 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3643 ret <4 x i32> %vecinit9 3644} 3645 3646; Function Attrs: norecurse nounwind readonly 3647define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3648; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3649; P9BE: # %bb.0: # %entry 3650; P9BE-NEXT: sldi r4, r4, 3 3651; P9BE-NEXT: lfdux f0, r3, r4 3652; P9BE-NEXT: lfd f1, 8(r3) 3653; P9BE-NEXT: lfd f2, 16(r3) 3654; P9BE-NEXT: lfd f3, 24(r3) 3655; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3656; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3657; P9BE-NEXT: xvcvdpuxws v2, vs1 3658; P9BE-NEXT: xvcvdpuxws v3, vs0 3659; P9BE-NEXT: vmrgew v2, v3, v2 3660; P9BE-NEXT: blr 3661; 3662; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3663; P9LE: # %bb.0: # %entry 3664; P9LE-NEXT: sldi r4, r4, 3 3665; P9LE-NEXT: lfdux f0, r3, r4 3666; P9LE-NEXT: lfd f2, 16(r3) 3667; P9LE-NEXT: lfd f1, 8(r3) 3668; P9LE-NEXT: lfd f3, 24(r3) 3669; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3670; P9LE-NEXT: xvcvdpuxws v2, vs0 3671; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3672; P9LE-NEXT: xvcvdpuxws v3, vs0 3673; P9LE-NEXT: vmrgew v2, v3, v2 3674; P9LE-NEXT: blr 3675; 3676; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3677; P8BE: # %bb.0: # %entry 3678; P8BE-NEXT: sldi r4, r4, 3 3679; P8BE-NEXT: lfdux f0, r3, r4 3680; P8BE-NEXT: lfd f1, 8(r3) 3681; P8BE-NEXT: lfd f2, 24(r3) 3682; P8BE-NEXT: lfd f3, 16(r3) 3683; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3684; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3685; P8BE-NEXT: xvcvdpuxws v2, vs1 3686; P8BE-NEXT: xvcvdpuxws v3, vs0 3687; P8BE-NEXT: vmrgew v2, v3, v2 3688; P8BE-NEXT: blr 3689; 3690; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3691; P8LE: # %bb.0: # %entry 3692; P8LE-NEXT: sldi r4, r4, 3 3693; P8LE-NEXT: lfdux f0, r3, r4 3694; P8LE-NEXT: lfd f1, 16(r3) 3695; P8LE-NEXT: lfd f2, 8(r3) 3696; P8LE-NEXT: lfd f3, 24(r3) 3697; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3698; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3699; P8LE-NEXT: xvcvdpuxws v2, vs0 3700; P8LE-NEXT: xvcvdpuxws v3, vs1 3701; P8LE-NEXT: vmrgew v2, v3, v2 3702; P8LE-NEXT: blr 3703entry: 3704 %idxprom = sext i32 %elem to i64 3705 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3706 %0 = load double, double* %arrayidx, align 8 3707 %conv = fptoui double %0 to i32 3708 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3709 %add = add nsw i32 %elem, 1 3710 %idxprom1 = sext i32 %add to i64 3711 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3712 %1 = load double, double* %arrayidx2, align 8 3713 %conv3 = fptoui double %1 to i32 3714 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3715 %add5 = add nsw i32 %elem, 2 3716 %idxprom6 = sext i32 %add5 to i64 3717 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3718 %2 = load double, double* %arrayidx7, align 8 3719 %conv8 = fptoui double %2 to i32 3720 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3721 %add10 = add nsw i32 %elem, 3 3722 %idxprom11 = sext i32 %add10 to i64 3723 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3724 %3 = load double, double* %arrayidx12, align 8 3725 %conv13 = fptoui double %3 to i32 3726 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3727 ret <4 x i32> %vecinit14 3728} 3729 3730; Function Attrs: norecurse nounwind readonly 3731define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3732; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3733; P9BE: # %bb.0: # %entry 3734; P9BE-NEXT: sldi r4, r4, 3 3735; P9BE-NEXT: lfdux f0, r3, r4 3736; P9BE-NEXT: lfd f1, -8(r3) 3737; P9BE-NEXT: lfd f2, -16(r3) 3738; P9BE-NEXT: lfd f3, -24(r3) 3739; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3740; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3741; P9BE-NEXT: xvcvdpuxws v2, vs1 3742; P9BE-NEXT: xvcvdpuxws v3, vs0 3743; P9BE-NEXT: vmrgew v2, v3, v2 3744; P9BE-NEXT: blr 3745; 3746; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3747; P9LE: # %bb.0: # %entry 3748; P9LE-NEXT: sldi r4, r4, 3 3749; P9LE-NEXT: lfdux f0, r3, r4 3750; P9LE-NEXT: lfd f2, -16(r3) 3751; P9LE-NEXT: lfd f1, -8(r3) 3752; P9LE-NEXT: lfd f3, -24(r3) 3753; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3754; P9LE-NEXT: xvcvdpuxws v2, vs0 3755; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3756; P9LE-NEXT: xvcvdpuxws v3, vs0 3757; P9LE-NEXT: vmrgew v2, v3, v2 3758; P9LE-NEXT: blr 3759; 3760; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3761; P8BE: # %bb.0: # %entry 3762; P8BE-NEXT: sldi r4, r4, 3 3763; P8BE-NEXT: lfdux f0, r3, r4 3764; P8BE-NEXT: lfd f1, -8(r3) 3765; P8BE-NEXT: lfd f2, -24(r3) 3766; P8BE-NEXT: lfd f3, -16(r3) 3767; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3768; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3769; P8BE-NEXT: xvcvdpuxws v2, vs1 3770; P8BE-NEXT: xvcvdpuxws v3, vs0 3771; P8BE-NEXT: vmrgew v2, v3, v2 3772; P8BE-NEXT: blr 3773; 3774; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3775; P8LE: # %bb.0: # %entry 3776; P8LE-NEXT: sldi r4, r4, 3 3777; P8LE-NEXT: lfdux f0, r3, r4 3778; P8LE-NEXT: lfd f1, -16(r3) 3779; P8LE-NEXT: lfd f2, -8(r3) 3780; P8LE-NEXT: lfd f3, -24(r3) 3781; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3782; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3783; P8LE-NEXT: xvcvdpuxws v2, vs0 3784; P8LE-NEXT: xvcvdpuxws v3, vs1 3785; P8LE-NEXT: vmrgew v2, v3, v2 3786; P8LE-NEXT: blr 3787entry: 3788 %idxprom = sext i32 %elem to i64 3789 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3790 %0 = load double, double* %arrayidx, align 8 3791 %conv = fptoui double %0 to i32 3792 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3793 %sub = add nsw i32 %elem, -1 3794 %idxprom1 = sext i32 %sub to i64 3795 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3796 %1 = load double, double* %arrayidx2, align 8 3797 %conv3 = fptoui double %1 to i32 3798 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3799 %sub5 = add nsw i32 %elem, -2 3800 %idxprom6 = sext i32 %sub5 to i64 3801 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3802 %2 = load double, double* %arrayidx7, align 8 3803 %conv8 = fptoui double %2 to i32 3804 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3805 %sub10 = add nsw i32 %elem, -3 3806 %idxprom11 = sext i32 %sub10 to i64 3807 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3808 %3 = load double, double* %arrayidx12, align 8 3809 %conv13 = fptoui double %3 to i32 3810 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3811 ret <4 x i32> %vecinit14 3812} 3813 3814; Function Attrs: norecurse nounwind readnone 3815define <4 x i32> @spltRegValConvdtoui(double %val) { 3816; P9BE-LABEL: spltRegValConvdtoui: 3817; P9BE: # %bb.0: # %entry 3818; P9BE-NEXT: xscvdpuxws f0, f1 3819; P9BE-NEXT: xxspltw v2, vs0, 1 3820; P9BE-NEXT: blr 3821; 3822; P9LE-LABEL: spltRegValConvdtoui: 3823; P9LE: # %bb.0: # %entry 3824; P9LE-NEXT: xscvdpuxws f0, f1 3825; P9LE-NEXT: xxspltw v2, vs0, 1 3826; P9LE-NEXT: blr 3827; 3828; P8BE-LABEL: spltRegValConvdtoui: 3829; P8BE: # %bb.0: # %entry 3830; P8BE-NEXT: xscvdpuxws f0, f1 3831; P8BE-NEXT: xxspltw v2, vs0, 1 3832; P8BE-NEXT: blr 3833; 3834; P8LE-LABEL: spltRegValConvdtoui: 3835; P8LE: # %bb.0: # %entry 3836; P8LE-NEXT: xscvdpuxws f0, f1 3837; P8LE-NEXT: xxspltw v2, vs0, 1 3838; P8LE-NEXT: blr 3839entry: 3840 %conv = fptoui double %val to i32 3841 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3842 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3843 ret <4 x i32> %splat.splat 3844} 3845 3846; Function Attrs: norecurse nounwind readonly 3847define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3848; P9BE-LABEL: spltMemValConvdtoui: 3849; P9BE: # %bb.0: # %entry 3850; P9BE-NEXT: lfd f0, 0(r3) 3851; P9BE-NEXT: xscvdpuxws f0, f0 3852; P9BE-NEXT: xxspltw v2, vs0, 1 3853; P9BE-NEXT: blr 3854; 3855; P9LE-LABEL: spltMemValConvdtoui: 3856; P9LE: # %bb.0: # %entry 3857; P9LE-NEXT: lfd f0, 0(r3) 3858; P9LE-NEXT: xscvdpuxws f0, f0 3859; P9LE-NEXT: xxspltw v2, vs0, 1 3860; P9LE-NEXT: blr 3861; 3862; P8BE-LABEL: spltMemValConvdtoui: 3863; P8BE: # %bb.0: # %entry 3864; P8BE-NEXT: lfdx f0, 0, r3 3865; P8BE-NEXT: xscvdpuxws f0, f0 3866; P8BE-NEXT: xxspltw v2, vs0, 1 3867; P8BE-NEXT: blr 3868; 3869; P8LE-LABEL: spltMemValConvdtoui: 3870; P8LE: # %bb.0: # %entry 3871; P8LE-NEXT: lfdx f0, 0, r3 3872; P8LE-NEXT: xscvdpuxws f0, f0 3873; P8LE-NEXT: xxspltw v2, vs0, 1 3874; P8LE-NEXT: blr 3875entry: 3876 %0 = load double, double* %ptr, align 8 3877 %conv = fptoui double %0 to i32 3878 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3879 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3880 ret <4 x i32> %splat.splat 3881} 3882; Function Attrs: norecurse nounwind readnone 3883define <2 x i64> @allZeroll() { 3884; P9BE-LABEL: allZeroll: 3885; P9BE: # %bb.0: # %entry 3886; P9BE-NEXT: xxlxor v2, v2, v2 3887; P9BE-NEXT: blr 3888; 3889; P9LE-LABEL: allZeroll: 3890; P9LE: # %bb.0: # %entry 3891; P9LE-NEXT: xxlxor v2, v2, v2 3892; P9LE-NEXT: blr 3893; 3894; P8BE-LABEL: allZeroll: 3895; P8BE: # %bb.0: # %entry 3896; P8BE-NEXT: xxlxor v2, v2, v2 3897; P8BE-NEXT: blr 3898; 3899; P8LE-LABEL: allZeroll: 3900; P8LE: # %bb.0: # %entry 3901; P8LE-NEXT: xxlxor v2, v2, v2 3902; P8LE-NEXT: blr 3903entry: 3904 ret <2 x i64> zeroinitializer 3905} 3906 3907; Function Attrs: norecurse nounwind readnone 3908define <2 x i64> @allOnell() { 3909; P9BE-LABEL: allOnell: 3910; P9BE: # %bb.0: # %entry 3911; P9BE-NEXT: xxspltib v2, 255 3912; P9BE-NEXT: blr 3913; 3914; P9LE-LABEL: allOnell: 3915; P9LE: # %bb.0: # %entry 3916; P9LE-NEXT: xxspltib v2, 255 3917; P9LE-NEXT: blr 3918; 3919; P8BE-LABEL: allOnell: 3920; P8BE: # %bb.0: # %entry 3921; P8BE-NEXT: vspltisb v2, -1 3922; P8BE-NEXT: blr 3923; 3924; P8LE-LABEL: allOnell: 3925; P8LE: # %bb.0: # %entry 3926; P8LE-NEXT: vspltisb v2, -1 3927; P8LE-NEXT: blr 3928entry: 3929 ret <2 x i64> <i64 -1, i64 -1> 3930} 3931 3932; Function Attrs: norecurse nounwind readnone 3933define <2 x i64> @spltConst1ll() { 3934; P9BE-LABEL: spltConst1ll: 3935; P9BE: # %bb.0: # %entry 3936; P9BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3937; P9BE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3938; P9BE-NEXT: lxvx v2, 0, r3 3939; P9BE-NEXT: blr 3940; 3941; P9LE-LABEL: spltConst1ll: 3942; P9LE: # %bb.0: # %entry 3943; P9LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3944; P9LE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3945; P9LE-NEXT: lxvx v2, 0, r3 3946; P9LE-NEXT: blr 3947; 3948; P8BE-LABEL: spltConst1ll: 3949; P8BE: # %bb.0: # %entry 3950; P8BE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3951; P8BE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3952; P8BE-NEXT: lxvd2x v2, 0, r3 3953; P8BE-NEXT: blr 3954; 3955; P8LE-LABEL: spltConst1ll: 3956; P8LE: # %bb.0: # %entry 3957; P8LE-NEXT: addis r3, r2, .LCPI68_0@toc@ha 3958; P8LE-NEXT: addi r3, r3, .LCPI68_0@toc@l 3959; P8LE-NEXT: lxvd2x vs0, 0, r3 3960; P8LE-NEXT: xxswapd v2, vs0 3961; P8LE-NEXT: blr 3962entry: 3963 ret <2 x i64> <i64 1, i64 1> 3964} 3965 3966; Function Attrs: norecurse nounwind readnone 3967define <2 x i64> @spltConst16kll() { 3968; P9BE-LABEL: spltConst16kll: 3969; P9BE: # %bb.0: # %entry 3970; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3971; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3972; P9BE-NEXT: lxvx v2, 0, r3 3973; P9BE-NEXT: blr 3974; 3975; P9LE-LABEL: spltConst16kll: 3976; P9LE: # %bb.0: # %entry 3977; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3978; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3979; P9LE-NEXT: lxvx v2, 0, r3 3980; P9LE-NEXT: blr 3981; 3982; P8BE-LABEL: spltConst16kll: 3983; P8BE: # %bb.0: # %entry 3984; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3985; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3986; P8BE-NEXT: lxvd2x v2, 0, r3 3987; P8BE-NEXT: blr 3988; 3989; P8LE-LABEL: spltConst16kll: 3990; P8LE: # %bb.0: # %entry 3991; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3992; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3993; P8LE-NEXT: lxvd2x vs0, 0, r3 3994; P8LE-NEXT: xxswapd v2, vs0 3995; P8LE-NEXT: blr 3996entry: 3997 ret <2 x i64> <i64 32767, i64 32767> 3998} 3999 4000; Function Attrs: norecurse nounwind readnone 4001define <2 x i64> @spltConst32kll() { 4002; P9BE-LABEL: spltConst32kll: 4003; P9BE: # %bb.0: # %entry 4004; P9BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4005; P9BE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4006; P9BE-NEXT: lxvx v2, 0, r3 4007; P9BE-NEXT: blr 4008; 4009; P9LE-LABEL: spltConst32kll: 4010; P9LE: # %bb.0: # %entry 4011; P9LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4012; P9LE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4013; P9LE-NEXT: lxvx v2, 0, r3 4014; P9LE-NEXT: blr 4015; 4016; P8BE-LABEL: spltConst32kll: 4017; P8BE: # %bb.0: # %entry 4018; P8BE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4019; P8BE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4020; P8BE-NEXT: lxvd2x v2, 0, r3 4021; P8BE-NEXT: blr 4022; 4023; P8LE-LABEL: spltConst32kll: 4024; P8LE: # %bb.0: # %entry 4025; P8LE-NEXT: addis r3, r2, .LCPI70_0@toc@ha 4026; P8LE-NEXT: addi r3, r3, .LCPI70_0@toc@l 4027; P8LE-NEXT: lxvd2x vs0, 0, r3 4028; P8LE-NEXT: xxswapd v2, vs0 4029; P8LE-NEXT: blr 4030entry: 4031 ret <2 x i64> <i64 65535, i64 65535> 4032} 4033 4034; Function Attrs: norecurse nounwind readnone 4035define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 4036; P9BE-LABEL: fromRegsll: 4037; P9BE: # %bb.0: # %entry 4038; P9BE-NEXT: mtvsrdd v2, r3, r4 4039; P9BE-NEXT: blr 4040; 4041; P9LE-LABEL: fromRegsll: 4042; P9LE: # %bb.0: # %entry 4043; P9LE-NEXT: mtvsrdd v2, r4, r3 4044; P9LE-NEXT: blr 4045; 4046; P8BE-LABEL: fromRegsll: 4047; P8BE: # %bb.0: # %entry 4048; P8BE-NEXT: mtvsrd f0, r4 4049; P8BE-NEXT: mtvsrd f1, r3 4050; P8BE-NEXT: xxmrghd v2, vs1, vs0 4051; P8BE-NEXT: blr 4052; 4053; P8LE-LABEL: fromRegsll: 4054; P8LE: # %bb.0: # %entry 4055; P8LE-NEXT: mtvsrd f0, r3 4056; P8LE-NEXT: mtvsrd f1, r4 4057; P8LE-NEXT: xxmrghd v2, vs1, vs0 4058; P8LE-NEXT: blr 4059entry: 4060 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 4061 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 4062 ret <2 x i64> %vecinit1 4063} 4064 4065; Function Attrs: norecurse nounwind readnone 4066define <2 x i64> @fromDiffConstsll() { 4067; P9BE-LABEL: fromDiffConstsll: 4068; P9BE: # %bb.0: # %entry 4069; P9BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4070; P9BE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4071; P9BE-NEXT: lxvx v2, 0, r3 4072; P9BE-NEXT: blr 4073; 4074; P9LE-LABEL: fromDiffConstsll: 4075; P9LE: # %bb.0: # %entry 4076; P9LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4077; P9LE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4078; P9LE-NEXT: lxvx v2, 0, r3 4079; P9LE-NEXT: blr 4080; 4081; P8BE-LABEL: fromDiffConstsll: 4082; P8BE: # %bb.0: # %entry 4083; P8BE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4084; P8BE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4085; P8BE-NEXT: lxvd2x v2, 0, r3 4086; P8BE-NEXT: blr 4087; 4088; P8LE-LABEL: fromDiffConstsll: 4089; P8LE: # %bb.0: # %entry 4090; P8LE-NEXT: addis r3, r2, .LCPI72_0@toc@ha 4091; P8LE-NEXT: addi r3, r3, .LCPI72_0@toc@l 4092; P8LE-NEXT: lxvd2x vs0, 0, r3 4093; P8LE-NEXT: xxswapd v2, vs0 4094; P8LE-NEXT: blr 4095entry: 4096 ret <2 x i64> <i64 242, i64 -113> 4097} 4098 4099; Function Attrs: norecurse nounwind readonly 4100define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 4101; P9BE-LABEL: fromDiffMemConsAll: 4102; P9BE: # %bb.0: # %entry 4103; P9BE-NEXT: lxv v2, 0(r3) 4104; P9BE-NEXT: blr 4105; 4106; P9LE-LABEL: fromDiffMemConsAll: 4107; P9LE: # %bb.0: # %entry 4108; P9LE-NEXT: lxv v2, 0(r3) 4109; P9LE-NEXT: blr 4110; 4111; P8BE-LABEL: fromDiffMemConsAll: 4112; P8BE: # %bb.0: # %entry 4113; P8BE-NEXT: lxvd2x v2, 0, r3 4114; P8BE-NEXT: blr 4115; 4116; P8LE-LABEL: fromDiffMemConsAll: 4117; P8LE: # %bb.0: # %entry 4118; P8LE-NEXT: lxvd2x vs0, 0, r3 4119; P8LE-NEXT: xxswapd v2, vs0 4120; P8LE-NEXT: blr 4121entry: 4122 %0 = load i64, i64* %arr, align 8 4123 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4124 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 4125 %1 = load i64, i64* %arrayidx1, align 8 4126 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4127 ret <2 x i64> %vecinit2 4128} 4129 4130; Function Attrs: norecurse nounwind readonly 4131define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 4132; P9BE-LABEL: fromDiffMemConsDll: 4133; P9BE: # %bb.0: # %entry 4134; P9BE-NEXT: lxv v2, 16(r3) 4135; P9BE-NEXT: xxswapd v2, v2 4136; P9BE-NEXT: blr 4137; 4138; P9LE-LABEL: fromDiffMemConsDll: 4139; P9LE: # %bb.0: # %entry 4140; P9LE-NEXT: addi r3, r3, 16 4141; P9LE-NEXT: lxvd2x v2, 0, r3 4142; P9LE-NEXT: blr 4143; 4144; P8BE-LABEL: fromDiffMemConsDll: 4145; P8BE: # %bb.0: # %entry 4146; P8BE-NEXT: addi r3, r3, 16 4147; P8BE-NEXT: lxvd2x v2, 0, r3 4148; P8BE-NEXT: xxswapd v2, v2 4149; P8BE-NEXT: blr 4150; 4151; P8LE-LABEL: fromDiffMemConsDll: 4152; P8LE: # %bb.0: # %entry 4153; P8LE-NEXT: addi r3, r3, 16 4154; P8LE-NEXT: lxvd2x v2, 0, r3 4155; P8LE-NEXT: blr 4156entry: 4157 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 4158 %0 = load i64, i64* %arrayidx, align 8 4159 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4160 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 4161 %1 = load i64, i64* %arrayidx1, align 8 4162 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4163 ret <2 x i64> %vecinit2 4164} 4165 4166; Function Attrs: norecurse nounwind readonly 4167define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4168; P9BE-LABEL: fromDiffMemVarAll: 4169; P9BE: # %bb.0: # %entry 4170; P9BE-NEXT: sldi r4, r4, 3 4171; P9BE-NEXT: lxvx v2, r3, r4 4172; P9BE-NEXT: blr 4173; 4174; P9LE-LABEL: fromDiffMemVarAll: 4175; P9LE: # %bb.0: # %entry 4176; P9LE-NEXT: sldi r4, r4, 3 4177; P9LE-NEXT: lxvx v2, r3, r4 4178; P9LE-NEXT: blr 4179; 4180; P8BE-LABEL: fromDiffMemVarAll: 4181; P8BE: # %bb.0: # %entry 4182; P8BE-NEXT: sldi r4, r4, 3 4183; P8BE-NEXT: lxvd2x v2, r3, r4 4184; P8BE-NEXT: blr 4185; 4186; P8LE-LABEL: fromDiffMemVarAll: 4187; P8LE: # %bb.0: # %entry 4188; P8LE-NEXT: sldi r4, r4, 3 4189; P8LE-NEXT: lxvd2x vs0, r3, r4 4190; P8LE-NEXT: xxswapd v2, vs0 4191; P8LE-NEXT: blr 4192entry: 4193 %idxprom = sext i32 %elem to i64 4194 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4195 %0 = load i64, i64* %arrayidx, align 8 4196 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4197 %add = add nsw i32 %elem, 1 4198 %idxprom1 = sext i32 %add to i64 4199 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4200 %1 = load i64, i64* %arrayidx2, align 8 4201 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4202 ret <2 x i64> %vecinit3 4203} 4204 4205; Function Attrs: norecurse nounwind readonly 4206define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4207; P9BE-LABEL: fromDiffMemVarDll: 4208; P9BE: # %bb.0: # %entry 4209; P9BE-NEXT: sldi r4, r4, 3 4210; P9BE-NEXT: add r3, r3, r4 4211; P9BE-NEXT: li r4, -8 4212; P9BE-NEXT: lxvx v2, r3, r4 4213; P9BE-NEXT: xxswapd v2, v2 4214; P9BE-NEXT: blr 4215; 4216; P9LE-LABEL: fromDiffMemVarDll: 4217; P9LE: # %bb.0: # %entry 4218; P9LE-NEXT: sldi r4, r4, 3 4219; P9LE-NEXT: add r3, r3, r4 4220; P9LE-NEXT: addi r3, r3, -8 4221; P9LE-NEXT: lxvd2x v2, 0, r3 4222; P9LE-NEXT: blr 4223; 4224; P8BE-LABEL: fromDiffMemVarDll: 4225; P8BE: # %bb.0: # %entry 4226; P8BE-NEXT: sldi r4, r4, 3 4227; P8BE-NEXT: add r3, r3, r4 4228; P8BE-NEXT: addi r3, r3, -8 4229; P8BE-NEXT: lxvd2x v2, 0, r3 4230; P8BE-NEXT: xxswapd v2, v2 4231; P8BE-NEXT: blr 4232; 4233; P8LE-LABEL: fromDiffMemVarDll: 4234; P8LE: # %bb.0: # %entry 4235; P8LE-NEXT: sldi r4, r4, 3 4236; P8LE-NEXT: add r3, r3, r4 4237; P8LE-NEXT: addi r3, r3, -8 4238; P8LE-NEXT: lxvd2x v2, 0, r3 4239; P8LE-NEXT: blr 4240entry: 4241 %idxprom = sext i32 %elem to i64 4242 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4243 %0 = load i64, i64* %arrayidx, align 8 4244 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4245 %sub = add nsw i32 %elem, -1 4246 %idxprom1 = sext i32 %sub to i64 4247 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4248 %1 = load i64, i64* %arrayidx2, align 8 4249 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4250 ret <2 x i64> %vecinit3 4251} 4252 4253; Function Attrs: norecurse nounwind readonly 4254define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4255; P9BE-LABEL: fromRandMemConsll: 4256; P9BE: # %bb.0: # %entry 4257; P9BE-NEXT: ld r4, 32(r3) 4258; P9BE-NEXT: ld r3, 144(r3) 4259; P9BE-NEXT: mtvsrdd v2, r4, r3 4260; P9BE-NEXT: blr 4261; 4262; P9LE-LABEL: fromRandMemConsll: 4263; P9LE: # %bb.0: # %entry 4264; P9LE-NEXT: ld r4, 32(r3) 4265; P9LE-NEXT: ld r3, 144(r3) 4266; P9LE-NEXT: mtvsrdd v2, r3, r4 4267; P9LE-NEXT: blr 4268; 4269; P8BE-LABEL: fromRandMemConsll: 4270; P8BE: # %bb.0: # %entry 4271; P8BE-NEXT: ld r4, 144(r3) 4272; P8BE-NEXT: ld r3, 32(r3) 4273; P8BE-NEXT: mtvsrd f0, r4 4274; P8BE-NEXT: mtvsrd f1, r3 4275; P8BE-NEXT: xxmrghd v2, vs1, vs0 4276; P8BE-NEXT: blr 4277; 4278; P8LE-LABEL: fromRandMemConsll: 4279; P8LE: # %bb.0: # %entry 4280; P8LE-NEXT: ld r4, 32(r3) 4281; P8LE-NEXT: ld r3, 144(r3) 4282; P8LE-NEXT: mtvsrd f0, r4 4283; P8LE-NEXT: mtvsrd f1, r3 4284; P8LE-NEXT: xxmrghd v2, vs1, vs0 4285; P8LE-NEXT: blr 4286entry: 4287 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4288 %0 = load i64, i64* %arrayidx, align 8 4289 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4290 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4291 %1 = load i64, i64* %arrayidx1, align 8 4292 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4293 ret <2 x i64> %vecinit2 4294} 4295 4296; Function Attrs: norecurse nounwind readonly 4297define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4298; P9BE-LABEL: fromRandMemVarll: 4299; P9BE: # %bb.0: # %entry 4300; P9BE-NEXT: sldi r4, r4, 3 4301; P9BE-NEXT: add r3, r3, r4 4302; P9BE-NEXT: ld r4, 32(r3) 4303; P9BE-NEXT: ld r3, 8(r3) 4304; P9BE-NEXT: mtvsrdd v2, r4, r3 4305; P9BE-NEXT: blr 4306; 4307; P9LE-LABEL: fromRandMemVarll: 4308; P9LE: # %bb.0: # %entry 4309; P9LE-NEXT: sldi r4, r4, 3 4310; P9LE-NEXT: add r3, r3, r4 4311; P9LE-NEXT: ld r4, 32(r3) 4312; P9LE-NEXT: ld r3, 8(r3) 4313; P9LE-NEXT: mtvsrdd v2, r3, r4 4314; P9LE-NEXT: blr 4315; 4316; P8BE-LABEL: fromRandMemVarll: 4317; P8BE: # %bb.0: # %entry 4318; P8BE-NEXT: sldi r4, r4, 3 4319; P8BE-NEXT: add r3, r3, r4 4320; P8BE-NEXT: ld r4, 8(r3) 4321; P8BE-NEXT: ld r3, 32(r3) 4322; P8BE-NEXT: mtvsrd f0, r4 4323; P8BE-NEXT: mtvsrd f1, r3 4324; P8BE-NEXT: xxmrghd v2, vs1, vs0 4325; P8BE-NEXT: blr 4326; 4327; P8LE-LABEL: fromRandMemVarll: 4328; P8LE: # %bb.0: # %entry 4329; P8LE-NEXT: sldi r4, r4, 3 4330; P8LE-NEXT: add r3, r3, r4 4331; P8LE-NEXT: ld r4, 32(r3) 4332; P8LE-NEXT: ld r3, 8(r3) 4333; P8LE-NEXT: mtvsrd f0, r4 4334; P8LE-NEXT: mtvsrd f1, r3 4335; P8LE-NEXT: xxmrghd v2, vs1, vs0 4336; P8LE-NEXT: blr 4337entry: 4338 %add = add nsw i32 %elem, 4 4339 %idxprom = sext i32 %add to i64 4340 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4341 %0 = load i64, i64* %arrayidx, align 8 4342 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4343 %add1 = add nsw i32 %elem, 1 4344 %idxprom2 = sext i32 %add1 to i64 4345 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4346 %1 = load i64, i64* %arrayidx3, align 8 4347 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4348 ret <2 x i64> %vecinit4 4349} 4350 4351; Function Attrs: norecurse nounwind readnone 4352define <2 x i64> @spltRegValll(i64 %val) { 4353; P9BE-LABEL: spltRegValll: 4354; P9BE: # %bb.0: # %entry 4355; P9BE-NEXT: mtvsrdd v2, r3, r3 4356; P9BE-NEXT: blr 4357; 4358; P9LE-LABEL: spltRegValll: 4359; P9LE: # %bb.0: # %entry 4360; P9LE-NEXT: mtvsrdd v2, r3, r3 4361; P9LE-NEXT: blr 4362; 4363; P8BE-LABEL: spltRegValll: 4364; P8BE: # %bb.0: # %entry 4365; P8BE-NEXT: mtvsrd f0, r3 4366; P8BE-NEXT: xxspltd v2, vs0, 0 4367; P8BE-NEXT: blr 4368; 4369; P8LE-LABEL: spltRegValll: 4370; P8LE: # %bb.0: # %entry 4371; P8LE-NEXT: mtvsrd f0, r3 4372; P8LE-NEXT: xxspltd v2, vs0, 0 4373; P8LE-NEXT: blr 4374entry: 4375 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4376 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4377 ret <2 x i64> %splat.splat 4378} 4379 4380; Function Attrs: norecurse nounwind readonly 4381define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4382; P9BE-LABEL: spltMemValll: 4383; P9BE: # %bb.0: # %entry 4384; P9BE-NEXT: lxvdsx v2, 0, r3 4385; P9BE-NEXT: blr 4386; 4387; P9LE-LABEL: spltMemValll: 4388; P9LE: # %bb.0: # %entry 4389; P9LE-NEXT: lxvdsx v2, 0, r3 4390; P9LE-NEXT: blr 4391; 4392; P8BE-LABEL: spltMemValll: 4393; P8BE: # %bb.0: # %entry 4394; P8BE-NEXT: lxvdsx v2, 0, r3 4395; P8BE-NEXT: blr 4396; 4397; P8LE-LABEL: spltMemValll: 4398; P8LE: # %bb.0: # %entry 4399; P8LE-NEXT: lxvdsx v2, 0, r3 4400; P8LE-NEXT: blr 4401entry: 4402 %0 = load i64, i64* %ptr, align 8 4403 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4404 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4405 ret <2 x i64> %splat.splat 4406} 4407 4408; Function Attrs: norecurse nounwind readnone 4409define <2 x i64> @spltCnstConvftoll() { 4410; P9BE-LABEL: spltCnstConvftoll: 4411; P9BE: # %bb.0: # %entry 4412; P9BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4413; P9BE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4414; P9BE-NEXT: lxvx v2, 0, r3 4415; P9BE-NEXT: blr 4416; 4417; P9LE-LABEL: spltCnstConvftoll: 4418; P9LE: # %bb.0: # %entry 4419; P9LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4420; P9LE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4421; P9LE-NEXT: lxvx v2, 0, r3 4422; P9LE-NEXT: blr 4423; 4424; P8BE-LABEL: spltCnstConvftoll: 4425; P8BE: # %bb.0: # %entry 4426; P8BE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4427; P8BE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4428; P8BE-NEXT: lxvd2x v2, 0, r3 4429; P8BE-NEXT: blr 4430; 4431; P8LE-LABEL: spltCnstConvftoll: 4432; P8LE: # %bb.0: # %entry 4433; P8LE-NEXT: addis r3, r2, .LCPI81_0@toc@ha 4434; P8LE-NEXT: addi r3, r3, .LCPI81_0@toc@l 4435; P8LE-NEXT: lxvd2x vs0, 0, r3 4436; P8LE-NEXT: xxswapd v2, vs0 4437; P8LE-NEXT: blr 4438entry: 4439 ret <2 x i64> <i64 4, i64 4> 4440} 4441 4442; Function Attrs: norecurse nounwind readnone 4443define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4444; P9BE-LABEL: fromRegsConvftoll: 4445; P9BE: # %bb.0: # %entry 4446; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4447; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4448; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4449; P9BE-NEXT: xvcvdpsxds v2, vs0 4450; P9BE-NEXT: blr 4451; 4452; P9LE-LABEL: fromRegsConvftoll: 4453; P9LE: # %bb.0: # %entry 4454; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4455; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4456; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4457; P9LE-NEXT: xvcvdpsxds v2, vs0 4458; P9LE-NEXT: blr 4459; 4460; P8BE-LABEL: fromRegsConvftoll: 4461; P8BE: # %bb.0: # %entry 4462; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4463; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4464; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4465; P8BE-NEXT: xvcvdpsxds v2, vs0 4466; P8BE-NEXT: blr 4467; 4468; P8LE-LABEL: fromRegsConvftoll: 4469; P8LE: # %bb.0: # %entry 4470; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4471; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4472; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4473; P8LE-NEXT: xvcvdpsxds v2, vs0 4474; P8LE-NEXT: blr 4475entry: 4476 %conv = fptosi float %a to i64 4477 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4478 %conv1 = fptosi float %b to i64 4479 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4480 ret <2 x i64> %vecinit2 4481} 4482 4483; Function Attrs: norecurse nounwind readnone 4484define <2 x i64> @fromDiffConstsConvftoll() { 4485; P9BE-LABEL: fromDiffConstsConvftoll: 4486; P9BE: # %bb.0: # %entry 4487; P9BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4488; P9BE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4489; P9BE-NEXT: lxvx v2, 0, r3 4490; P9BE-NEXT: blr 4491; 4492; P9LE-LABEL: fromDiffConstsConvftoll: 4493; P9LE: # %bb.0: # %entry 4494; P9LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4495; P9LE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4496; P9LE-NEXT: lxvx v2, 0, r3 4497; P9LE-NEXT: blr 4498; 4499; P8BE-LABEL: fromDiffConstsConvftoll: 4500; P8BE: # %bb.0: # %entry 4501; P8BE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4502; P8BE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4503; P8BE-NEXT: lxvd2x v2, 0, r3 4504; P8BE-NEXT: blr 4505; 4506; P8LE-LABEL: fromDiffConstsConvftoll: 4507; P8LE: # %bb.0: # %entry 4508; P8LE-NEXT: addis r3, r2, .LCPI83_0@toc@ha 4509; P8LE-NEXT: addi r3, r3, .LCPI83_0@toc@l 4510; P8LE-NEXT: lxvd2x vs0, 0, r3 4511; P8LE-NEXT: xxswapd v2, vs0 4512; P8LE-NEXT: blr 4513entry: 4514 ret <2 x i64> <i64 24, i64 234> 4515} 4516 4517; Function Attrs: norecurse nounwind readonly 4518define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4519; P9BE-LABEL: fromDiffMemConsAConvftoll: 4520; P9BE: # %bb.0: # %entry 4521; P9BE-NEXT: lfs f0, 0(r3) 4522; P9BE-NEXT: lfs f1, 4(r3) 4523; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4524; P9BE-NEXT: xvcvdpsxds v2, vs0 4525; P9BE-NEXT: blr 4526; 4527; P9LE-LABEL: fromDiffMemConsAConvftoll: 4528; P9LE: # %bb.0: # %entry 4529; P9LE-NEXT: lfs f0, 0(r3) 4530; P9LE-NEXT: lfs f1, 4(r3) 4531; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4532; P9LE-NEXT: xvcvdpsxds v2, vs0 4533; P9LE-NEXT: blr 4534; 4535; P8BE-LABEL: fromDiffMemConsAConvftoll: 4536; P8BE: # %bb.0: # %entry 4537; P8BE-NEXT: lfsx f0, 0, r3 4538; P8BE-NEXT: lfs f1, 4(r3) 4539; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4540; P8BE-NEXT: xvcvdpsxds v2, vs0 4541; P8BE-NEXT: blr 4542; 4543; P8LE-LABEL: fromDiffMemConsAConvftoll: 4544; P8LE: # %bb.0: # %entry 4545; P8LE-NEXT: lfsx f0, 0, r3 4546; P8LE-NEXT: lfs f1, 4(r3) 4547; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4548; P8LE-NEXT: xvcvdpsxds v2, vs0 4549; P8LE-NEXT: blr 4550entry: 4551 %0 = load float, float* %ptr, align 4 4552 %conv = fptosi float %0 to i64 4553 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4554 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4555 %1 = load float, float* %arrayidx1, align 4 4556 %conv2 = fptosi float %1 to i64 4557 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4558 ret <2 x i64> %vecinit3 4559} 4560 4561; Function Attrs: norecurse nounwind readonly 4562define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4563; P9BE-LABEL: fromDiffMemConsDConvftoll: 4564; P9BE: # %bb.0: # %entry 4565; P9BE-NEXT: lfs f0, 12(r3) 4566; P9BE-NEXT: lfs f1, 8(r3) 4567; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4568; P9BE-NEXT: xvcvdpsxds v2, vs0 4569; P9BE-NEXT: blr 4570; 4571; P9LE-LABEL: fromDiffMemConsDConvftoll: 4572; P9LE: # %bb.0: # %entry 4573; P9LE-NEXT: lfs f0, 12(r3) 4574; P9LE-NEXT: lfs f1, 8(r3) 4575; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4576; P9LE-NEXT: xvcvdpsxds v2, vs0 4577; P9LE-NEXT: blr 4578; 4579; P8BE-LABEL: fromDiffMemConsDConvftoll: 4580; P8BE: # %bb.0: # %entry 4581; P8BE-NEXT: lfs f0, 12(r3) 4582; P8BE-NEXT: lfs f1, 8(r3) 4583; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4584; P8BE-NEXT: xvcvdpsxds v2, vs0 4585; P8BE-NEXT: blr 4586; 4587; P8LE-LABEL: fromDiffMemConsDConvftoll: 4588; P8LE: # %bb.0: # %entry 4589; P8LE-NEXT: lfs f0, 12(r3) 4590; P8LE-NEXT: lfs f1, 8(r3) 4591; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4592; P8LE-NEXT: xvcvdpsxds v2, vs0 4593; P8LE-NEXT: blr 4594entry: 4595 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4596 %0 = load float, float* %arrayidx, align 4 4597 %conv = fptosi float %0 to i64 4598 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4599 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4600 %1 = load float, float* %arrayidx1, align 4 4601 %conv2 = fptosi float %1 to i64 4602 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4603 ret <2 x i64> %vecinit3 4604} 4605 4606; Function Attrs: norecurse nounwind readonly 4607define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4608; P9BE-LABEL: fromDiffMemVarAConvftoll: 4609; P9BE: # %bb.0: # %entry 4610; P9BE-NEXT: sldi r4, r4, 2 4611; P9BE-NEXT: lfsux f0, r3, r4 4612; P9BE-NEXT: lfs f1, 4(r3) 4613; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4614; P9BE-NEXT: xvcvdpsxds v2, vs0 4615; P9BE-NEXT: blr 4616; 4617; P9LE-LABEL: fromDiffMemVarAConvftoll: 4618; P9LE: # %bb.0: # %entry 4619; P9LE-NEXT: sldi r4, r4, 2 4620; P9LE-NEXT: lfsux f0, r3, r4 4621; P9LE-NEXT: lfs f1, 4(r3) 4622; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4623; P9LE-NEXT: xvcvdpsxds v2, vs0 4624; P9LE-NEXT: blr 4625; 4626; P8BE-LABEL: fromDiffMemVarAConvftoll: 4627; P8BE: # %bb.0: # %entry 4628; P8BE-NEXT: sldi r4, r4, 2 4629; P8BE-NEXT: lfsux f0, r3, r4 4630; P8BE-NEXT: lfs f1, 4(r3) 4631; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4632; P8BE-NEXT: xvcvdpsxds v2, vs0 4633; P8BE-NEXT: blr 4634; 4635; P8LE-LABEL: fromDiffMemVarAConvftoll: 4636; P8LE: # %bb.0: # %entry 4637; P8LE-NEXT: sldi r4, r4, 2 4638; P8LE-NEXT: lfsux f0, r3, r4 4639; P8LE-NEXT: lfs f1, 4(r3) 4640; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4641; P8LE-NEXT: xvcvdpsxds v2, vs0 4642; P8LE-NEXT: blr 4643entry: 4644 %idxprom = sext i32 %elem to i64 4645 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4646 %0 = load float, float* %arrayidx, align 4 4647 %conv = fptosi float %0 to i64 4648 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4649 %add = add nsw i32 %elem, 1 4650 %idxprom1 = sext i32 %add to i64 4651 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4652 %1 = load float, float* %arrayidx2, align 4 4653 %conv3 = fptosi float %1 to i64 4654 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4655 ret <2 x i64> %vecinit4 4656} 4657 4658; Function Attrs: norecurse nounwind readonly 4659define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4660; P9BE-LABEL: fromDiffMemVarDConvftoll: 4661; P9BE: # %bb.0: # %entry 4662; P9BE-NEXT: sldi r4, r4, 2 4663; P9BE-NEXT: lfsux f0, r3, r4 4664; P9BE-NEXT: lfs f1, -4(r3) 4665; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4666; P9BE-NEXT: xvcvdpsxds v2, vs0 4667; P9BE-NEXT: blr 4668; 4669; P9LE-LABEL: fromDiffMemVarDConvftoll: 4670; P9LE: # %bb.0: # %entry 4671; P9LE-NEXT: sldi r4, r4, 2 4672; P9LE-NEXT: lfsux f0, r3, r4 4673; P9LE-NEXT: lfs f1, -4(r3) 4674; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4675; P9LE-NEXT: xvcvdpsxds v2, vs0 4676; P9LE-NEXT: blr 4677; 4678; P8BE-LABEL: fromDiffMemVarDConvftoll: 4679; P8BE: # %bb.0: # %entry 4680; P8BE-NEXT: sldi r4, r4, 2 4681; P8BE-NEXT: lfsux f0, r3, r4 4682; P8BE-NEXT: lfs f1, -4(r3) 4683; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4684; P8BE-NEXT: xvcvdpsxds v2, vs0 4685; P8BE-NEXT: blr 4686; 4687; P8LE-LABEL: fromDiffMemVarDConvftoll: 4688; P8LE: # %bb.0: # %entry 4689; P8LE-NEXT: sldi r4, r4, 2 4690; P8LE-NEXT: lfsux f0, r3, r4 4691; P8LE-NEXT: lfs f1, -4(r3) 4692; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4693; P8LE-NEXT: xvcvdpsxds v2, vs0 4694; P8LE-NEXT: blr 4695entry: 4696 %idxprom = sext i32 %elem to i64 4697 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4698 %0 = load float, float* %arrayidx, align 4 4699 %conv = fptosi float %0 to i64 4700 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4701 %sub = add nsw i32 %elem, -1 4702 %idxprom1 = sext i32 %sub to i64 4703 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4704 %1 = load float, float* %arrayidx2, align 4 4705 %conv3 = fptosi float %1 to i64 4706 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4707 ret <2 x i64> %vecinit4 4708} 4709 4710; Function Attrs: norecurse nounwind readnone 4711define <2 x i64> @spltRegValConvftoll(float %val) { 4712; P9BE-LABEL: spltRegValConvftoll: 4713; P9BE: # %bb.0: # %entry 4714; P9BE-NEXT: xscvdpsxds f0, f1 4715; P9BE-NEXT: xxspltd v2, f0, 0 4716; P9BE-NEXT: blr 4717; 4718; P9LE-LABEL: spltRegValConvftoll: 4719; P9LE: # %bb.0: # %entry 4720; P9LE-NEXT: xscvdpsxds f0, f1 4721; P9LE-NEXT: xxspltd v2, f0, 0 4722; P9LE-NEXT: blr 4723; 4724; P8BE-LABEL: spltRegValConvftoll: 4725; P8BE: # %bb.0: # %entry 4726; P8BE-NEXT: xscvdpsxds f0, f1 4727; P8BE-NEXT: xxspltd v2, f0, 0 4728; P8BE-NEXT: blr 4729; 4730; P8LE-LABEL: spltRegValConvftoll: 4731; P8LE: # %bb.0: # %entry 4732; P8LE-NEXT: xscvdpsxds f0, f1 4733; P8LE-NEXT: xxspltd v2, f0, 0 4734; P8LE-NEXT: blr 4735entry: 4736 %conv = fptosi float %val to i64 4737 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4738 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4739 ret <2 x i64> %splat.splat 4740} 4741 4742; Function Attrs: norecurse nounwind readonly 4743define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4744; P9BE-LABEL: spltMemValConvftoll: 4745; P9BE: # %bb.0: # %entry 4746; P9BE-NEXT: lfs f0, 0(r3) 4747; P9BE-NEXT: xscvdpsxds f0, f0 4748; P9BE-NEXT: xxspltd v2, f0, 0 4749; P9BE-NEXT: blr 4750; 4751; P9LE-LABEL: spltMemValConvftoll: 4752; P9LE: # %bb.0: # %entry 4753; P9LE-NEXT: lfs f0, 0(r3) 4754; P9LE-NEXT: xscvdpsxds f0, f0 4755; P9LE-NEXT: xxspltd v2, f0, 0 4756; P9LE-NEXT: blr 4757; 4758; P8BE-LABEL: spltMemValConvftoll: 4759; P8BE: # %bb.0: # %entry 4760; P8BE-NEXT: lfsx f0, 0, r3 4761; P8BE-NEXT: xscvdpsxds f0, f0 4762; P8BE-NEXT: xxspltd v2, f0, 0 4763; P8BE-NEXT: blr 4764; 4765; P8LE-LABEL: spltMemValConvftoll: 4766; P8LE: # %bb.0: # %entry 4767; P8LE-NEXT: lfsx f0, 0, r3 4768; P8LE-NEXT: xscvdpsxds f0, f0 4769; P8LE-NEXT: xxspltd v2, f0, 0 4770; P8LE-NEXT: blr 4771entry: 4772 %0 = load float, float* %ptr, align 4 4773 %conv = fptosi float %0 to i64 4774 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4775 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4776 ret <2 x i64> %splat.splat 4777} 4778 4779; Function Attrs: norecurse nounwind readnone 4780define <2 x i64> @spltCnstConvdtoll() { 4781; P9BE-LABEL: spltCnstConvdtoll: 4782; P9BE: # %bb.0: # %entry 4783; P9BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4784; P9BE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4785; P9BE-NEXT: lxvx v2, 0, r3 4786; P9BE-NEXT: blr 4787; 4788; P9LE-LABEL: spltCnstConvdtoll: 4789; P9LE: # %bb.0: # %entry 4790; P9LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4791; P9LE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4792; P9LE-NEXT: lxvx v2, 0, r3 4793; P9LE-NEXT: blr 4794; 4795; P8BE-LABEL: spltCnstConvdtoll: 4796; P8BE: # %bb.0: # %entry 4797; P8BE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4798; P8BE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4799; P8BE-NEXT: lxvd2x v2, 0, r3 4800; P8BE-NEXT: blr 4801; 4802; P8LE-LABEL: spltCnstConvdtoll: 4803; P8LE: # %bb.0: # %entry 4804; P8LE-NEXT: addis r3, r2, .LCPI90_0@toc@ha 4805; P8LE-NEXT: addi r3, r3, .LCPI90_0@toc@l 4806; P8LE-NEXT: lxvd2x vs0, 0, r3 4807; P8LE-NEXT: xxswapd v2, vs0 4808; P8LE-NEXT: blr 4809entry: 4810 ret <2 x i64> <i64 4, i64 4> 4811} 4812 4813; Function Attrs: norecurse nounwind readnone 4814define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4815; P9BE-LABEL: fromRegsConvdtoll: 4816; P9BE: # %bb.0: # %entry 4817; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4818; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4819; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4820; P9BE-NEXT: xvcvdpsxds v2, vs0 4821; P9BE-NEXT: blr 4822; 4823; P9LE-LABEL: fromRegsConvdtoll: 4824; P9LE: # %bb.0: # %entry 4825; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4826; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4827; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4828; P9LE-NEXT: xvcvdpsxds v2, vs0 4829; P9LE-NEXT: blr 4830; 4831; P8BE-LABEL: fromRegsConvdtoll: 4832; P8BE: # %bb.0: # %entry 4833; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4834; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4835; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4836; P8BE-NEXT: xvcvdpsxds v2, vs0 4837; P8BE-NEXT: blr 4838; 4839; P8LE-LABEL: fromRegsConvdtoll: 4840; P8LE: # %bb.0: # %entry 4841; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4842; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4843; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4844; P8LE-NEXT: xvcvdpsxds v2, vs0 4845; P8LE-NEXT: blr 4846entry: 4847 %conv = fptosi double %a to i64 4848 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4849 %conv1 = fptosi double %b to i64 4850 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4851 ret <2 x i64> %vecinit2 4852} 4853 4854; Function Attrs: norecurse nounwind readnone 4855define <2 x i64> @fromDiffConstsConvdtoll() { 4856; P9BE-LABEL: fromDiffConstsConvdtoll: 4857; P9BE: # %bb.0: # %entry 4858; P9BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4859; P9BE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4860; P9BE-NEXT: lxvx v2, 0, r3 4861; P9BE-NEXT: blr 4862; 4863; P9LE-LABEL: fromDiffConstsConvdtoll: 4864; P9LE: # %bb.0: # %entry 4865; P9LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4866; P9LE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4867; P9LE-NEXT: lxvx v2, 0, r3 4868; P9LE-NEXT: blr 4869; 4870; P8BE-LABEL: fromDiffConstsConvdtoll: 4871; P8BE: # %bb.0: # %entry 4872; P8BE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4873; P8BE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4874; P8BE-NEXT: lxvd2x v2, 0, r3 4875; P8BE-NEXT: blr 4876; 4877; P8LE-LABEL: fromDiffConstsConvdtoll: 4878; P8LE: # %bb.0: # %entry 4879; P8LE-NEXT: addis r3, r2, .LCPI92_0@toc@ha 4880; P8LE-NEXT: addi r3, r3, .LCPI92_0@toc@l 4881; P8LE-NEXT: lxvd2x vs0, 0, r3 4882; P8LE-NEXT: xxswapd v2, vs0 4883; P8LE-NEXT: blr 4884entry: 4885 ret <2 x i64> <i64 24, i64 234> 4886} 4887 4888; Function Attrs: norecurse nounwind readonly 4889define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4890; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4891; P9BE: # %bb.0: # %entry 4892; P9BE-NEXT: lxv vs0, 0(r3) 4893; P9BE-NEXT: xvcvdpsxds v2, vs0 4894; P9BE-NEXT: blr 4895; 4896; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4897; P9LE: # %bb.0: # %entry 4898; P9LE-NEXT: lxv vs0, 0(r3) 4899; P9LE-NEXT: xvcvdpsxds v2, vs0 4900; P9LE-NEXT: blr 4901; 4902; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4903; P8BE: # %bb.0: # %entry 4904; P8BE-NEXT: lxvd2x vs0, 0, r3 4905; P8BE-NEXT: xvcvdpsxds v2, vs0 4906; P8BE-NEXT: blr 4907; 4908; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4909; P8LE: # %bb.0: # %entry 4910; P8LE-NEXT: lxvd2x vs0, 0, r3 4911; P8LE-NEXT: xxswapd vs0, vs0 4912; P8LE-NEXT: xvcvdpsxds v2, vs0 4913; P8LE-NEXT: blr 4914entry: 4915 %0 = bitcast double* %ptr to <2 x double>* 4916 %1 = load <2 x double>, <2 x double>* %0, align 8 4917 %2 = fptosi <2 x double> %1 to <2 x i64> 4918 ret <2 x i64> %2 4919} 4920 4921; Function Attrs: norecurse nounwind readonly 4922define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4923; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4924; P9BE: # %bb.0: # %entry 4925; P9BE-NEXT: lxv vs0, 16(r3) 4926; P9BE-NEXT: xxswapd vs0, vs0 4927; P9BE-NEXT: xvcvdpsxds v2, vs0 4928; P9BE-NEXT: blr 4929; 4930; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4931; P9LE: # %bb.0: # %entry 4932; P9LE-NEXT: addi r3, r3, 16 4933; P9LE-NEXT: lxvd2x vs0, 0, r3 4934; P9LE-NEXT: xvcvdpsxds v2, vs0 4935; P9LE-NEXT: blr 4936; 4937; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4938; P8BE: # %bb.0: # %entry 4939; P8BE-NEXT: addi r3, r3, 16 4940; P8BE-NEXT: lxvd2x vs0, 0, r3 4941; P8BE-NEXT: xxswapd vs0, vs0 4942; P8BE-NEXT: xvcvdpsxds v2, vs0 4943; P8BE-NEXT: blr 4944; 4945; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4946; P8LE: # %bb.0: # %entry 4947; P8LE-NEXT: addi r3, r3, 16 4948; P8LE-NEXT: lxvd2x vs0, 0, r3 4949; P8LE-NEXT: xvcvdpsxds v2, vs0 4950; P8LE-NEXT: blr 4951entry: 4952 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4953 %0 = load double, double* %arrayidx, align 8 4954 %conv = fptosi double %0 to i64 4955 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4956 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4957 %1 = load double, double* %arrayidx1, align 8 4958 %conv2 = fptosi double %1 to i64 4959 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4960 ret <2 x i64> %vecinit3 4961} 4962 4963; Function Attrs: norecurse nounwind readonly 4964define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4965; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4966; P9BE: # %bb.0: # %entry 4967; P9BE-NEXT: sldi r4, r4, 3 4968; P9BE-NEXT: lxvx vs0, r3, r4 4969; P9BE-NEXT: xvcvdpsxds v2, vs0 4970; P9BE-NEXT: blr 4971; 4972; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4973; P9LE: # %bb.0: # %entry 4974; P9LE-NEXT: sldi r4, r4, 3 4975; P9LE-NEXT: lxvx vs0, r3, r4 4976; P9LE-NEXT: xvcvdpsxds v2, vs0 4977; P9LE-NEXT: blr 4978; 4979; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4980; P8BE: # %bb.0: # %entry 4981; P8BE-NEXT: sldi r4, r4, 3 4982; P8BE-NEXT: lxvd2x vs0, r3, r4 4983; P8BE-NEXT: xvcvdpsxds v2, vs0 4984; P8BE-NEXT: blr 4985; 4986; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4987; P8LE: # %bb.0: # %entry 4988; P8LE-NEXT: sldi r4, r4, 3 4989; P8LE-NEXT: lxvd2x vs0, r3, r4 4990; P8LE-NEXT: xxswapd vs0, vs0 4991; P8LE-NEXT: xvcvdpsxds v2, vs0 4992; P8LE-NEXT: blr 4993entry: 4994 %idxprom = sext i32 %elem to i64 4995 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4996 %0 = load double, double* %arrayidx, align 8 4997 %conv = fptosi double %0 to i64 4998 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4999 %add = add nsw i32 %elem, 1 5000 %idxprom1 = sext i32 %add to i64 5001 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 5002 %1 = load double, double* %arrayidx2, align 8 5003 %conv3 = fptosi double %1 to i64 5004 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5005 ret <2 x i64> %vecinit4 5006} 5007 5008; Function Attrs: norecurse nounwind readonly 5009define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 5010; P9BE-LABEL: fromDiffMemVarDConvdtoll: 5011; P9BE: # %bb.0: # %entry 5012; P9BE-NEXT: sldi r4, r4, 3 5013; P9BE-NEXT: add r3, r3, r4 5014; P9BE-NEXT: li r4, -8 5015; P9BE-NEXT: lxvx vs0, r3, r4 5016; P9BE-NEXT: xxswapd vs0, vs0 5017; P9BE-NEXT: xvcvdpsxds v2, vs0 5018; P9BE-NEXT: blr 5019; 5020; P9LE-LABEL: fromDiffMemVarDConvdtoll: 5021; P9LE: # %bb.0: # %entry 5022; P9LE-NEXT: sldi r4, r4, 3 5023; P9LE-NEXT: add r3, r3, r4 5024; P9LE-NEXT: addi r3, r3, -8 5025; P9LE-NEXT: lxvd2x vs0, 0, r3 5026; P9LE-NEXT: xvcvdpsxds v2, vs0 5027; P9LE-NEXT: blr 5028; 5029; P8BE-LABEL: fromDiffMemVarDConvdtoll: 5030; P8BE: # %bb.0: # %entry 5031; P8BE-NEXT: sldi r4, r4, 3 5032; P8BE-NEXT: add r3, r3, r4 5033; P8BE-NEXT: addi r3, r3, -8 5034; P8BE-NEXT: lxvd2x vs0, 0, r3 5035; P8BE-NEXT: xxswapd vs0, vs0 5036; P8BE-NEXT: xvcvdpsxds v2, vs0 5037; P8BE-NEXT: blr 5038; 5039; P8LE-LABEL: fromDiffMemVarDConvdtoll: 5040; P8LE: # %bb.0: # %entry 5041; P8LE-NEXT: sldi r4, r4, 3 5042; P8LE-NEXT: add r3, r3, r4 5043; P8LE-NEXT: addi r3, r3, -8 5044; P8LE-NEXT: lxvd2x vs0, 0, r3 5045; P8LE-NEXT: xvcvdpsxds v2, vs0 5046; P8LE-NEXT: blr 5047entry: 5048 %idxprom = sext i32 %elem to i64 5049 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 5050 %0 = load double, double* %arrayidx, align 8 5051 %conv = fptosi double %0 to i64 5052 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5053 %sub = add nsw i32 %elem, -1 5054 %idxprom1 = sext i32 %sub to i64 5055 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 5056 %1 = load double, double* %arrayidx2, align 8 5057 %conv3 = fptosi double %1 to i64 5058 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5059 ret <2 x i64> %vecinit4 5060} 5061 5062; Function Attrs: norecurse nounwind readnone 5063define <2 x i64> @spltRegValConvdtoll(double %val) { 5064; P9BE-LABEL: spltRegValConvdtoll: 5065; P9BE: # %bb.0: # %entry 5066; P9BE-NEXT: xscvdpsxds f0, f1 5067; P9BE-NEXT: xxspltd v2, vs0, 0 5068; P9BE-NEXT: blr 5069; 5070; P9LE-LABEL: spltRegValConvdtoll: 5071; P9LE: # %bb.0: # %entry 5072; P9LE-NEXT: xscvdpsxds f0, f1 5073; P9LE-NEXT: xxspltd v2, vs0, 0 5074; P9LE-NEXT: blr 5075; 5076; P8BE-LABEL: spltRegValConvdtoll: 5077; P8BE: # %bb.0: # %entry 5078; P8BE-NEXT: xscvdpsxds f0, f1 5079; P8BE-NEXT: xxspltd v2, vs0, 0 5080; P8BE-NEXT: blr 5081; 5082; P8LE-LABEL: spltRegValConvdtoll: 5083; P8LE: # %bb.0: # %entry 5084; P8LE-NEXT: xscvdpsxds f0, f1 5085; P8LE-NEXT: xxspltd v2, vs0, 0 5086; P8LE-NEXT: blr 5087entry: 5088 %conv = fptosi double %val to i64 5089 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5090 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5091 ret <2 x i64> %splat.splat 5092} 5093 5094; Function Attrs: norecurse nounwind readonly 5095define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 5096; P9BE-LABEL: spltMemValConvdtoll: 5097; P9BE: # %bb.0: # %entry 5098; P9BE-NEXT: lxvdsx vs0, 0, r3 5099; P9BE-NEXT: xvcvdpsxds v2, vs0 5100; P9BE-NEXT: blr 5101; 5102; P9LE-LABEL: spltMemValConvdtoll: 5103; P9LE: # %bb.0: # %entry 5104; P9LE-NEXT: lxvdsx vs0, 0, r3 5105; P9LE-NEXT: xvcvdpsxds v2, vs0 5106; P9LE-NEXT: blr 5107; 5108; P8BE-LABEL: spltMemValConvdtoll: 5109; P8BE: # %bb.0: # %entry 5110; P8BE-NEXT: lxvdsx vs0, 0, r3 5111; P8BE-NEXT: xvcvdpsxds v2, vs0 5112; P8BE-NEXT: blr 5113; 5114; P8LE-LABEL: spltMemValConvdtoll: 5115; P8LE: # %bb.0: # %entry 5116; P8LE-NEXT: lxvdsx vs0, 0, r3 5117; P8LE-NEXT: xvcvdpsxds v2, vs0 5118; P8LE-NEXT: blr 5119entry: 5120 %0 = load double, double* %ptr, align 8 5121 %conv = fptosi double %0 to i64 5122 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5123 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5124 ret <2 x i64> %splat.splat 5125} 5126 5127; Function Attrs: norecurse nounwind readnone 5128define <2 x i64> @allZeroull() { 5129; P9BE-LABEL: allZeroull: 5130; P9BE: # %bb.0: # %entry 5131; P9BE-NEXT: xxlxor v2, v2, v2 5132; P9BE-NEXT: blr 5133; 5134; P9LE-LABEL: allZeroull: 5135; P9LE: # %bb.0: # %entry 5136; P9LE-NEXT: xxlxor v2, v2, v2 5137; P9LE-NEXT: blr 5138; 5139; P8BE-LABEL: allZeroull: 5140; P8BE: # %bb.0: # %entry 5141; P8BE-NEXT: xxlxor v2, v2, v2 5142; P8BE-NEXT: blr 5143; 5144; P8LE-LABEL: allZeroull: 5145; P8LE: # %bb.0: # %entry 5146; P8LE-NEXT: xxlxor v2, v2, v2 5147; P8LE-NEXT: blr 5148entry: 5149 ret <2 x i64> zeroinitializer 5150} 5151 5152; Function Attrs: norecurse nounwind readnone 5153define <2 x i64> @allOneull() { 5154; P9BE-LABEL: allOneull: 5155; P9BE: # %bb.0: # %entry 5156; P9BE-NEXT: xxspltib v2, 255 5157; P9BE-NEXT: blr 5158; 5159; P9LE-LABEL: allOneull: 5160; P9LE: # %bb.0: # %entry 5161; P9LE-NEXT: xxspltib v2, 255 5162; P9LE-NEXT: blr 5163; 5164; P8BE-LABEL: allOneull: 5165; P8BE: # %bb.0: # %entry 5166; P8BE-NEXT: vspltisb v2, -1 5167; P8BE-NEXT: blr 5168; 5169; P8LE-LABEL: allOneull: 5170; P8LE: # %bb.0: # %entry 5171; P8LE-NEXT: vspltisb v2, -1 5172; P8LE-NEXT: blr 5173entry: 5174 ret <2 x i64> <i64 -1, i64 -1> 5175} 5176 5177; Function Attrs: norecurse nounwind readnone 5178define <2 x i64> @spltConst1ull() { 5179; P9BE-LABEL: spltConst1ull: 5180; P9BE: # %bb.0: # %entry 5181; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5182; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5183; P9BE-NEXT: lxvx v2, 0, r3 5184; P9BE-NEXT: blr 5185; 5186; P9LE-LABEL: spltConst1ull: 5187; P9LE: # %bb.0: # %entry 5188; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5189; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5190; P9LE-NEXT: lxvx v2, 0, r3 5191; P9LE-NEXT: blr 5192; 5193; P8BE-LABEL: spltConst1ull: 5194; P8BE: # %bb.0: # %entry 5195; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5196; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5197; P8BE-NEXT: lxvd2x v2, 0, r3 5198; P8BE-NEXT: blr 5199; 5200; P8LE-LABEL: spltConst1ull: 5201; P8LE: # %bb.0: # %entry 5202; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5203; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5204; P8LE-NEXT: lxvd2x vs0, 0, r3 5205; P8LE-NEXT: xxswapd v2, vs0 5206; P8LE-NEXT: blr 5207entry: 5208 ret <2 x i64> <i64 1, i64 1> 5209} 5210 5211; Function Attrs: norecurse nounwind readnone 5212define <2 x i64> @spltConst16kull() { 5213; P9BE-LABEL: spltConst16kull: 5214; P9BE: # %bb.0: # %entry 5215; P9BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5216; P9BE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5217; P9BE-NEXT: lxvx v2, 0, r3 5218; P9BE-NEXT: blr 5219; 5220; P9LE-LABEL: spltConst16kull: 5221; P9LE: # %bb.0: # %entry 5222; P9LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5223; P9LE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5224; P9LE-NEXT: lxvx v2, 0, r3 5225; P9LE-NEXT: blr 5226; 5227; P8BE-LABEL: spltConst16kull: 5228; P8BE: # %bb.0: # %entry 5229; P8BE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5230; P8BE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5231; P8BE-NEXT: lxvd2x v2, 0, r3 5232; P8BE-NEXT: blr 5233; 5234; P8LE-LABEL: spltConst16kull: 5235; P8LE: # %bb.0: # %entry 5236; P8LE-NEXT: addis r3, r2, .LCPI102_0@toc@ha 5237; P8LE-NEXT: addi r3, r3, .LCPI102_0@toc@l 5238; P8LE-NEXT: lxvd2x vs0, 0, r3 5239; P8LE-NEXT: xxswapd v2, vs0 5240; P8LE-NEXT: blr 5241entry: 5242 ret <2 x i64> <i64 32767, i64 32767> 5243} 5244 5245; Function Attrs: norecurse nounwind readnone 5246define <2 x i64> @spltConst32kull() { 5247; P9BE-LABEL: spltConst32kull: 5248; P9BE: # %bb.0: # %entry 5249; P9BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5250; P9BE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5251; P9BE-NEXT: lxvx v2, 0, r3 5252; P9BE-NEXT: blr 5253; 5254; P9LE-LABEL: spltConst32kull: 5255; P9LE: # %bb.0: # %entry 5256; P9LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5257; P9LE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5258; P9LE-NEXT: lxvx v2, 0, r3 5259; P9LE-NEXT: blr 5260; 5261; P8BE-LABEL: spltConst32kull: 5262; P8BE: # %bb.0: # %entry 5263; P8BE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5264; P8BE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5265; P8BE-NEXT: lxvd2x v2, 0, r3 5266; P8BE-NEXT: blr 5267; 5268; P8LE-LABEL: spltConst32kull: 5269; P8LE: # %bb.0: # %entry 5270; P8LE-NEXT: addis r3, r2, .LCPI103_0@toc@ha 5271; P8LE-NEXT: addi r3, r3, .LCPI103_0@toc@l 5272; P8LE-NEXT: lxvd2x vs0, 0, r3 5273; P8LE-NEXT: xxswapd v2, vs0 5274; P8LE-NEXT: blr 5275entry: 5276 ret <2 x i64> <i64 65535, i64 65535> 5277} 5278 5279; Function Attrs: norecurse nounwind readnone 5280define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5281; P9BE-LABEL: fromRegsull: 5282; P9BE: # %bb.0: # %entry 5283; P9BE-NEXT: mtvsrdd v2, r3, r4 5284; P9BE-NEXT: blr 5285; 5286; P9LE-LABEL: fromRegsull: 5287; P9LE: # %bb.0: # %entry 5288; P9LE-NEXT: mtvsrdd v2, r4, r3 5289; P9LE-NEXT: blr 5290; 5291; P8BE-LABEL: fromRegsull: 5292; P8BE: # %bb.0: # %entry 5293; P8BE-NEXT: mtvsrd f0, r4 5294; P8BE-NEXT: mtvsrd f1, r3 5295; P8BE-NEXT: xxmrghd v2, vs1, vs0 5296; P8BE-NEXT: blr 5297; 5298; P8LE-LABEL: fromRegsull: 5299; P8LE: # %bb.0: # %entry 5300; P8LE-NEXT: mtvsrd f0, r3 5301; P8LE-NEXT: mtvsrd f1, r4 5302; P8LE-NEXT: xxmrghd v2, vs1, vs0 5303; P8LE-NEXT: blr 5304entry: 5305 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5306 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5307 ret <2 x i64> %vecinit1 5308} 5309 5310; Function Attrs: norecurse nounwind readnone 5311define <2 x i64> @fromDiffConstsull() { 5312; P9BE-LABEL: fromDiffConstsull: 5313; P9BE: # %bb.0: # %entry 5314; P9BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5315; P9BE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5316; P9BE-NEXT: lxvx v2, 0, r3 5317; P9BE-NEXT: blr 5318; 5319; P9LE-LABEL: fromDiffConstsull: 5320; P9LE: # %bb.0: # %entry 5321; P9LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5322; P9LE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5323; P9LE-NEXT: lxvx v2, 0, r3 5324; P9LE-NEXT: blr 5325; 5326; P8BE-LABEL: fromDiffConstsull: 5327; P8BE: # %bb.0: # %entry 5328; P8BE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5329; P8BE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5330; P8BE-NEXT: lxvd2x v2, 0, r3 5331; P8BE-NEXT: blr 5332; 5333; P8LE-LABEL: fromDiffConstsull: 5334; P8LE: # %bb.0: # %entry 5335; P8LE-NEXT: addis r3, r2, .LCPI105_0@toc@ha 5336; P8LE-NEXT: addi r3, r3, .LCPI105_0@toc@l 5337; P8LE-NEXT: lxvd2x vs0, 0, r3 5338; P8LE-NEXT: xxswapd v2, vs0 5339; P8LE-NEXT: blr 5340entry: 5341 ret <2 x i64> <i64 242, i64 -113> 5342} 5343 5344; Function Attrs: norecurse nounwind readonly 5345define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5346; P9BE-LABEL: fromDiffMemConsAull: 5347; P9BE: # %bb.0: # %entry 5348; P9BE-NEXT: lxv v2, 0(r3) 5349; P9BE-NEXT: blr 5350; 5351; P9LE-LABEL: fromDiffMemConsAull: 5352; P9LE: # %bb.0: # %entry 5353; P9LE-NEXT: lxv v2, 0(r3) 5354; P9LE-NEXT: blr 5355; 5356; P8BE-LABEL: fromDiffMemConsAull: 5357; P8BE: # %bb.0: # %entry 5358; P8BE-NEXT: lxvd2x v2, 0, r3 5359; P8BE-NEXT: blr 5360; 5361; P8LE-LABEL: fromDiffMemConsAull: 5362; P8LE: # %bb.0: # %entry 5363; P8LE-NEXT: lxvd2x vs0, 0, r3 5364; P8LE-NEXT: xxswapd v2, vs0 5365; P8LE-NEXT: blr 5366entry: 5367 %0 = load i64, i64* %arr, align 8 5368 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5369 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5370 %1 = load i64, i64* %arrayidx1, align 8 5371 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5372 ret <2 x i64> %vecinit2 5373} 5374 5375; Function Attrs: norecurse nounwind readonly 5376define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5377; P9BE-LABEL: fromDiffMemConsDull: 5378; P9BE: # %bb.0: # %entry 5379; P9BE-NEXT: lxv v2, 16(r3) 5380; P9BE-NEXT: xxswapd v2, v2 5381; P9BE-NEXT: blr 5382; 5383; P9LE-LABEL: fromDiffMemConsDull: 5384; P9LE: # %bb.0: # %entry 5385; P9LE-NEXT: addi r3, r3, 16 5386; P9LE-NEXT: lxvd2x v2, 0, r3 5387; P9LE-NEXT: blr 5388; 5389; P8BE-LABEL: fromDiffMemConsDull: 5390; P8BE: # %bb.0: # %entry 5391; P8BE-NEXT: addi r3, r3, 16 5392; P8BE-NEXT: lxvd2x v2, 0, r3 5393; P8BE-NEXT: xxswapd v2, v2 5394; P8BE-NEXT: blr 5395; 5396; P8LE-LABEL: fromDiffMemConsDull: 5397; P8LE: # %bb.0: # %entry 5398; P8LE-NEXT: addi r3, r3, 16 5399; P8LE-NEXT: lxvd2x v2, 0, r3 5400; P8LE-NEXT: blr 5401entry: 5402 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5403 %0 = load i64, i64* %arrayidx, align 8 5404 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5405 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5406 %1 = load i64, i64* %arrayidx1, align 8 5407 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5408 ret <2 x i64> %vecinit2 5409} 5410 5411; Function Attrs: norecurse nounwind readonly 5412define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5413; P9BE-LABEL: fromDiffMemVarAull: 5414; P9BE: # %bb.0: # %entry 5415; P9BE-NEXT: sldi r4, r4, 3 5416; P9BE-NEXT: lxvx v2, r3, r4 5417; P9BE-NEXT: blr 5418; 5419; P9LE-LABEL: fromDiffMemVarAull: 5420; P9LE: # %bb.0: # %entry 5421; P9LE-NEXT: sldi r4, r4, 3 5422; P9LE-NEXT: lxvx v2, r3, r4 5423; P9LE-NEXT: blr 5424; 5425; P8BE-LABEL: fromDiffMemVarAull: 5426; P8BE: # %bb.0: # %entry 5427; P8BE-NEXT: sldi r4, r4, 3 5428; P8BE-NEXT: lxvd2x v2, r3, r4 5429; P8BE-NEXT: blr 5430; 5431; P8LE-LABEL: fromDiffMemVarAull: 5432; P8LE: # %bb.0: # %entry 5433; P8LE-NEXT: sldi r4, r4, 3 5434; P8LE-NEXT: lxvd2x vs0, r3, r4 5435; P8LE-NEXT: xxswapd v2, vs0 5436; P8LE-NEXT: blr 5437entry: 5438 %idxprom = sext i32 %elem to i64 5439 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5440 %0 = load i64, i64* %arrayidx, align 8 5441 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5442 %add = add nsw i32 %elem, 1 5443 %idxprom1 = sext i32 %add to i64 5444 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5445 %1 = load i64, i64* %arrayidx2, align 8 5446 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5447 ret <2 x i64> %vecinit3 5448} 5449 5450; Function Attrs: norecurse nounwind readonly 5451define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5452; P9BE-LABEL: fromDiffMemVarDull: 5453; P9BE: # %bb.0: # %entry 5454; P9BE-NEXT: sldi r4, r4, 3 5455; P9BE-NEXT: add r3, r3, r4 5456; P9BE-NEXT: li r4, -8 5457; P9BE-NEXT: lxvx v2, r3, r4 5458; P9BE-NEXT: xxswapd v2, v2 5459; P9BE-NEXT: blr 5460; 5461; P9LE-LABEL: fromDiffMemVarDull: 5462; P9LE: # %bb.0: # %entry 5463; P9LE-NEXT: sldi r4, r4, 3 5464; P9LE-NEXT: add r3, r3, r4 5465; P9LE-NEXT: addi r3, r3, -8 5466; P9LE-NEXT: lxvd2x v2, 0, r3 5467; P9LE-NEXT: blr 5468; 5469; P8BE-LABEL: fromDiffMemVarDull: 5470; P8BE: # %bb.0: # %entry 5471; P8BE-NEXT: sldi r4, r4, 3 5472; P8BE-NEXT: add r3, r3, r4 5473; P8BE-NEXT: addi r3, r3, -8 5474; P8BE-NEXT: lxvd2x v2, 0, r3 5475; P8BE-NEXT: xxswapd v2, v2 5476; P8BE-NEXT: blr 5477; 5478; P8LE-LABEL: fromDiffMemVarDull: 5479; P8LE: # %bb.0: # %entry 5480; P8LE-NEXT: sldi r4, r4, 3 5481; P8LE-NEXT: add r3, r3, r4 5482; P8LE-NEXT: addi r3, r3, -8 5483; P8LE-NEXT: lxvd2x v2, 0, r3 5484; P8LE-NEXT: blr 5485entry: 5486 %idxprom = sext i32 %elem to i64 5487 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5488 %0 = load i64, i64* %arrayidx, align 8 5489 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5490 %sub = add nsw i32 %elem, -1 5491 %idxprom1 = sext i32 %sub to i64 5492 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5493 %1 = load i64, i64* %arrayidx2, align 8 5494 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5495 ret <2 x i64> %vecinit3 5496} 5497 5498; Function Attrs: norecurse nounwind readonly 5499define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5500; P9BE-LABEL: fromRandMemConsull: 5501; P9BE: # %bb.0: # %entry 5502; P9BE-NEXT: ld r4, 32(r3) 5503; P9BE-NEXT: ld r3, 144(r3) 5504; P9BE-NEXT: mtvsrdd v2, r4, r3 5505; P9BE-NEXT: blr 5506; 5507; P9LE-LABEL: fromRandMemConsull: 5508; P9LE: # %bb.0: # %entry 5509; P9LE-NEXT: ld r4, 32(r3) 5510; P9LE-NEXT: ld r3, 144(r3) 5511; P9LE-NEXT: mtvsrdd v2, r3, r4 5512; P9LE-NEXT: blr 5513; 5514; P8BE-LABEL: fromRandMemConsull: 5515; P8BE: # %bb.0: # %entry 5516; P8BE-NEXT: ld r4, 144(r3) 5517; P8BE-NEXT: ld r3, 32(r3) 5518; P8BE-NEXT: mtvsrd f0, r4 5519; P8BE-NEXT: mtvsrd f1, r3 5520; P8BE-NEXT: xxmrghd v2, vs1, vs0 5521; P8BE-NEXT: blr 5522; 5523; P8LE-LABEL: fromRandMemConsull: 5524; P8LE: # %bb.0: # %entry 5525; P8LE-NEXT: ld r4, 32(r3) 5526; P8LE-NEXT: ld r3, 144(r3) 5527; P8LE-NEXT: mtvsrd f0, r4 5528; P8LE-NEXT: mtvsrd f1, r3 5529; P8LE-NEXT: xxmrghd v2, vs1, vs0 5530; P8LE-NEXT: blr 5531entry: 5532 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5533 %0 = load i64, i64* %arrayidx, align 8 5534 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5535 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5536 %1 = load i64, i64* %arrayidx1, align 8 5537 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5538 ret <2 x i64> %vecinit2 5539} 5540 5541; Function Attrs: norecurse nounwind readonly 5542define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5543; P9BE-LABEL: fromRandMemVarull: 5544; P9BE: # %bb.0: # %entry 5545; P9BE-NEXT: sldi r4, r4, 3 5546; P9BE-NEXT: add r3, r3, r4 5547; P9BE-NEXT: ld r4, 32(r3) 5548; P9BE-NEXT: ld r3, 8(r3) 5549; P9BE-NEXT: mtvsrdd v2, r4, r3 5550; P9BE-NEXT: blr 5551; 5552; P9LE-LABEL: fromRandMemVarull: 5553; P9LE: # %bb.0: # %entry 5554; P9LE-NEXT: sldi r4, r4, 3 5555; P9LE-NEXT: add r3, r3, r4 5556; P9LE-NEXT: ld r4, 32(r3) 5557; P9LE-NEXT: ld r3, 8(r3) 5558; P9LE-NEXT: mtvsrdd v2, r3, r4 5559; P9LE-NEXT: blr 5560; 5561; P8BE-LABEL: fromRandMemVarull: 5562; P8BE: # %bb.0: # %entry 5563; P8BE-NEXT: sldi r4, r4, 3 5564; P8BE-NEXT: add r3, r3, r4 5565; P8BE-NEXT: ld r4, 8(r3) 5566; P8BE-NEXT: ld r3, 32(r3) 5567; P8BE-NEXT: mtvsrd f0, r4 5568; P8BE-NEXT: mtvsrd f1, r3 5569; P8BE-NEXT: xxmrghd v2, vs1, vs0 5570; P8BE-NEXT: blr 5571; 5572; P8LE-LABEL: fromRandMemVarull: 5573; P8LE: # %bb.0: # %entry 5574; P8LE-NEXT: sldi r4, r4, 3 5575; P8LE-NEXT: add r3, r3, r4 5576; P8LE-NEXT: ld r4, 32(r3) 5577; P8LE-NEXT: ld r3, 8(r3) 5578; P8LE-NEXT: mtvsrd f0, r4 5579; P8LE-NEXT: mtvsrd f1, r3 5580; P8LE-NEXT: xxmrghd v2, vs1, vs0 5581; P8LE-NEXT: blr 5582entry: 5583 %add = add nsw i32 %elem, 4 5584 %idxprom = sext i32 %add to i64 5585 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5586 %0 = load i64, i64* %arrayidx, align 8 5587 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5588 %add1 = add nsw i32 %elem, 1 5589 %idxprom2 = sext i32 %add1 to i64 5590 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5591 %1 = load i64, i64* %arrayidx3, align 8 5592 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5593 ret <2 x i64> %vecinit4 5594} 5595 5596; Function Attrs: norecurse nounwind readnone 5597define <2 x i64> @spltRegValull(i64 %val) { 5598; P9BE-LABEL: spltRegValull: 5599; P9BE: # %bb.0: # %entry 5600; P9BE-NEXT: mtvsrdd v2, r3, r3 5601; P9BE-NEXT: blr 5602; 5603; P9LE-LABEL: spltRegValull: 5604; P9LE: # %bb.0: # %entry 5605; P9LE-NEXT: mtvsrdd v2, r3, r3 5606; P9LE-NEXT: blr 5607; 5608; P8BE-LABEL: spltRegValull: 5609; P8BE: # %bb.0: # %entry 5610; P8BE-NEXT: mtvsrd f0, r3 5611; P8BE-NEXT: xxspltd v2, vs0, 0 5612; P8BE-NEXT: blr 5613; 5614; P8LE-LABEL: spltRegValull: 5615; P8LE: # %bb.0: # %entry 5616; P8LE-NEXT: mtvsrd f0, r3 5617; P8LE-NEXT: xxspltd v2, vs0, 0 5618; P8LE-NEXT: blr 5619entry: 5620 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5621 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5622 ret <2 x i64> %splat.splat 5623} 5624 5625; Function Attrs: norecurse nounwind readonly 5626define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5627; P9BE-LABEL: spltMemValull: 5628; P9BE: # %bb.0: # %entry 5629; P9BE-NEXT: lxvdsx v2, 0, r3 5630; P9BE-NEXT: blr 5631; 5632; P9LE-LABEL: spltMemValull: 5633; P9LE: # %bb.0: # %entry 5634; P9LE-NEXT: lxvdsx v2, 0, r3 5635; P9LE-NEXT: blr 5636; 5637; P8BE-LABEL: spltMemValull: 5638; P8BE: # %bb.0: # %entry 5639; P8BE-NEXT: lxvdsx v2, 0, r3 5640; P8BE-NEXT: blr 5641; 5642; P8LE-LABEL: spltMemValull: 5643; P8LE: # %bb.0: # %entry 5644; P8LE-NEXT: lxvdsx v2, 0, r3 5645; P8LE-NEXT: blr 5646entry: 5647 %0 = load i64, i64* %ptr, align 8 5648 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5649 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5650 ret <2 x i64> %splat.splat 5651} 5652 5653; Function Attrs: norecurse nounwind readnone 5654define <2 x i64> @spltCnstConvftoull() { 5655; P9BE-LABEL: spltCnstConvftoull: 5656; P9BE: # %bb.0: # %entry 5657; P9BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5658; P9BE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5659; P9BE-NEXT: lxvx v2, 0, r3 5660; P9BE-NEXT: blr 5661; 5662; P9LE-LABEL: spltCnstConvftoull: 5663; P9LE: # %bb.0: # %entry 5664; P9LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5665; P9LE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5666; P9LE-NEXT: lxvx v2, 0, r3 5667; P9LE-NEXT: blr 5668; 5669; P8BE-LABEL: spltCnstConvftoull: 5670; P8BE: # %bb.0: # %entry 5671; P8BE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5672; P8BE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5673; P8BE-NEXT: lxvd2x v2, 0, r3 5674; P8BE-NEXT: blr 5675; 5676; P8LE-LABEL: spltCnstConvftoull: 5677; P8LE: # %bb.0: # %entry 5678; P8LE-NEXT: addis r3, r2, .LCPI114_0@toc@ha 5679; P8LE-NEXT: addi r3, r3, .LCPI114_0@toc@l 5680; P8LE-NEXT: lxvd2x vs0, 0, r3 5681; P8LE-NEXT: xxswapd v2, vs0 5682; P8LE-NEXT: blr 5683entry: 5684 ret <2 x i64> <i64 4, i64 4> 5685} 5686 5687; Function Attrs: norecurse nounwind readnone 5688define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5689; P9BE-LABEL: fromRegsConvftoull: 5690; P9BE: # %bb.0: # %entry 5691; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5692; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5693; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5694; P9BE-NEXT: xvcvdpuxds v2, vs0 5695; P9BE-NEXT: blr 5696; 5697; P9LE-LABEL: fromRegsConvftoull: 5698; P9LE: # %bb.0: # %entry 5699; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5700; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5701; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5702; P9LE-NEXT: xvcvdpuxds v2, vs0 5703; P9LE-NEXT: blr 5704; 5705; P8BE-LABEL: fromRegsConvftoull: 5706; P8BE: # %bb.0: # %entry 5707; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5708; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5709; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5710; P8BE-NEXT: xvcvdpuxds v2, vs0 5711; P8BE-NEXT: blr 5712; 5713; P8LE-LABEL: fromRegsConvftoull: 5714; P8LE: # %bb.0: # %entry 5715; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5716; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5717; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5718; P8LE-NEXT: xvcvdpuxds v2, vs0 5719; P8LE-NEXT: blr 5720entry: 5721 %conv = fptoui float %a to i64 5722 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5723 %conv1 = fptoui float %b to i64 5724 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5725 ret <2 x i64> %vecinit2 5726} 5727 5728; Function Attrs: norecurse nounwind readnone 5729define <2 x i64> @fromDiffConstsConvftoull() { 5730; P9BE-LABEL: fromDiffConstsConvftoull: 5731; P9BE: # %bb.0: # %entry 5732; P9BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5733; P9BE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5734; P9BE-NEXT: lxvx v2, 0, r3 5735; P9BE-NEXT: blr 5736; 5737; P9LE-LABEL: fromDiffConstsConvftoull: 5738; P9LE: # %bb.0: # %entry 5739; P9LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5740; P9LE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5741; P9LE-NEXT: lxvx v2, 0, r3 5742; P9LE-NEXT: blr 5743; 5744; P8BE-LABEL: fromDiffConstsConvftoull: 5745; P8BE: # %bb.0: # %entry 5746; P8BE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5747; P8BE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5748; P8BE-NEXT: lxvd2x v2, 0, r3 5749; P8BE-NEXT: blr 5750; 5751; P8LE-LABEL: fromDiffConstsConvftoull: 5752; P8LE: # %bb.0: # %entry 5753; P8LE-NEXT: addis r3, r2, .LCPI116_0@toc@ha 5754; P8LE-NEXT: addi r3, r3, .LCPI116_0@toc@l 5755; P8LE-NEXT: lxvd2x vs0, 0, r3 5756; P8LE-NEXT: xxswapd v2, vs0 5757; P8LE-NEXT: blr 5758entry: 5759 ret <2 x i64> <i64 24, i64 234> 5760} 5761 5762; Function Attrs: norecurse nounwind readonly 5763define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5764; P9BE-LABEL: fromDiffMemConsAConvftoull: 5765; P9BE: # %bb.0: # %entry 5766; P9BE-NEXT: lfs f0, 0(r3) 5767; P9BE-NEXT: lfs f1, 4(r3) 5768; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5769; P9BE-NEXT: xvcvdpuxds v2, vs0 5770; P9BE-NEXT: blr 5771; 5772; P9LE-LABEL: fromDiffMemConsAConvftoull: 5773; P9LE: # %bb.0: # %entry 5774; P9LE-NEXT: lfs f0, 0(r3) 5775; P9LE-NEXT: lfs f1, 4(r3) 5776; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5777; P9LE-NEXT: xvcvdpuxds v2, vs0 5778; P9LE-NEXT: blr 5779; 5780; P8BE-LABEL: fromDiffMemConsAConvftoull: 5781; P8BE: # %bb.0: # %entry 5782; P8BE-NEXT: lfsx f0, 0, r3 5783; P8BE-NEXT: lfs f1, 4(r3) 5784; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5785; P8BE-NEXT: xvcvdpuxds v2, vs0 5786; P8BE-NEXT: blr 5787; 5788; P8LE-LABEL: fromDiffMemConsAConvftoull: 5789; P8LE: # %bb.0: # %entry 5790; P8LE-NEXT: lfsx f0, 0, r3 5791; P8LE-NEXT: lfs f1, 4(r3) 5792; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5793; P8LE-NEXT: xvcvdpuxds v2, vs0 5794; P8LE-NEXT: blr 5795entry: 5796 %0 = load float, float* %ptr, align 4 5797 %conv = fptoui float %0 to i64 5798 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5799 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5800 %1 = load float, float* %arrayidx1, align 4 5801 %conv2 = fptoui float %1 to i64 5802 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5803 ret <2 x i64> %vecinit3 5804} 5805 5806; Function Attrs: norecurse nounwind readonly 5807define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5808; P9BE-LABEL: fromDiffMemConsDConvftoull: 5809; P9BE: # %bb.0: # %entry 5810; P9BE-NEXT: lfs f0, 12(r3) 5811; P9BE-NEXT: lfs f1, 8(r3) 5812; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5813; P9BE-NEXT: xvcvdpuxds v2, vs0 5814; P9BE-NEXT: blr 5815; 5816; P9LE-LABEL: fromDiffMemConsDConvftoull: 5817; P9LE: # %bb.0: # %entry 5818; P9LE-NEXT: lfs f0, 12(r3) 5819; P9LE-NEXT: lfs f1, 8(r3) 5820; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5821; P9LE-NEXT: xvcvdpuxds v2, vs0 5822; P9LE-NEXT: blr 5823; 5824; P8BE-LABEL: fromDiffMemConsDConvftoull: 5825; P8BE: # %bb.0: # %entry 5826; P8BE-NEXT: lfs f0, 12(r3) 5827; P8BE-NEXT: lfs f1, 8(r3) 5828; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5829; P8BE-NEXT: xvcvdpuxds v2, vs0 5830; P8BE-NEXT: blr 5831; 5832; P8LE-LABEL: fromDiffMemConsDConvftoull: 5833; P8LE: # %bb.0: # %entry 5834; P8LE-NEXT: lfs f0, 12(r3) 5835; P8LE-NEXT: lfs f1, 8(r3) 5836; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5837; P8LE-NEXT: xvcvdpuxds v2, vs0 5838; P8LE-NEXT: blr 5839entry: 5840 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5841 %0 = load float, float* %arrayidx, align 4 5842 %conv = fptoui float %0 to i64 5843 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5844 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5845 %1 = load float, float* %arrayidx1, align 4 5846 %conv2 = fptoui float %1 to i64 5847 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5848 ret <2 x i64> %vecinit3 5849} 5850 5851; Function Attrs: norecurse nounwind readonly 5852define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5853; P9BE-LABEL: fromDiffMemVarAConvftoull: 5854; P9BE: # %bb.0: # %entry 5855; P9BE-NEXT: sldi r4, r4, 2 5856; P9BE-NEXT: lfsux f0, r3, r4 5857; P9BE-NEXT: lfs f1, 4(r3) 5858; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5859; P9BE-NEXT: xvcvdpuxds v2, vs0 5860; P9BE-NEXT: blr 5861; 5862; P9LE-LABEL: fromDiffMemVarAConvftoull: 5863; P9LE: # %bb.0: # %entry 5864; P9LE-NEXT: sldi r4, r4, 2 5865; P9LE-NEXT: lfsux f0, r3, r4 5866; P9LE-NEXT: lfs f1, 4(r3) 5867; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5868; P9LE-NEXT: xvcvdpuxds v2, vs0 5869; P9LE-NEXT: blr 5870; 5871; P8BE-LABEL: fromDiffMemVarAConvftoull: 5872; P8BE: # %bb.0: # %entry 5873; P8BE-NEXT: sldi r4, r4, 2 5874; P8BE-NEXT: lfsux f0, r3, r4 5875; P8BE-NEXT: lfs f1, 4(r3) 5876; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5877; P8BE-NEXT: xvcvdpuxds v2, vs0 5878; P8BE-NEXT: blr 5879; 5880; P8LE-LABEL: fromDiffMemVarAConvftoull: 5881; P8LE: # %bb.0: # %entry 5882; P8LE-NEXT: sldi r4, r4, 2 5883; P8LE-NEXT: lfsux f0, r3, r4 5884; P8LE-NEXT: lfs f1, 4(r3) 5885; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5886; P8LE-NEXT: xvcvdpuxds v2, vs0 5887; P8LE-NEXT: blr 5888entry: 5889 %idxprom = sext i32 %elem to i64 5890 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5891 %0 = load float, float* %arrayidx, align 4 5892 %conv = fptoui float %0 to i64 5893 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5894 %add = add nsw i32 %elem, 1 5895 %idxprom1 = sext i32 %add to i64 5896 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5897 %1 = load float, float* %arrayidx2, align 4 5898 %conv3 = fptoui float %1 to i64 5899 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5900 ret <2 x i64> %vecinit4 5901} 5902 5903; Function Attrs: norecurse nounwind readonly 5904define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5905; P9BE-LABEL: fromDiffMemVarDConvftoull: 5906; P9BE: # %bb.0: # %entry 5907; P9BE-NEXT: sldi r4, r4, 2 5908; P9BE-NEXT: lfsux f0, r3, r4 5909; P9BE-NEXT: lfs f1, -4(r3) 5910; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5911; P9BE-NEXT: xvcvdpuxds v2, vs0 5912; P9BE-NEXT: blr 5913; 5914; P9LE-LABEL: fromDiffMemVarDConvftoull: 5915; P9LE: # %bb.0: # %entry 5916; P9LE-NEXT: sldi r4, r4, 2 5917; P9LE-NEXT: lfsux f0, r3, r4 5918; P9LE-NEXT: lfs f1, -4(r3) 5919; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5920; P9LE-NEXT: xvcvdpuxds v2, vs0 5921; P9LE-NEXT: blr 5922; 5923; P8BE-LABEL: fromDiffMemVarDConvftoull: 5924; P8BE: # %bb.0: # %entry 5925; P8BE-NEXT: sldi r4, r4, 2 5926; P8BE-NEXT: lfsux f0, r3, r4 5927; P8BE-NEXT: lfs f1, -4(r3) 5928; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5929; P8BE-NEXT: xvcvdpuxds v2, vs0 5930; P8BE-NEXT: blr 5931; 5932; P8LE-LABEL: fromDiffMemVarDConvftoull: 5933; P8LE: # %bb.0: # %entry 5934; P8LE-NEXT: sldi r4, r4, 2 5935; P8LE-NEXT: lfsux f0, r3, r4 5936; P8LE-NEXT: lfs f1, -4(r3) 5937; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5938; P8LE-NEXT: xvcvdpuxds v2, vs0 5939; P8LE-NEXT: blr 5940entry: 5941 %idxprom = sext i32 %elem to i64 5942 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5943 %0 = load float, float* %arrayidx, align 4 5944 %conv = fptoui float %0 to i64 5945 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5946 %sub = add nsw i32 %elem, -1 5947 %idxprom1 = sext i32 %sub to i64 5948 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5949 %1 = load float, float* %arrayidx2, align 4 5950 %conv3 = fptoui float %1 to i64 5951 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5952 ret <2 x i64> %vecinit4 5953} 5954 5955; Function Attrs: norecurse nounwind readnone 5956define <2 x i64> @spltRegValConvftoull(float %val) { 5957; P9BE-LABEL: spltRegValConvftoull: 5958; P9BE: # %bb.0: # %entry 5959; P9BE-NEXT: xscvdpuxds f0, f1 5960; P9BE-NEXT: xxspltd v2, f0, 0 5961; P9BE-NEXT: blr 5962; 5963; P9LE-LABEL: spltRegValConvftoull: 5964; P9LE: # %bb.0: # %entry 5965; P9LE-NEXT: xscvdpuxds f0, f1 5966; P9LE-NEXT: xxspltd v2, f0, 0 5967; P9LE-NEXT: blr 5968; 5969; P8BE-LABEL: spltRegValConvftoull: 5970; P8BE: # %bb.0: # %entry 5971; P8BE-NEXT: xscvdpuxds f0, f1 5972; P8BE-NEXT: xxspltd v2, f0, 0 5973; P8BE-NEXT: blr 5974; 5975; P8LE-LABEL: spltRegValConvftoull: 5976; P8LE: # %bb.0: # %entry 5977; P8LE-NEXT: xscvdpuxds f0, f1 5978; P8LE-NEXT: xxspltd v2, f0, 0 5979; P8LE-NEXT: blr 5980entry: 5981 %conv = fptoui float %val to i64 5982 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5983 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5984 ret <2 x i64> %splat.splat 5985} 5986 5987; Function Attrs: norecurse nounwind readonly 5988define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5989; P9BE-LABEL: spltMemValConvftoull: 5990; P9BE: # %bb.0: # %entry 5991; P9BE-NEXT: lfs f0, 0(r3) 5992; P9BE-NEXT: xscvdpuxds f0, f0 5993; P9BE-NEXT: xxspltd v2, f0, 0 5994; P9BE-NEXT: blr 5995; 5996; P9LE-LABEL: spltMemValConvftoull: 5997; P9LE: # %bb.0: # %entry 5998; P9LE-NEXT: lfs f0, 0(r3) 5999; P9LE-NEXT: xscvdpuxds f0, f0 6000; P9LE-NEXT: xxspltd v2, f0, 0 6001; P9LE-NEXT: blr 6002; 6003; P8BE-LABEL: spltMemValConvftoull: 6004; P8BE: # %bb.0: # %entry 6005; P8BE-NEXT: lfsx f0, 0, r3 6006; P8BE-NEXT: xscvdpuxds f0, f0 6007; P8BE-NEXT: xxspltd v2, f0, 0 6008; P8BE-NEXT: blr 6009; 6010; P8LE-LABEL: spltMemValConvftoull: 6011; P8LE: # %bb.0: # %entry 6012; P8LE-NEXT: lfsx f0, 0, r3 6013; P8LE-NEXT: xscvdpuxds f0, f0 6014; P8LE-NEXT: xxspltd v2, f0, 0 6015; P8LE-NEXT: blr 6016entry: 6017 %0 = load float, float* %ptr, align 4 6018 %conv = fptoui float %0 to i64 6019 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6020 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6021 ret <2 x i64> %splat.splat 6022} 6023 6024; Function Attrs: norecurse nounwind readnone 6025define <2 x i64> @spltCnstConvdtoull() { 6026; P9BE-LABEL: spltCnstConvdtoull: 6027; P9BE: # %bb.0: # %entry 6028; P9BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6029; P9BE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6030; P9BE-NEXT: lxvx v2, 0, r3 6031; P9BE-NEXT: blr 6032; 6033; P9LE-LABEL: spltCnstConvdtoull: 6034; P9LE: # %bb.0: # %entry 6035; P9LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6036; P9LE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6037; P9LE-NEXT: lxvx v2, 0, r3 6038; P9LE-NEXT: blr 6039; 6040; P8BE-LABEL: spltCnstConvdtoull: 6041; P8BE: # %bb.0: # %entry 6042; P8BE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6043; P8BE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6044; P8BE-NEXT: lxvd2x v2, 0, r3 6045; P8BE-NEXT: blr 6046; 6047; P8LE-LABEL: spltCnstConvdtoull: 6048; P8LE: # %bb.0: # %entry 6049; P8LE-NEXT: addis r3, r2, .LCPI123_0@toc@ha 6050; P8LE-NEXT: addi r3, r3, .LCPI123_0@toc@l 6051; P8LE-NEXT: lxvd2x vs0, 0, r3 6052; P8LE-NEXT: xxswapd v2, vs0 6053; P8LE-NEXT: blr 6054entry: 6055 ret <2 x i64> <i64 4, i64 4> 6056} 6057 6058; Function Attrs: norecurse nounwind readnone 6059define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 6060; P9BE-LABEL: fromRegsConvdtoull: 6061; P9BE: # %bb.0: # %entry 6062; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6063; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6064; P9BE-NEXT: xxmrghd vs0, vs1, vs2 6065; P9BE-NEXT: xvcvdpuxds v2, vs0 6066; P9BE-NEXT: blr 6067; 6068; P9LE-LABEL: fromRegsConvdtoull: 6069; P9LE: # %bb.0: # %entry 6070; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6071; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6072; P9LE-NEXT: xxmrghd vs0, vs2, vs1 6073; P9LE-NEXT: xvcvdpuxds v2, vs0 6074; P9LE-NEXT: blr 6075; 6076; P8BE-LABEL: fromRegsConvdtoull: 6077; P8BE: # %bb.0: # %entry 6078; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6079; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6080; P8BE-NEXT: xxmrghd vs0, vs1, vs2 6081; P8BE-NEXT: xvcvdpuxds v2, vs0 6082; P8BE-NEXT: blr 6083; 6084; P8LE-LABEL: fromRegsConvdtoull: 6085; P8LE: # %bb.0: # %entry 6086; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 6087; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 6088; P8LE-NEXT: xxmrghd vs0, vs2, vs1 6089; P8LE-NEXT: xvcvdpuxds v2, vs0 6090; P8LE-NEXT: blr 6091entry: 6092 %conv = fptoui double %a to i64 6093 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6094 %conv1 = fptoui double %b to i64 6095 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 6096 ret <2 x i64> %vecinit2 6097} 6098 6099; Function Attrs: norecurse nounwind readnone 6100define <2 x i64> @fromDiffConstsConvdtoull() { 6101; P9BE-LABEL: fromDiffConstsConvdtoull: 6102; P9BE: # %bb.0: # %entry 6103; P9BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6104; P9BE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6105; P9BE-NEXT: lxvx v2, 0, r3 6106; P9BE-NEXT: blr 6107; 6108; P9LE-LABEL: fromDiffConstsConvdtoull: 6109; P9LE: # %bb.0: # %entry 6110; P9LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6111; P9LE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6112; P9LE-NEXT: lxvx v2, 0, r3 6113; P9LE-NEXT: blr 6114; 6115; P8BE-LABEL: fromDiffConstsConvdtoull: 6116; P8BE: # %bb.0: # %entry 6117; P8BE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6118; P8BE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6119; P8BE-NEXT: lxvd2x v2, 0, r3 6120; P8BE-NEXT: blr 6121; 6122; P8LE-LABEL: fromDiffConstsConvdtoull: 6123; P8LE: # %bb.0: # %entry 6124; P8LE-NEXT: addis r3, r2, .LCPI125_0@toc@ha 6125; P8LE-NEXT: addi r3, r3, .LCPI125_0@toc@l 6126; P8LE-NEXT: lxvd2x vs0, 0, r3 6127; P8LE-NEXT: xxswapd v2, vs0 6128; P8LE-NEXT: blr 6129entry: 6130 ret <2 x i64> <i64 24, i64 234> 6131} 6132 6133; Function Attrs: norecurse nounwind readonly 6134define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 6135; P9BE-LABEL: fromDiffMemConsAConvdtoull: 6136; P9BE: # %bb.0: # %entry 6137; P9BE-NEXT: lxv vs0, 0(r3) 6138; P9BE-NEXT: xvcvdpuxds v2, vs0 6139; P9BE-NEXT: blr 6140; 6141; P9LE-LABEL: fromDiffMemConsAConvdtoull: 6142; P9LE: # %bb.0: # %entry 6143; P9LE-NEXT: lxv vs0, 0(r3) 6144; P9LE-NEXT: xvcvdpuxds v2, vs0 6145; P9LE-NEXT: blr 6146; 6147; P8BE-LABEL: fromDiffMemConsAConvdtoull: 6148; P8BE: # %bb.0: # %entry 6149; P8BE-NEXT: lxvd2x vs0, 0, r3 6150; P8BE-NEXT: xvcvdpuxds v2, vs0 6151; P8BE-NEXT: blr 6152; 6153; P8LE-LABEL: fromDiffMemConsAConvdtoull: 6154; P8LE: # %bb.0: # %entry 6155; P8LE-NEXT: lxvd2x vs0, 0, r3 6156; P8LE-NEXT: xxswapd vs0, vs0 6157; P8LE-NEXT: xvcvdpuxds v2, vs0 6158; P8LE-NEXT: blr 6159entry: 6160 %0 = bitcast double* %ptr to <2 x double>* 6161 %1 = load <2 x double>, <2 x double>* %0, align 8 6162 %2 = fptoui <2 x double> %1 to <2 x i64> 6163 ret <2 x i64> %2 6164} 6165 6166; Function Attrs: norecurse nounwind readonly 6167define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 6168; P9BE-LABEL: fromDiffMemConsDConvdtoull: 6169; P9BE: # %bb.0: # %entry 6170; P9BE-NEXT: lxv vs0, 16(r3) 6171; P9BE-NEXT: xxswapd vs0, vs0 6172; P9BE-NEXT: xvcvdpuxds v2, vs0 6173; P9BE-NEXT: blr 6174; 6175; P9LE-LABEL: fromDiffMemConsDConvdtoull: 6176; P9LE: # %bb.0: # %entry 6177; P9LE-NEXT: addi r3, r3, 16 6178; P9LE-NEXT: lxvd2x vs0, 0, r3 6179; P9LE-NEXT: xvcvdpuxds v2, vs0 6180; P9LE-NEXT: blr 6181; 6182; P8BE-LABEL: fromDiffMemConsDConvdtoull: 6183; P8BE: # %bb.0: # %entry 6184; P8BE-NEXT: addi r3, r3, 16 6185; P8BE-NEXT: lxvd2x vs0, 0, r3 6186; P8BE-NEXT: xxswapd vs0, vs0 6187; P8BE-NEXT: xvcvdpuxds v2, vs0 6188; P8BE-NEXT: blr 6189; 6190; P8LE-LABEL: fromDiffMemConsDConvdtoull: 6191; P8LE: # %bb.0: # %entry 6192; P8LE-NEXT: addi r3, r3, 16 6193; P8LE-NEXT: lxvd2x vs0, 0, r3 6194; P8LE-NEXT: xvcvdpuxds v2, vs0 6195; P8LE-NEXT: blr 6196entry: 6197 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 6198 %0 = load double, double* %arrayidx, align 8 6199 %conv = fptoui double %0 to i64 6200 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6201 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 6202 %1 = load double, double* %arrayidx1, align 8 6203 %conv2 = fptoui double %1 to i64 6204 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6205 ret <2 x i64> %vecinit3 6206} 6207 6208; Function Attrs: norecurse nounwind readonly 6209define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6210; P9BE-LABEL: fromDiffMemVarAConvdtoull: 6211; P9BE: # %bb.0: # %entry 6212; P9BE-NEXT: sldi r4, r4, 3 6213; P9BE-NEXT: lxvx vs0, r3, r4 6214; P9BE-NEXT: xvcvdpuxds v2, vs0 6215; P9BE-NEXT: blr 6216; 6217; P9LE-LABEL: fromDiffMemVarAConvdtoull: 6218; P9LE: # %bb.0: # %entry 6219; P9LE-NEXT: sldi r4, r4, 3 6220; P9LE-NEXT: lxvx vs0, r3, r4 6221; P9LE-NEXT: xvcvdpuxds v2, vs0 6222; P9LE-NEXT: blr 6223; 6224; P8BE-LABEL: fromDiffMemVarAConvdtoull: 6225; P8BE: # %bb.0: # %entry 6226; P8BE-NEXT: sldi r4, r4, 3 6227; P8BE-NEXT: lxvd2x vs0, r3, r4 6228; P8BE-NEXT: xvcvdpuxds v2, vs0 6229; P8BE-NEXT: blr 6230; 6231; P8LE-LABEL: fromDiffMemVarAConvdtoull: 6232; P8LE: # %bb.0: # %entry 6233; P8LE-NEXT: sldi r4, r4, 3 6234; P8LE-NEXT: lxvd2x vs0, r3, r4 6235; P8LE-NEXT: xxswapd vs0, vs0 6236; P8LE-NEXT: xvcvdpuxds v2, vs0 6237; P8LE-NEXT: blr 6238entry: 6239 %idxprom = sext i32 %elem to i64 6240 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6241 %0 = load double, double* %arrayidx, align 8 6242 %conv = fptoui double %0 to i64 6243 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6244 %add = add nsw i32 %elem, 1 6245 %idxprom1 = sext i32 %add to i64 6246 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6247 %1 = load double, double* %arrayidx2, align 8 6248 %conv3 = fptoui double %1 to i64 6249 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6250 ret <2 x i64> %vecinit4 6251} 6252 6253; Function Attrs: norecurse nounwind readonly 6254define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6255; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6256; P9BE: # %bb.0: # %entry 6257; P9BE-NEXT: sldi r4, r4, 3 6258; P9BE-NEXT: add r3, r3, r4 6259; P9BE-NEXT: li r4, -8 6260; P9BE-NEXT: lxvx vs0, r3, r4 6261; P9BE-NEXT: xxswapd vs0, vs0 6262; P9BE-NEXT: xvcvdpuxds v2, vs0 6263; P9BE-NEXT: blr 6264; 6265; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6266; P9LE: # %bb.0: # %entry 6267; P9LE-NEXT: sldi r4, r4, 3 6268; P9LE-NEXT: add r3, r3, r4 6269; P9LE-NEXT: addi r3, r3, -8 6270; P9LE-NEXT: lxvd2x vs0, 0, r3 6271; P9LE-NEXT: xvcvdpuxds v2, vs0 6272; P9LE-NEXT: blr 6273; 6274; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6275; P8BE: # %bb.0: # %entry 6276; P8BE-NEXT: sldi r4, r4, 3 6277; P8BE-NEXT: add r3, r3, r4 6278; P8BE-NEXT: addi r3, r3, -8 6279; P8BE-NEXT: lxvd2x vs0, 0, r3 6280; P8BE-NEXT: xxswapd vs0, vs0 6281; P8BE-NEXT: xvcvdpuxds v2, vs0 6282; P8BE-NEXT: blr 6283; 6284; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6285; P8LE: # %bb.0: # %entry 6286; P8LE-NEXT: sldi r4, r4, 3 6287; P8LE-NEXT: add r3, r3, r4 6288; P8LE-NEXT: addi r3, r3, -8 6289; P8LE-NEXT: lxvd2x vs0, 0, r3 6290; P8LE-NEXT: xvcvdpuxds v2, vs0 6291; P8LE-NEXT: blr 6292entry: 6293 %idxprom = sext i32 %elem to i64 6294 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6295 %0 = load double, double* %arrayidx, align 8 6296 %conv = fptoui double %0 to i64 6297 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6298 %sub = add nsw i32 %elem, -1 6299 %idxprom1 = sext i32 %sub to i64 6300 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6301 %1 = load double, double* %arrayidx2, align 8 6302 %conv3 = fptoui double %1 to i64 6303 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6304 ret <2 x i64> %vecinit4 6305} 6306 6307; Function Attrs: norecurse nounwind readnone 6308define <2 x i64> @spltRegValConvdtoull(double %val) { 6309; P9BE-LABEL: spltRegValConvdtoull: 6310; P9BE: # %bb.0: # %entry 6311; P9BE-NEXT: xscvdpuxds f0, f1 6312; P9BE-NEXT: xxspltd v2, vs0, 0 6313; P9BE-NEXT: blr 6314; 6315; P9LE-LABEL: spltRegValConvdtoull: 6316; P9LE: # %bb.0: # %entry 6317; P9LE-NEXT: xscvdpuxds f0, f1 6318; P9LE-NEXT: xxspltd v2, vs0, 0 6319; P9LE-NEXT: blr 6320; 6321; P8BE-LABEL: spltRegValConvdtoull: 6322; P8BE: # %bb.0: # %entry 6323; P8BE-NEXT: xscvdpuxds f0, f1 6324; P8BE-NEXT: xxspltd v2, vs0, 0 6325; P8BE-NEXT: blr 6326; 6327; P8LE-LABEL: spltRegValConvdtoull: 6328; P8LE: # %bb.0: # %entry 6329; P8LE-NEXT: xscvdpuxds f0, f1 6330; P8LE-NEXT: xxspltd v2, vs0, 0 6331; P8LE-NEXT: blr 6332entry: 6333 %conv = fptoui double %val to i64 6334 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6335 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6336 ret <2 x i64> %splat.splat 6337} 6338 6339; Function Attrs: norecurse nounwind readonly 6340define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6341; P9BE-LABEL: spltMemValConvdtoull: 6342; P9BE: # %bb.0: # %entry 6343; P9BE-NEXT: lxvdsx vs0, 0, r3 6344; P9BE-NEXT: xvcvdpuxds v2, vs0 6345; P9BE-NEXT: blr 6346; 6347; P9LE-LABEL: spltMemValConvdtoull: 6348; P9LE: # %bb.0: # %entry 6349; P9LE-NEXT: lxvdsx vs0, 0, r3 6350; P9LE-NEXT: xvcvdpuxds v2, vs0 6351; P9LE-NEXT: blr 6352; 6353; P8BE-LABEL: spltMemValConvdtoull: 6354; P8BE: # %bb.0: # %entry 6355; P8BE-NEXT: lxvdsx vs0, 0, r3 6356; P8BE-NEXT: xvcvdpuxds v2, vs0 6357; P8BE-NEXT: blr 6358; 6359; P8LE-LABEL: spltMemValConvdtoull: 6360; P8LE: # %bb.0: # %entry 6361; P8LE-NEXT: lxvdsx vs0, 0, r3 6362; P8LE-NEXT: xvcvdpuxds v2, vs0 6363; P8LE-NEXT: blr 6364entry: 6365 %0 = load double, double* %ptr, align 8 6366 %conv = fptoui double %0 to i64 6367 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6368 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6369 ret <2 x i64> %splat.splat 6370} 6371