1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(float *ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(float *ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(float *arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(float *arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(float *ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(double *ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(double *ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(double *arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(double *arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(double *ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(float *ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(float *ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(float *arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(float *arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(float *ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(double *ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(double *ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(double *arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(double *arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(double *ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(float *ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(float *ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(float *arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(float *arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(float *ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(double *ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(double *ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(double *arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(double *arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(double *ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(float *ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(float *ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(float *arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(float *arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(float *ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(double *ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(double *ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(double *arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(double *arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(double *ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712define <4 x i32> @allZeroi() { 713; P9BE-LABEL: allZeroi: 714; P9BE: # %bb.0: # %entry 715; P9BE-NEXT: xxlxor v2, v2, v2 716; P9BE-NEXT: blr 717; 718; P9LE-LABEL: allZeroi: 719; P9LE: # %bb.0: # %entry 720; P9LE-NEXT: xxlxor v2, v2, v2 721; P9LE-NEXT: blr 722; 723; P8BE-LABEL: allZeroi: 724; P8BE: # %bb.0: # %entry 725; P8BE-NEXT: xxlxor v2, v2, v2 726; P8BE-NEXT: blr 727; 728; P8LE-LABEL: allZeroi: 729; P8LE: # %bb.0: # %entry 730; P8LE-NEXT: xxlxor v2, v2, v2 731; P8LE-NEXT: blr 732entry: 733 ret <4 x i32> zeroinitializer 734} 735 736define <4 x i32> @spltConst1i() { 737; P9BE-LABEL: spltConst1i: 738; P9BE: # %bb.0: # %entry 739; P9BE-NEXT: vspltisw v2, 1 740; P9BE-NEXT: blr 741; 742; P9LE-LABEL: spltConst1i: 743; P9LE: # %bb.0: # %entry 744; P9LE-NEXT: vspltisw v2, 1 745; P9LE-NEXT: blr 746; 747; P8BE-LABEL: spltConst1i: 748; P8BE: # %bb.0: # %entry 749; P8BE-NEXT: vspltisw v2, 1 750; P8BE-NEXT: blr 751; 752; P8LE-LABEL: spltConst1i: 753; P8LE: # %bb.0: # %entry 754; P8LE-NEXT: vspltisw v2, 1 755; P8LE-NEXT: blr 756entry: 757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 758} 759 760define <4 x i32> @spltConst16ki() { 761; P9BE-LABEL: spltConst16ki: 762; P9BE: # %bb.0: # %entry 763; P9BE-NEXT: vspltisw v2, -15 764; P9BE-NEXT: vsrw v2, v2, v2 765; P9BE-NEXT: blr 766; 767; P9LE-LABEL: spltConst16ki: 768; P9LE: # %bb.0: # %entry 769; P9LE-NEXT: vspltisw v2, -15 770; P9LE-NEXT: vsrw v2, v2, v2 771; P9LE-NEXT: blr 772; 773; P8BE-LABEL: spltConst16ki: 774; P8BE: # %bb.0: # %entry 775; P8BE-NEXT: vspltisw v2, -15 776; P8BE-NEXT: vsrw v2, v2, v2 777; P8BE-NEXT: blr 778; 779; P8LE-LABEL: spltConst16ki: 780; P8LE: # %bb.0: # %entry 781; P8LE-NEXT: vspltisw v2, -15 782; P8LE-NEXT: vsrw v2, v2, v2 783; P8LE-NEXT: blr 784entry: 785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 786} 787 788define <4 x i32> @spltConst32ki() { 789; P9BE-LABEL: spltConst32ki: 790; P9BE: # %bb.0: # %entry 791; P9BE-NEXT: vspltisw v2, -16 792; P9BE-NEXT: vsrw v2, v2, v2 793; P9BE-NEXT: blr 794; 795; P9LE-LABEL: spltConst32ki: 796; P9LE: # %bb.0: # %entry 797; P9LE-NEXT: vspltisw v2, -16 798; P9LE-NEXT: vsrw v2, v2, v2 799; P9LE-NEXT: blr 800; 801; P8BE-LABEL: spltConst32ki: 802; P8BE: # %bb.0: # %entry 803; P8BE-NEXT: vspltisw v2, -16 804; P8BE-NEXT: vsrw v2, v2, v2 805; P8BE-NEXT: blr 806; 807; P8LE-LABEL: spltConst32ki: 808; P8LE: # %bb.0: # %entry 809; P8LE-NEXT: vspltisw v2, -16 810; P8LE-NEXT: vsrw v2, v2, v2 811; P8LE-NEXT: blr 812entry: 813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 814} 815 816define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 817; P9BE-LABEL: fromRegsi: 818; P9BE: # %bb.0: # %entry 819; P9BE-NEXT: rldimi r6, r5, 32, 0 820; P9BE-NEXT: rldimi r4, r3, 32, 0 821; P9BE-NEXT: mtvsrdd v2, r4, r6 822; P9BE-NEXT: blr 823; 824; P9LE-LABEL: fromRegsi: 825; P9LE: # %bb.0: # %entry 826; P9LE-NEXT: rldimi r3, r4, 32, 0 827; P9LE-NEXT: rldimi r5, r6, 32, 0 828; P9LE-NEXT: mtvsrdd v2, r5, r3 829; P9LE-NEXT: blr 830; 831; P8BE-LABEL: fromRegsi: 832; P8BE: # %bb.0: # %entry 833; P8BE-NEXT: rldimi r6, r5, 32, 0 834; P8BE-NEXT: rldimi r4, r3, 32, 0 835; P8BE-NEXT: mtfprd f0, r6 836; P8BE-NEXT: mtfprd f1, r4 837; P8BE-NEXT: xxmrghd v2, vs1, vs0 838; P8BE-NEXT: blr 839; 840; P8LE-LABEL: fromRegsi: 841; P8LE: # %bb.0: # %entry 842; P8LE-NEXT: rldimi r3, r4, 32, 0 843; P8LE-NEXT: rldimi r5, r6, 32, 0 844; P8LE-NEXT: mtfprd f0, r3 845; P8LE-NEXT: mtfprd f1, r5 846; P8LE-NEXT: xxmrghd v2, vs1, vs0 847; P8LE-NEXT: blr 848entry: 849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 853 ret <4 x i32> %vecinit3 854} 855 856define <4 x i32> @fromDiffConstsi() { 857; P9BE-LABEL: fromDiffConstsi: 858; P9BE: # %bb.0: # %entry 859; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 860; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 861; P9BE-NEXT: lxvx v2, 0, r3 862; P9BE-NEXT: blr 863; 864; P9LE-LABEL: fromDiffConstsi: 865; P9LE: # %bb.0: # %entry 866; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 867; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 868; P9LE-NEXT: lxvx v2, 0, r3 869; P9LE-NEXT: blr 870; 871; P8BE-LABEL: fromDiffConstsi: 872; P8BE: # %bb.0: # %entry 873; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 874; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 875; P8BE-NEXT: lxvw4x v2, 0, r3 876; P8BE-NEXT: blr 877; 878; P8LE-LABEL: fromDiffConstsi: 879; P8LE: # %bb.0: # %entry 880; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 881; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 882; P8LE-NEXT: lvx v2, 0, r3 883; P8LE-NEXT: blr 884entry: 885 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 886} 887 888define <4 x i32> @fromDiffMemConsAi(i32* nocapture readonly %arr) { 889; P9BE-LABEL: fromDiffMemConsAi: 890; P9BE: # %bb.0: # %entry 891; P9BE-NEXT: lxv v2, 0(r3) 892; P9BE-NEXT: blr 893; 894; P9LE-LABEL: fromDiffMemConsAi: 895; P9LE: # %bb.0: # %entry 896; P9LE-NEXT: lxv v2, 0(r3) 897; P9LE-NEXT: blr 898; 899; P8BE-LABEL: fromDiffMemConsAi: 900; P8BE: # %bb.0: # %entry 901; P8BE-NEXT: lxvw4x v2, 0, r3 902; P8BE-NEXT: blr 903; 904; P8LE-LABEL: fromDiffMemConsAi: 905; P8LE: # %bb.0: # %entry 906; P8LE-NEXT: lxvd2x vs0, 0, r3 907; P8LE-NEXT: xxswapd v2, vs0 908; P8LE-NEXT: blr 909entry: 910 %0 = load i32, i32* %arr, align 4 911 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 912 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 913 %1 = load i32, i32* %arrayidx1, align 4 914 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 915 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 916 %2 = load i32, i32* %arrayidx3, align 4 917 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 918 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 919 %3 = load i32, i32* %arrayidx5, align 4 920 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 921 ret <4 x i32> %vecinit6 922} 923 924define <4 x i32> @fromDiffMemConsDi(i32* nocapture readonly %arr) { 925; P9BE-LABEL: fromDiffMemConsDi: 926; P9BE: # %bb.0: # %entry 927; P9BE-NEXT: lxv v2, 0(r3) 928; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 929; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 930; P9BE-NEXT: lxvx v3, 0, r3 931; P9BE-NEXT: vperm v2, v2, v2, v3 932; P9BE-NEXT: blr 933; 934; P9LE-LABEL: fromDiffMemConsDi: 935; P9LE: # %bb.0: # %entry 936; P9LE-NEXT: lxvw4x v2, 0, r3 937; P9LE-NEXT: blr 938; 939; P8BE-LABEL: fromDiffMemConsDi: 940; P8BE: # %bb.0: # %entry 941; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 942; P8BE-NEXT: lxvw4x v2, 0, r3 943; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l 944; P8BE-NEXT: lxvw4x v3, 0, r4 945; P8BE-NEXT: vperm v2, v2, v2, v3 946; P8BE-NEXT: blr 947; 948; P8LE-LABEL: fromDiffMemConsDi: 949; P8LE: # %bb.0: # %entry 950; P8LE-NEXT: lxvd2x vs0, 0, r3 951; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha 952; P8LE-NEXT: addi r3, r4, .LCPI7_0@toc@l 953; P8LE-NEXT: lvx v2, 0, r3 954; P8LE-NEXT: xxswapd v3, vs0 955; P8LE-NEXT: vperm v2, v3, v3, v2 956; P8LE-NEXT: blr 957entry: 958 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 959 %0 = load i32, i32* %arrayidx, align 4 960 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 961 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 962 %1 = load i32, i32* %arrayidx1, align 4 963 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 964 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 965 %2 = load i32, i32* %arrayidx3, align 4 966 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 967 %3 = load i32, i32* %arr, align 4 968 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 969 ret <4 x i32> %vecinit6 970} 971 972define <4 x i32> @fromDiffMemVarAi(i32* nocapture readonly %arr, i32 signext %elem) { 973; P9BE-LABEL: fromDiffMemVarAi: 974; P9BE: # %bb.0: # %entry 975; P9BE-NEXT: sldi r4, r4, 2 976; P9BE-NEXT: lxvx v2, r3, r4 977; P9BE-NEXT: blr 978; 979; P9LE-LABEL: fromDiffMemVarAi: 980; P9LE: # %bb.0: # %entry 981; P9LE-NEXT: sldi r4, r4, 2 982; P9LE-NEXT: lxvx v2, r3, r4 983; P9LE-NEXT: blr 984; 985; P8BE-LABEL: fromDiffMemVarAi: 986; P8BE: # %bb.0: # %entry 987; P8BE-NEXT: sldi r4, r4, 2 988; P8BE-NEXT: lxvw4x v2, r3, r4 989; P8BE-NEXT: blr 990; 991; P8LE-LABEL: fromDiffMemVarAi: 992; P8LE: # %bb.0: # %entry 993; P8LE-NEXT: sldi r4, r4, 2 994; P8LE-NEXT: lxvd2x vs0, r3, r4 995; P8LE-NEXT: xxswapd v2, vs0 996; P8LE-NEXT: blr 997entry: 998 %idxprom = sext i32 %elem to i64 999 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1000 %0 = load i32, i32* %arrayidx, align 4 1001 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1002 %add = add nsw i32 %elem, 1 1003 %idxprom1 = sext i32 %add to i64 1004 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1005 %1 = load i32, i32* %arrayidx2, align 4 1006 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1007 %add4 = add nsw i32 %elem, 2 1008 %idxprom5 = sext i32 %add4 to i64 1009 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1010 %2 = load i32, i32* %arrayidx6, align 4 1011 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1012 %add8 = add nsw i32 %elem, 3 1013 %idxprom9 = sext i32 %add8 to i64 1014 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1015 %3 = load i32, i32* %arrayidx10, align 4 1016 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1017 ret <4 x i32> %vecinit11 1018} 1019 1020define <4 x i32> @fromDiffMemVarDi(i32* nocapture readonly %arr, i32 signext %elem) { 1021; P9BE-LABEL: fromDiffMemVarDi: 1022; P9BE: # %bb.0: # %entry 1023; P9BE-NEXT: sldi r4, r4, 2 1024; P9BE-NEXT: add r3, r3, r4 1025; P9BE-NEXT: addi r3, r3, -12 1026; P9BE-NEXT: lxvx v2, 0, r3 1027; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1028; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1029; P9BE-NEXT: lxvx v3, 0, r3 1030; P9BE-NEXT: vperm v2, v2, v2, v3 1031; P9BE-NEXT: blr 1032; 1033; P9LE-LABEL: fromDiffMemVarDi: 1034; P9LE: # %bb.0: # %entry 1035; P9LE-NEXT: sldi r4, r4, 2 1036; P9LE-NEXT: add r3, r3, r4 1037; P9LE-NEXT: addi r3, r3, -12 1038; P9LE-NEXT: lxvx v2, 0, r3 1039; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1040; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1041; P9LE-NEXT: lxvx v3, 0, r3 1042; P9LE-NEXT: vperm v2, v2, v2, v3 1043; P9LE-NEXT: blr 1044; 1045; P8BE-LABEL: fromDiffMemVarDi: 1046; P8BE: # %bb.0: # %entry 1047; P8BE-NEXT: sldi r4, r4, 2 1048; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1049; P8BE-NEXT: add r3, r3, r4 1050; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l 1051; P8BE-NEXT: addi r3, r3, -12 1052; P8BE-NEXT: lxvw4x v3, 0, r4 1053; P8BE-NEXT: lxvw4x v2, 0, r3 1054; P8BE-NEXT: vperm v2, v2, v2, v3 1055; P8BE-NEXT: blr 1056; 1057; P8LE-LABEL: fromDiffMemVarDi: 1058; P8LE: # %bb.0: # %entry 1059; P8LE-NEXT: sldi r4, r4, 2 1060; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1061; P8LE-NEXT: add r3, r3, r4 1062; P8LE-NEXT: addi r3, r3, -12 1063; P8LE-NEXT: lxvd2x vs0, 0, r3 1064; P8LE-NEXT: addi r3, r5, .LCPI9_0@toc@l 1065; P8LE-NEXT: lvx v3, 0, r3 1066; P8LE-NEXT: xxswapd v2, vs0 1067; P8LE-NEXT: vperm v2, v2, v2, v3 1068; P8LE-NEXT: blr 1069entry: 1070 %idxprom = sext i32 %elem to i64 1071 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1072 %0 = load i32, i32* %arrayidx, align 4 1073 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1074 %sub = add nsw i32 %elem, -1 1075 %idxprom1 = sext i32 %sub to i64 1076 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 1077 %1 = load i32, i32* %arrayidx2, align 4 1078 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1079 %sub4 = add nsw i32 %elem, -2 1080 %idxprom5 = sext i32 %sub4 to i64 1081 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 1082 %2 = load i32, i32* %arrayidx6, align 4 1083 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1084 %sub8 = add nsw i32 %elem, -3 1085 %idxprom9 = sext i32 %sub8 to i64 1086 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 1087 %3 = load i32, i32* %arrayidx10, align 4 1088 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1089 ret <4 x i32> %vecinit11 1090} 1091 1092define <4 x i32> @fromRandMemConsi(i32* nocapture readonly %arr) { 1093; P9BE-LABEL: fromRandMemConsi: 1094; P9BE: # %bb.0: # %entry 1095; P9BE-NEXT: lwz r4, 16(r3) 1096; P9BE-NEXT: lwz r5, 72(r3) 1097; P9BE-NEXT: lwz r6, 8(r3) 1098; P9BE-NEXT: lwz r3, 352(r3) 1099; P9BE-NEXT: rldimi r3, r6, 32, 0 1100; P9BE-NEXT: rldimi r5, r4, 32, 0 1101; P9BE-NEXT: mtvsrdd v2, r5, r3 1102; P9BE-NEXT: blr 1103; 1104; P9LE-LABEL: fromRandMemConsi: 1105; P9LE: # %bb.0: # %entry 1106; P9LE-NEXT: lwz r4, 16(r3) 1107; P9LE-NEXT: lwz r5, 72(r3) 1108; P9LE-NEXT: lwz r6, 8(r3) 1109; P9LE-NEXT: lwz r3, 352(r3) 1110; P9LE-NEXT: rldimi r4, r5, 32, 0 1111; P9LE-NEXT: rldimi r6, r3, 32, 0 1112; P9LE-NEXT: mtvsrdd v2, r6, r4 1113; P9LE-NEXT: blr 1114; 1115; P8BE-LABEL: fromRandMemConsi: 1116; P8BE: # %bb.0: # %entry 1117; P8BE-NEXT: lwz r4, 8(r3) 1118; P8BE-NEXT: lwz r5, 352(r3) 1119; P8BE-NEXT: lwz r6, 16(r3) 1120; P8BE-NEXT: lwz r3, 72(r3) 1121; P8BE-NEXT: rldimi r5, r4, 32, 0 1122; P8BE-NEXT: rldimi r3, r6, 32, 0 1123; P8BE-NEXT: mtfprd f0, r5 1124; P8BE-NEXT: mtfprd f1, r3 1125; P8BE-NEXT: xxmrghd v2, vs1, vs0 1126; P8BE-NEXT: blr 1127; 1128; P8LE-LABEL: fromRandMemConsi: 1129; P8LE: # %bb.0: # %entry 1130; P8LE-NEXT: lwz r4, 16(r3) 1131; P8LE-NEXT: lwz r5, 72(r3) 1132; P8LE-NEXT: lwz r6, 8(r3) 1133; P8LE-NEXT: lwz r3, 352(r3) 1134; P8LE-NEXT: rldimi r4, r5, 32, 0 1135; P8LE-NEXT: rldimi r6, r3, 32, 0 1136; P8LE-NEXT: mtfprd f0, r4 1137; P8LE-NEXT: mtfprd f1, r6 1138; P8LE-NEXT: xxmrghd v2, vs1, vs0 1139; P8LE-NEXT: blr 1140entry: 1141 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 1142 %0 = load i32, i32* %arrayidx, align 4 1143 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1144 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 1145 %1 = load i32, i32* %arrayidx1, align 4 1146 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1147 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 1148 %2 = load i32, i32* %arrayidx3, align 4 1149 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1150 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 1151 %3 = load i32, i32* %arrayidx5, align 4 1152 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1153 ret <4 x i32> %vecinit6 1154} 1155 1156define <4 x i32> @fromRandMemVari(i32* nocapture readonly %arr, i32 signext %elem) { 1157; P9BE-LABEL: fromRandMemVari: 1158; P9BE: # %bb.0: # %entry 1159; P9BE-NEXT: sldi r4, r4, 2 1160; P9BE-NEXT: add r3, r3, r4 1161; P9BE-NEXT: lwz r4, 16(r3) 1162; P9BE-NEXT: lwz r5, 4(r3) 1163; P9BE-NEXT: lwz r6, 8(r3) 1164; P9BE-NEXT: lwz r3, 32(r3) 1165; P9BE-NEXT: rldimi r3, r6, 32, 0 1166; P9BE-NEXT: rldimi r5, r4, 32, 0 1167; P9BE-NEXT: mtvsrdd v2, r5, r3 1168; P9BE-NEXT: blr 1169; 1170; P9LE-LABEL: fromRandMemVari: 1171; P9LE: # %bb.0: # %entry 1172; P9LE-NEXT: sldi r4, r4, 2 1173; P9LE-NEXT: add r3, r3, r4 1174; P9LE-NEXT: lwz r4, 16(r3) 1175; P9LE-NEXT: lwz r5, 4(r3) 1176; P9LE-NEXT: lwz r6, 8(r3) 1177; P9LE-NEXT: lwz r3, 32(r3) 1178; P9LE-NEXT: rldimi r4, r5, 32, 0 1179; P9LE-NEXT: rldimi r6, r3, 32, 0 1180; P9LE-NEXT: mtvsrdd v2, r6, r4 1181; P9LE-NEXT: blr 1182; 1183; P8BE-LABEL: fromRandMemVari: 1184; P8BE: # %bb.0: # %entry 1185; P8BE-NEXT: sldi r4, r4, 2 1186; P8BE-NEXT: add r3, r3, r4 1187; P8BE-NEXT: lwz r4, 8(r3) 1188; P8BE-NEXT: lwz r5, 32(r3) 1189; P8BE-NEXT: lwz r6, 16(r3) 1190; P8BE-NEXT: lwz r3, 4(r3) 1191; P8BE-NEXT: rldimi r5, r4, 32, 0 1192; P8BE-NEXT: rldimi r3, r6, 32, 0 1193; P8BE-NEXT: mtfprd f0, r5 1194; P8BE-NEXT: mtfprd f1, r3 1195; P8BE-NEXT: xxmrghd v2, vs1, vs0 1196; P8BE-NEXT: blr 1197; 1198; P8LE-LABEL: fromRandMemVari: 1199; P8LE: # %bb.0: # %entry 1200; P8LE-NEXT: sldi r4, r4, 2 1201; P8LE-NEXT: add r3, r3, r4 1202; P8LE-NEXT: lwz r4, 16(r3) 1203; P8LE-NEXT: lwz r5, 4(r3) 1204; P8LE-NEXT: lwz r6, 8(r3) 1205; P8LE-NEXT: lwz r3, 32(r3) 1206; P8LE-NEXT: rldimi r4, r5, 32, 0 1207; P8LE-NEXT: rldimi r6, r3, 32, 0 1208; P8LE-NEXT: mtfprd f0, r4 1209; P8LE-NEXT: mtfprd f1, r6 1210; P8LE-NEXT: xxmrghd v2, vs1, vs0 1211; P8LE-NEXT: blr 1212entry: 1213 %add = add nsw i32 %elem, 4 1214 %idxprom = sext i32 %add to i64 1215 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 1216 %0 = load i32, i32* %arrayidx, align 4 1217 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1218 %add1 = add nsw i32 %elem, 1 1219 %idxprom2 = sext i32 %add1 to i64 1220 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 1221 %1 = load i32, i32* %arrayidx3, align 4 1222 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1223 %add5 = add nsw i32 %elem, 2 1224 %idxprom6 = sext i32 %add5 to i64 1225 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 1226 %2 = load i32, i32* %arrayidx7, align 4 1227 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1228 %add9 = add nsw i32 %elem, 8 1229 %idxprom10 = sext i32 %add9 to i64 1230 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 1231 %3 = load i32, i32* %arrayidx11, align 4 1232 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1233 ret <4 x i32> %vecinit12 1234} 1235 1236define <4 x i32> @spltRegVali(i32 signext %val) { 1237; P9BE-LABEL: spltRegVali: 1238; P9BE: # %bb.0: # %entry 1239; P9BE-NEXT: mtvsrws v2, r3 1240; P9BE-NEXT: blr 1241; 1242; P9LE-LABEL: spltRegVali: 1243; P9LE: # %bb.0: # %entry 1244; P9LE-NEXT: mtvsrws v2, r3 1245; P9LE-NEXT: blr 1246; 1247; P8BE-LABEL: spltRegVali: 1248; P8BE: # %bb.0: # %entry 1249; P8BE-NEXT: mtfprwz f0, r3 1250; P8BE-NEXT: xxspltw v2, vs0, 1 1251; P8BE-NEXT: blr 1252; 1253; P8LE-LABEL: spltRegVali: 1254; P8LE: # %bb.0: # %entry 1255; P8LE-NEXT: mtfprwz f0, r3 1256; P8LE-NEXT: xxspltw v2, vs0, 1 1257; P8LE-NEXT: blr 1258entry: 1259 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1260 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1261 ret <4 x i32> %splat.splat 1262} 1263 1264define <4 x i32> @spltMemVali(i32* nocapture readonly %ptr) { 1265; P9BE-LABEL: spltMemVali: 1266; P9BE: # %bb.0: # %entry 1267; P9BE-NEXT: lxvwsx v2, 0, r3 1268; P9BE-NEXT: blr 1269; 1270; P9LE-LABEL: spltMemVali: 1271; P9LE: # %bb.0: # %entry 1272; P9LE-NEXT: lxvwsx v2, 0, r3 1273; P9LE-NEXT: blr 1274; 1275; P8BE-LABEL: spltMemVali: 1276; P8BE: # %bb.0: # %entry 1277; P8BE-NEXT: lfiwzx f0, 0, r3 1278; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 1279; P8BE-NEXT: xxspltw v2, vs0, 0 1280; P8BE-NEXT: blr 1281; 1282; P8LE-LABEL: spltMemVali: 1283; P8LE: # %bb.0: # %entry 1284; P8LE-NEXT: lfiwzx f0, 0, r3 1285; P8LE-NEXT: xxspltw v2, vs0, 1 1286; P8LE-NEXT: blr 1287entry: 1288 %0 = load i32, i32* %ptr, align 4 1289 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1290 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1291 ret <4 x i32> %splat.splat 1292} 1293 1294define <4 x i32> @spltCnstConvftoi() { 1295; P9BE-LABEL: spltCnstConvftoi: 1296; P9BE: # %bb.0: # %entry 1297; P9BE-NEXT: vspltisw v2, 4 1298; P9BE-NEXT: blr 1299; 1300; P9LE-LABEL: spltCnstConvftoi: 1301; P9LE: # %bb.0: # %entry 1302; P9LE-NEXT: vspltisw v2, 4 1303; P9LE-NEXT: blr 1304; 1305; P8BE-LABEL: spltCnstConvftoi: 1306; P8BE: # %bb.0: # %entry 1307; P8BE-NEXT: vspltisw v2, 4 1308; P8BE-NEXT: blr 1309; 1310; P8LE-LABEL: spltCnstConvftoi: 1311; P8LE: # %bb.0: # %entry 1312; P8LE-NEXT: vspltisw v2, 4 1313; P8LE-NEXT: blr 1314entry: 1315 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1316} 1317 1318define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1319; P9BE-LABEL: fromRegsConvftoi: 1320; P9BE: # %bb.0: # %entry 1321; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1322; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1323; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1324; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1325; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1326; P9BE-NEXT: xvcvdpsxws v2, vs0 1327; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1328; P9BE-NEXT: xvcvdpsxws v3, vs0 1329; P9BE-NEXT: vmrgew v2, v3, v2 1330; P9BE-NEXT: blr 1331; 1332; P9LE-LABEL: fromRegsConvftoi: 1333; P9LE: # %bb.0: # %entry 1334; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1335; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1336; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1337; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1338; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1339; P9LE-NEXT: xvcvdpsxws v2, vs0 1340; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1341; P9LE-NEXT: xvcvdpsxws v3, vs0 1342; P9LE-NEXT: vmrgew v2, v3, v2 1343; P9LE-NEXT: blr 1344; 1345; P8BE-LABEL: fromRegsConvftoi: 1346; P8BE: # %bb.0: # %entry 1347; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1348; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1349; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1350; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1351; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1352; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1353; P8BE-NEXT: xvcvdpsxws v2, vs0 1354; P8BE-NEXT: xvcvdpsxws v3, vs1 1355; P8BE-NEXT: vmrgew v2, v3, v2 1356; P8BE-NEXT: blr 1357; 1358; P8LE-LABEL: fromRegsConvftoi: 1359; P8LE: # %bb.0: # %entry 1360; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1361; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1362; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1363; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1364; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1365; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1366; P8LE-NEXT: xvcvdpsxws v2, vs0 1367; P8LE-NEXT: xvcvdpsxws v3, vs1 1368; P8LE-NEXT: vmrgew v2, v3, v2 1369; P8LE-NEXT: blr 1370entry: 1371 %conv = fptosi float %a to i32 1372 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1373 %conv1 = fptosi float %b to i32 1374 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1375 %conv3 = fptosi float %c to i32 1376 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1377 %conv5 = fptosi float %d to i32 1378 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1379 ret <4 x i32> %vecinit6 1380} 1381 1382define <4 x i32> @fromDiffConstsConvftoi() { 1383; P9BE-LABEL: fromDiffConstsConvftoi: 1384; P9BE: # %bb.0: # %entry 1385; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1386; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1387; P9BE-NEXT: lxvx v2, 0, r3 1388; P9BE-NEXT: blr 1389; 1390; P9LE-LABEL: fromDiffConstsConvftoi: 1391; P9LE: # %bb.0: # %entry 1392; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1393; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1394; P9LE-NEXT: lxvx v2, 0, r3 1395; P9LE-NEXT: blr 1396; 1397; P8BE-LABEL: fromDiffConstsConvftoi: 1398; P8BE: # %bb.0: # %entry 1399; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1400; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1401; P8BE-NEXT: lxvw4x v2, 0, r3 1402; P8BE-NEXT: blr 1403; 1404; P8LE-LABEL: fromDiffConstsConvftoi: 1405; P8LE: # %bb.0: # %entry 1406; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1407; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1408; P8LE-NEXT: lvx v2, 0, r3 1409; P8LE-NEXT: blr 1410entry: 1411 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1412} 1413 1414define <4 x i32> @fromDiffMemConsAConvftoi(float* nocapture readonly %ptr) { 1415; P9BE-LABEL: fromDiffMemConsAConvftoi: 1416; P9BE: # %bb.0: # %entry 1417; P9BE-NEXT: lxv vs0, 0(r3) 1418; P9BE-NEXT: xvcvspsxws v2, vs0 1419; P9BE-NEXT: blr 1420; 1421; P9LE-LABEL: fromDiffMemConsAConvftoi: 1422; P9LE: # %bb.0: # %entry 1423; P9LE-NEXT: lxv vs0, 0(r3) 1424; P9LE-NEXT: xvcvspsxws v2, vs0 1425; P9LE-NEXT: blr 1426; 1427; P8BE-LABEL: fromDiffMemConsAConvftoi: 1428; P8BE: # %bb.0: # %entry 1429; P8BE-NEXT: lxvw4x vs0, 0, r3 1430; P8BE-NEXT: xvcvspsxws v2, vs0 1431; P8BE-NEXT: blr 1432; 1433; P8LE-LABEL: fromDiffMemConsAConvftoi: 1434; P8LE: # %bb.0: # %entry 1435; P8LE-NEXT: lxvd2x vs0, 0, r3 1436; P8LE-NEXT: xxswapd v2, vs0 1437; P8LE-NEXT: xvcvspsxws v2, v2 1438; P8LE-NEXT: blr 1439entry: 1440 %0 = bitcast float* %ptr to <4 x float>* 1441 %1 = load <4 x float>, <4 x float>* %0, align 4 1442 %2 = fptosi <4 x float> %1 to <4 x i32> 1443 ret <4 x i32> %2 1444} 1445 1446define <4 x i32> @fromDiffMemConsDConvftoi(float* nocapture readonly %ptr) { 1447; P9BE-LABEL: fromDiffMemConsDConvftoi: 1448; P9BE: # %bb.0: # %entry 1449; P9BE-NEXT: lxv v2, 0(r3) 1450; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1451; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1452; P9BE-NEXT: lxvx v3, 0, r3 1453; P9BE-NEXT: vperm v2, v2, v2, v3 1454; P9BE-NEXT: xvcvspsxws v2, v2 1455; P9BE-NEXT: blr 1456; 1457; P9LE-LABEL: fromDiffMemConsDConvftoi: 1458; P9LE: # %bb.0: # %entry 1459; P9LE-NEXT: lxv v2, 0(r3) 1460; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1461; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1462; P9LE-NEXT: lxvx v3, 0, r3 1463; P9LE-NEXT: vperm v2, v2, v2, v3 1464; P9LE-NEXT: xvcvspsxws v2, v2 1465; P9LE-NEXT: blr 1466; 1467; P8BE-LABEL: fromDiffMemConsDConvftoi: 1468; P8BE: # %bb.0: # %entry 1469; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1470; P8BE-NEXT: lxvw4x v2, 0, r3 1471; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1472; P8BE-NEXT: lxvw4x v3, 0, r4 1473; P8BE-NEXT: vperm v2, v2, v2, v3 1474; P8BE-NEXT: xvcvspsxws v2, v2 1475; P8BE-NEXT: blr 1476; 1477; P8LE-LABEL: fromDiffMemConsDConvftoi: 1478; P8LE: # %bb.0: # %entry 1479; P8LE-NEXT: lxvd2x vs0, 0, r3 1480; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1481; P8LE-NEXT: addi r3, r4, .LCPI18_0@toc@l 1482; P8LE-NEXT: lvx v2, 0, r3 1483; P8LE-NEXT: xxswapd v3, vs0 1484; P8LE-NEXT: vperm v2, v3, v3, v2 1485; P8LE-NEXT: xvcvspsxws v2, v2 1486; P8LE-NEXT: blr 1487entry: 1488 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 1489 %0 = load float, float* %arrayidx, align 4 1490 %conv = fptosi float %0 to i32 1491 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1492 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 1493 %1 = load float, float* %arrayidx1, align 4 1494 %conv2 = fptosi float %1 to i32 1495 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1496 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 1497 %2 = load float, float* %arrayidx4, align 4 1498 %conv5 = fptosi float %2 to i32 1499 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1500 %3 = load float, float* %ptr, align 4 1501 %conv8 = fptosi float %3 to i32 1502 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1503 ret <4 x i32> %vecinit9 1504} 1505 1506define <4 x i32> @fromDiffMemVarAConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1507; P9BE-LABEL: fromDiffMemVarAConvftoi: 1508; P9BE: # %bb.0: # %entry 1509; P9BE-NEXT: sldi r4, r4, 2 1510; P9BE-NEXT: lfsux f0, r3, r4 1511; P9BE-NEXT: lfs f1, 12(r3) 1512; P9BE-NEXT: lfs f2, 4(r3) 1513; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1514; P9BE-NEXT: xvcvdpsp v2, vs1 1515; P9BE-NEXT: lfs f1, 8(r3) 1516; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1517; P9BE-NEXT: xvcvdpsp v3, vs0 1518; P9BE-NEXT: vmrgew v2, v3, v2 1519; P9BE-NEXT: xvcvspsxws v2, v2 1520; P9BE-NEXT: blr 1521; 1522; P9LE-LABEL: fromDiffMemVarAConvftoi: 1523; P9LE: # %bb.0: # %entry 1524; P9LE-NEXT: sldi r4, r4, 2 1525; P9LE-NEXT: lfsux f0, r3, r4 1526; P9LE-NEXT: lfs f1, 8(r3) 1527; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1528; P9LE-NEXT: lfs f1, 12(r3) 1529; P9LE-NEXT: xvcvdpsp v2, vs0 1530; P9LE-NEXT: lfs f0, 4(r3) 1531; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1532; P9LE-NEXT: xvcvdpsp v3, vs0 1533; P9LE-NEXT: vmrgew v2, v3, v2 1534; P9LE-NEXT: xvcvspsxws v2, v2 1535; P9LE-NEXT: blr 1536; 1537; P8BE-LABEL: fromDiffMemVarAConvftoi: 1538; P8BE: # %bb.0: # %entry 1539; P8BE-NEXT: sldi r4, r4, 2 1540; P8BE-NEXT: lfsux f0, r3, r4 1541; P8BE-NEXT: lfs f1, 12(r3) 1542; P8BE-NEXT: lfs f2, 4(r3) 1543; P8BE-NEXT: lfs f3, 8(r3) 1544; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1545; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1546; P8BE-NEXT: xvcvdpsp v2, vs1 1547; P8BE-NEXT: xvcvdpsp v3, vs0 1548; P8BE-NEXT: vmrgew v2, v3, v2 1549; P8BE-NEXT: xvcvspsxws v2, v2 1550; P8BE-NEXT: blr 1551; 1552; P8LE-LABEL: fromDiffMemVarAConvftoi: 1553; P8LE: # %bb.0: # %entry 1554; P8LE-NEXT: sldi r4, r4, 2 1555; P8LE-NEXT: lfsux f0, r3, r4 1556; P8LE-NEXT: lfs f1, 8(r3) 1557; P8LE-NEXT: lfs f2, 4(r3) 1558; P8LE-NEXT: lfs f3, 12(r3) 1559; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1560; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1561; P8LE-NEXT: xvcvdpsp v2, vs0 1562; P8LE-NEXT: xvcvdpsp v3, vs1 1563; P8LE-NEXT: vmrgew v2, v3, v2 1564; P8LE-NEXT: xvcvspsxws v2, v2 1565; P8LE-NEXT: blr 1566entry: 1567 %idxprom = sext i32 %elem to i64 1568 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1569 %0 = load float, float* %arrayidx, align 4 1570 %conv = fptosi float %0 to i32 1571 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1572 %add = add nsw i32 %elem, 1 1573 %idxprom1 = sext i32 %add to i64 1574 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1575 %1 = load float, float* %arrayidx2, align 4 1576 %conv3 = fptosi float %1 to i32 1577 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1578 %add5 = add nsw i32 %elem, 2 1579 %idxprom6 = sext i32 %add5 to i64 1580 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1581 %2 = load float, float* %arrayidx7, align 4 1582 %conv8 = fptosi float %2 to i32 1583 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1584 %add10 = add nsw i32 %elem, 3 1585 %idxprom11 = sext i32 %add10 to i64 1586 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1587 %3 = load float, float* %arrayidx12, align 4 1588 %conv13 = fptosi float %3 to i32 1589 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1590 ret <4 x i32> %vecinit14 1591} 1592 1593define <4 x i32> @fromDiffMemVarDConvftoi(float* nocapture readonly %arr, i32 signext %elem) { 1594; P9BE-LABEL: fromDiffMemVarDConvftoi: 1595; P9BE: # %bb.0: # %entry 1596; P9BE-NEXT: sldi r4, r4, 2 1597; P9BE-NEXT: lfsux f0, r3, r4 1598; P9BE-NEXT: lfs f1, -12(r3) 1599; P9BE-NEXT: lfs f2, -4(r3) 1600; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1601; P9BE-NEXT: xvcvdpsp v2, vs1 1602; P9BE-NEXT: lfs f1, -8(r3) 1603; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1604; P9BE-NEXT: xvcvdpsp v3, vs0 1605; P9BE-NEXT: vmrgew v2, v3, v2 1606; P9BE-NEXT: xvcvspsxws v2, v2 1607; P9BE-NEXT: blr 1608; 1609; P9LE-LABEL: fromDiffMemVarDConvftoi: 1610; P9LE: # %bb.0: # %entry 1611; P9LE-NEXT: sldi r4, r4, 2 1612; P9LE-NEXT: lfsux f0, r3, r4 1613; P9LE-NEXT: lfs f1, -8(r3) 1614; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1615; P9LE-NEXT: lfs f1, -12(r3) 1616; P9LE-NEXT: xvcvdpsp v2, vs0 1617; P9LE-NEXT: lfs f0, -4(r3) 1618; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1619; P9LE-NEXT: xvcvdpsp v3, vs0 1620; P9LE-NEXT: vmrgew v2, v3, v2 1621; P9LE-NEXT: xvcvspsxws v2, v2 1622; P9LE-NEXT: blr 1623; 1624; P8BE-LABEL: fromDiffMemVarDConvftoi: 1625; P8BE: # %bb.0: # %entry 1626; P8BE-NEXT: sldi r4, r4, 2 1627; P8BE-NEXT: lfsux f0, r3, r4 1628; P8BE-NEXT: lfs f1, -12(r3) 1629; P8BE-NEXT: lfs f2, -4(r3) 1630; P8BE-NEXT: lfs f3, -8(r3) 1631; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1632; P8BE-NEXT: xxmrghd vs0, vs0, vs3 1633; P8BE-NEXT: xvcvdpsp v2, vs1 1634; P8BE-NEXT: xvcvdpsp v3, vs0 1635; P8BE-NEXT: vmrgew v2, v3, v2 1636; P8BE-NEXT: xvcvspsxws v2, v2 1637; P8BE-NEXT: blr 1638; 1639; P8LE-LABEL: fromDiffMemVarDConvftoi: 1640; P8LE: # %bb.0: # %entry 1641; P8LE-NEXT: sldi r4, r4, 2 1642; P8LE-NEXT: lfsux f0, r3, r4 1643; P8LE-NEXT: lfs f1, -8(r3) 1644; P8LE-NEXT: lfs f2, -4(r3) 1645; P8LE-NEXT: lfs f3, -12(r3) 1646; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1647; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1648; P8LE-NEXT: xvcvdpsp v2, vs0 1649; P8LE-NEXT: xvcvdpsp v3, vs1 1650; P8LE-NEXT: vmrgew v2, v3, v2 1651; P8LE-NEXT: xvcvspsxws v2, v2 1652; P8LE-NEXT: blr 1653entry: 1654 %idxprom = sext i32 %elem to i64 1655 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 1656 %0 = load float, float* %arrayidx, align 4 1657 %conv = fptosi float %0 to i32 1658 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1659 %sub = add nsw i32 %elem, -1 1660 %idxprom1 = sext i32 %sub to i64 1661 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 1662 %1 = load float, float* %arrayidx2, align 4 1663 %conv3 = fptosi float %1 to i32 1664 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1665 %sub5 = add nsw i32 %elem, -2 1666 %idxprom6 = sext i32 %sub5 to i64 1667 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 1668 %2 = load float, float* %arrayidx7, align 4 1669 %conv8 = fptosi float %2 to i32 1670 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1671 %sub10 = add nsw i32 %elem, -3 1672 %idxprom11 = sext i32 %sub10 to i64 1673 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 1674 %3 = load float, float* %arrayidx12, align 4 1675 %conv13 = fptosi float %3 to i32 1676 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1677 ret <4 x i32> %vecinit14 1678; FIXME: implement finding consecutive loads with pre-inc 1679} 1680 1681define <4 x i32> @spltRegValConvftoi(float %val) { 1682; P9BE-LABEL: spltRegValConvftoi: 1683; P9BE: # %bb.0: # %entry 1684; P9BE-NEXT: xscvdpsxws f0, f1 1685; P9BE-NEXT: xxspltw v2, vs0, 1 1686; P9BE-NEXT: blr 1687; 1688; P9LE-LABEL: spltRegValConvftoi: 1689; P9LE: # %bb.0: # %entry 1690; P9LE-NEXT: xscvdpsxws f0, f1 1691; P9LE-NEXT: xxspltw v2, vs0, 1 1692; P9LE-NEXT: blr 1693; 1694; P8BE-LABEL: spltRegValConvftoi: 1695; P8BE: # %bb.0: # %entry 1696; P8BE-NEXT: xscvdpsxws f0, f1 1697; P8BE-NEXT: xxspltw v2, vs0, 1 1698; P8BE-NEXT: blr 1699; 1700; P8LE-LABEL: spltRegValConvftoi: 1701; P8LE: # %bb.0: # %entry 1702; P8LE-NEXT: xscvdpsxws f0, f1 1703; P8LE-NEXT: xxspltw v2, vs0, 1 1704; P8LE-NEXT: blr 1705entry: 1706 %conv = fptosi float %val to i32 1707 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1708 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1709 ret <4 x i32> %splat.splat 1710} 1711 1712define <4 x i32> @spltMemValConvftoi(float* nocapture readonly %ptr) { 1713; P9BE-LABEL: spltMemValConvftoi: 1714; P9BE: # %bb.0: # %entry 1715; P9BE-NEXT: lxvwsx vs0, 0, r3 1716; P9BE-NEXT: xvcvspsxws v2, vs0 1717; P9BE-NEXT: blr 1718; 1719; P9LE-LABEL: spltMemValConvftoi: 1720; P9LE: # %bb.0: # %entry 1721; P9LE-NEXT: lxvwsx vs0, 0, r3 1722; P9LE-NEXT: xvcvspsxws v2, vs0 1723; P9LE-NEXT: blr 1724; 1725; P8BE-LABEL: spltMemValConvftoi: 1726; P8BE: # %bb.0: # %entry 1727; P8BE-NEXT: lfsx f0, 0, r3 1728; P8BE-NEXT: xscvdpsxws f0, f0 1729; P8BE-NEXT: xxspltw v2, vs0, 1 1730; P8BE-NEXT: blr 1731; 1732; P8LE-LABEL: spltMemValConvftoi: 1733; P8LE: # %bb.0: # %entry 1734; P8LE-NEXT: lfsx f0, 0, r3 1735; P8LE-NEXT: xscvdpsxws f0, f0 1736; P8LE-NEXT: xxspltw v2, vs0, 1 1737; P8LE-NEXT: blr 1738entry: 1739 %0 = load float, float* %ptr, align 4 1740 %conv = fptosi float %0 to i32 1741 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1742 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1743 ret <4 x i32> %splat.splat 1744} 1745 1746define <4 x i32> @spltCnstConvdtoi() { 1747; P9BE-LABEL: spltCnstConvdtoi: 1748; P9BE: # %bb.0: # %entry 1749; P9BE-NEXT: vspltisw v2, 4 1750; P9BE-NEXT: blr 1751; 1752; P9LE-LABEL: spltCnstConvdtoi: 1753; P9LE: # %bb.0: # %entry 1754; P9LE-NEXT: vspltisw v2, 4 1755; P9LE-NEXT: blr 1756; 1757; P8BE-LABEL: spltCnstConvdtoi: 1758; P8BE: # %bb.0: # %entry 1759; P8BE-NEXT: vspltisw v2, 4 1760; P8BE-NEXT: blr 1761; 1762; P8LE-LABEL: spltCnstConvdtoi: 1763; P8LE: # %bb.0: # %entry 1764; P8LE-NEXT: vspltisw v2, 4 1765; P8LE-NEXT: blr 1766entry: 1767 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1768} 1769 1770define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1771; P9BE-LABEL: fromRegsConvdtoi: 1772; P9BE: # %bb.0: # %entry 1773; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1774; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1775; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1776; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1777; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1778; P9BE-NEXT: xvcvdpsxws v2, vs0 1779; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1780; P9BE-NEXT: xvcvdpsxws v3, vs0 1781; P9BE-NEXT: vmrgew v2, v3, v2 1782; P9BE-NEXT: blr 1783; 1784; P9LE-LABEL: fromRegsConvdtoi: 1785; P9LE: # %bb.0: # %entry 1786; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1787; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1788; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1789; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1790; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1791; P9LE-NEXT: xvcvdpsxws v2, vs0 1792; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1793; P9LE-NEXT: xvcvdpsxws v3, vs0 1794; P9LE-NEXT: vmrgew v2, v3, v2 1795; P9LE-NEXT: blr 1796; 1797; P8BE-LABEL: fromRegsConvdtoi: 1798; P8BE: # %bb.0: # %entry 1799; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1800; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1801; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1802; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1803; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1804; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1805; P8BE-NEXT: xvcvdpsxws v2, vs0 1806; P8BE-NEXT: xvcvdpsxws v3, vs1 1807; P8BE-NEXT: vmrgew v2, v3, v2 1808; P8BE-NEXT: blr 1809; 1810; P8LE-LABEL: fromRegsConvdtoi: 1811; P8LE: # %bb.0: # %entry 1812; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 1813; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 1814; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 1815; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 1816; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1817; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1818; P8LE-NEXT: xvcvdpsxws v2, vs0 1819; P8LE-NEXT: xvcvdpsxws v3, vs1 1820; P8LE-NEXT: vmrgew v2, v3, v2 1821; P8LE-NEXT: blr 1822entry: 1823 %conv = fptosi double %a to i32 1824 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1825 %conv1 = fptosi double %b to i32 1826 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1827 %conv3 = fptosi double %c to i32 1828 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1829 %conv5 = fptosi double %d to i32 1830 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1831 ret <4 x i32> %vecinit6 1832} 1833 1834define <4 x i32> @fromDiffConstsConvdtoi() { 1835; P9BE-LABEL: fromDiffConstsConvdtoi: 1836; P9BE: # %bb.0: # %entry 1837; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1838; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1839; P9BE-NEXT: lxvx v2, 0, r3 1840; P9BE-NEXT: blr 1841; 1842; P9LE-LABEL: fromDiffConstsConvdtoi: 1843; P9LE: # %bb.0: # %entry 1844; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1845; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1846; P9LE-NEXT: lxvx v2, 0, r3 1847; P9LE-NEXT: blr 1848; 1849; P8BE-LABEL: fromDiffConstsConvdtoi: 1850; P8BE: # %bb.0: # %entry 1851; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1852; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1853; P8BE-NEXT: lxvw4x v2, 0, r3 1854; P8BE-NEXT: blr 1855; 1856; P8LE-LABEL: fromDiffConstsConvdtoi: 1857; P8LE: # %bb.0: # %entry 1858; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1859; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1860; P8LE-NEXT: lvx v2, 0, r3 1861; P8LE-NEXT: blr 1862entry: 1863 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1864} 1865 1866define <4 x i32> @fromDiffMemConsAConvdtoi(double* nocapture readonly %ptr) { 1867; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1868; P9BE: # %bb.0: # %entry 1869; P9BE-NEXT: lxv vs0, 0(r3) 1870; P9BE-NEXT: lxv vs1, 16(r3) 1871; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1872; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1873; P9BE-NEXT: xvcvdpsxws v2, vs2 1874; P9BE-NEXT: xvcvdpsxws v3, vs0 1875; P9BE-NEXT: vmrgew v2, v3, v2 1876; P9BE-NEXT: blr 1877; 1878; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1879; P9LE: # %bb.0: # %entry 1880; P9LE-NEXT: lxv vs0, 0(r3) 1881; P9LE-NEXT: lxv vs1, 16(r3) 1882; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1883; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1884; P9LE-NEXT: xvcvdpsxws v2, vs2 1885; P9LE-NEXT: xvcvdpsxws v3, vs0 1886; P9LE-NEXT: vmrgew v2, v3, v2 1887; P9LE-NEXT: blr 1888; 1889; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1890; P8BE: # %bb.0: # %entry 1891; P8BE-NEXT: li r4, 16 1892; P8BE-NEXT: lxvd2x vs0, 0, r3 1893; P8BE-NEXT: lxvd2x vs1, r3, r4 1894; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1895; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1896; P8BE-NEXT: xvcvdpsxws v2, vs2 1897; P8BE-NEXT: xvcvdpsxws v3, vs0 1898; P8BE-NEXT: vmrgew v2, v3, v2 1899; P8BE-NEXT: blr 1900; 1901; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1902; P8LE: # %bb.0: # %entry 1903; P8LE-NEXT: li r4, 16 1904; P8LE-NEXT: lxvd2x vs0, 0, r3 1905; P8LE-NEXT: lxvd2x vs1, r3, r4 1906; P8LE-NEXT: xxswapd vs0, vs0 1907; P8LE-NEXT: xxswapd vs1, vs1 1908; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1909; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1910; P8LE-NEXT: xvcvdpsxws v2, vs2 1911; P8LE-NEXT: xvcvdpsxws v3, vs0 1912; P8LE-NEXT: vmrgew v2, v3, v2 1913; P8LE-NEXT: blr 1914entry: 1915 %0 = bitcast double* %ptr to <2 x double>* 1916 %1 = load <2 x double>, <2 x double>* %0, align 8 1917 %2 = fptosi <2 x double> %1 to <2 x i32> 1918 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 1919 %3 = bitcast double* %arrayidx4 to <2 x double>* 1920 %4 = load <2 x double>, <2 x double>* %3, align 8 1921 %5 = fptosi <2 x double> %4 to <2 x i32> 1922 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1923 ret <4 x i32> %vecinit9 1924} 1925 1926define <4 x i32> @fromDiffMemConsDConvdtoi(double* nocapture readonly %ptr) { 1927; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1928; P9BE: # %bb.0: # %entry 1929; P9BE-NEXT: lfd f0, 24(r3) 1930; P9BE-NEXT: lfd f1, 16(r3) 1931; P9BE-NEXT: lfd f2, 8(r3) 1932; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1933; P9BE-NEXT: lfd f3, 0(r3) 1934; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1935; P9BE-NEXT: xvcvdpsxws v2, vs1 1936; P9BE-NEXT: xvcvdpsxws v3, vs0 1937; P9BE-NEXT: vmrgew v2, v3, v2 1938; P9BE-NEXT: blr 1939; 1940; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1941; P9LE: # %bb.0: # %entry 1942; P9LE-NEXT: lfd f0, 24(r3) 1943; P9LE-NEXT: lfd f2, 8(r3) 1944; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1945; P9LE-NEXT: lfd f1, 16(r3) 1946; P9LE-NEXT: lfd f3, 0(r3) 1947; P9LE-NEXT: xvcvdpsxws v2, vs0 1948; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1949; P9LE-NEXT: xvcvdpsxws v3, vs0 1950; P9LE-NEXT: vmrgew v2, v3, v2 1951; P9LE-NEXT: blr 1952; 1953; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1954; P8BE: # %bb.0: # %entry 1955; P8BE-NEXT: lfdx f3, 0, r3 1956; P8BE-NEXT: lfd f0, 24(r3) 1957; P8BE-NEXT: lfd f1, 8(r3) 1958; P8BE-NEXT: lfd f2, 16(r3) 1959; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1960; P8BE-NEXT: xxmrghd vs1, vs2, vs3 1961; P8BE-NEXT: xvcvdpsxws v2, vs0 1962; P8BE-NEXT: xvcvdpsxws v3, vs1 1963; P8BE-NEXT: vmrgew v2, v2, v3 1964; P8BE-NEXT: blr 1965; 1966; P8LE-LABEL: fromDiffMemConsDConvdtoi: 1967; P8LE: # %bb.0: # %entry 1968; P8LE-NEXT: lfdx f3, 0, r3 1969; P8LE-NEXT: lfd f0, 24(r3) 1970; P8LE-NEXT: lfd f1, 8(r3) 1971; P8LE-NEXT: lfd f2, 16(r3) 1972; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1973; P8LE-NEXT: xxmrghd vs1, vs3, vs2 1974; P8LE-NEXT: xvcvdpsxws v2, vs0 1975; P8LE-NEXT: xvcvdpsxws v3, vs1 1976; P8LE-NEXT: vmrgew v2, v3, v2 1977; P8LE-NEXT: blr 1978entry: 1979 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 1980 %0 = load double, double* %arrayidx, align 8 1981 %conv = fptosi double %0 to i32 1982 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1983 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 1984 %1 = load double, double* %arrayidx1, align 8 1985 %conv2 = fptosi double %1 to i32 1986 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1987 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 1988 %2 = load double, double* %arrayidx4, align 8 1989 %conv5 = fptosi double %2 to i32 1990 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1991 %3 = load double, double* %ptr, align 8 1992 %conv8 = fptosi double %3 to i32 1993 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1994 ret <4 x i32> %vecinit9 1995} 1996 1997define <4 x i32> @fromDiffMemVarAConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 1998; P9BE-LABEL: fromDiffMemVarAConvdtoi: 1999; P9BE: # %bb.0: # %entry 2000; P9BE-NEXT: sldi r4, r4, 3 2001; P9BE-NEXT: lfdux f0, r3, r4 2002; P9BE-NEXT: lfd f1, 8(r3) 2003; P9BE-NEXT: lfd f2, 16(r3) 2004; P9BE-NEXT: lfd f3, 24(r3) 2005; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2006; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2007; P9BE-NEXT: xvcvdpsxws v2, vs1 2008; P9BE-NEXT: xvcvdpsxws v3, vs0 2009; P9BE-NEXT: vmrgew v2, v3, v2 2010; P9BE-NEXT: blr 2011; 2012; P9LE-LABEL: fromDiffMemVarAConvdtoi: 2013; P9LE: # %bb.0: # %entry 2014; P9LE-NEXT: sldi r4, r4, 3 2015; P9LE-NEXT: lfdux f0, r3, r4 2016; P9LE-NEXT: lfd f2, 16(r3) 2017; P9LE-NEXT: lfd f1, 8(r3) 2018; P9LE-NEXT: lfd f3, 24(r3) 2019; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2020; P9LE-NEXT: xvcvdpsxws v2, vs0 2021; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2022; P9LE-NEXT: xvcvdpsxws v3, vs0 2023; P9LE-NEXT: vmrgew v2, v3, v2 2024; P9LE-NEXT: blr 2025; 2026; P8BE-LABEL: fromDiffMemVarAConvdtoi: 2027; P8BE: # %bb.0: # %entry 2028; P8BE-NEXT: sldi r4, r4, 3 2029; P8BE-NEXT: lfdux f0, r3, r4 2030; P8BE-NEXT: lfd f1, 8(r3) 2031; P8BE-NEXT: lfd f2, 24(r3) 2032; P8BE-NEXT: lfd f3, 16(r3) 2033; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2034; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2035; P8BE-NEXT: xvcvdpsxws v2, vs1 2036; P8BE-NEXT: xvcvdpsxws v3, vs0 2037; P8BE-NEXT: vmrgew v2, v3, v2 2038; P8BE-NEXT: blr 2039; 2040; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2041; P8LE: # %bb.0: # %entry 2042; P8LE-NEXT: sldi r4, r4, 3 2043; P8LE-NEXT: lfdux f0, r3, r4 2044; P8LE-NEXT: lfd f1, 16(r3) 2045; P8LE-NEXT: lfd f2, 8(r3) 2046; P8LE-NEXT: lfd f3, 24(r3) 2047; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2048; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2049; P8LE-NEXT: xvcvdpsxws v2, vs0 2050; P8LE-NEXT: xvcvdpsxws v3, vs1 2051; P8LE-NEXT: vmrgew v2, v3, v2 2052; P8LE-NEXT: blr 2053entry: 2054 %idxprom = sext i32 %elem to i64 2055 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2056 %0 = load double, double* %arrayidx, align 8 2057 %conv = fptosi double %0 to i32 2058 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2059 %add = add nsw i32 %elem, 1 2060 %idxprom1 = sext i32 %add to i64 2061 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2062 %1 = load double, double* %arrayidx2, align 8 2063 %conv3 = fptosi double %1 to i32 2064 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2065 %add5 = add nsw i32 %elem, 2 2066 %idxprom6 = sext i32 %add5 to i64 2067 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2068 %2 = load double, double* %arrayidx7, align 8 2069 %conv8 = fptosi double %2 to i32 2070 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2071 %add10 = add nsw i32 %elem, 3 2072 %idxprom11 = sext i32 %add10 to i64 2073 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2074 %3 = load double, double* %arrayidx12, align 8 2075 %conv13 = fptosi double %3 to i32 2076 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2077 ret <4 x i32> %vecinit14 2078} 2079 2080define <4 x i32> @fromDiffMemVarDConvdtoi(double* nocapture readonly %arr, i32 signext %elem) { 2081; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2082; P9BE: # %bb.0: # %entry 2083; P9BE-NEXT: sldi r4, r4, 3 2084; P9BE-NEXT: lfdux f0, r3, r4 2085; P9BE-NEXT: lfd f1, -8(r3) 2086; P9BE-NEXT: lfd f2, -16(r3) 2087; P9BE-NEXT: lfd f3, -24(r3) 2088; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2089; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2090; P9BE-NEXT: xvcvdpsxws v2, vs1 2091; P9BE-NEXT: xvcvdpsxws v3, vs0 2092; P9BE-NEXT: vmrgew v2, v3, v2 2093; P9BE-NEXT: blr 2094; 2095; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2096; P9LE: # %bb.0: # %entry 2097; P9LE-NEXT: sldi r4, r4, 3 2098; P9LE-NEXT: lfdux f0, r3, r4 2099; P9LE-NEXT: lfd f2, -16(r3) 2100; P9LE-NEXT: lfd f1, -8(r3) 2101; P9LE-NEXT: lfd f3, -24(r3) 2102; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2103; P9LE-NEXT: xvcvdpsxws v2, vs0 2104; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2105; P9LE-NEXT: xvcvdpsxws v3, vs0 2106; P9LE-NEXT: vmrgew v2, v3, v2 2107; P9LE-NEXT: blr 2108; 2109; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2110; P8BE: # %bb.0: # %entry 2111; P8BE-NEXT: sldi r4, r4, 3 2112; P8BE-NEXT: lfdux f0, r3, r4 2113; P8BE-NEXT: lfd f1, -8(r3) 2114; P8BE-NEXT: lfd f2, -24(r3) 2115; P8BE-NEXT: lfd f3, -16(r3) 2116; P8BE-NEXT: xxmrghd vs1, vs1, vs2 2117; P8BE-NEXT: xxmrghd vs0, vs0, vs3 2118; P8BE-NEXT: xvcvdpsxws v2, vs1 2119; P8BE-NEXT: xvcvdpsxws v3, vs0 2120; P8BE-NEXT: vmrgew v2, v3, v2 2121; P8BE-NEXT: blr 2122; 2123; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2124; P8LE: # %bb.0: # %entry 2125; P8LE-NEXT: sldi r4, r4, 3 2126; P8LE-NEXT: lfdux f0, r3, r4 2127; P8LE-NEXT: lfd f1, -16(r3) 2128; P8LE-NEXT: lfd f2, -8(r3) 2129; P8LE-NEXT: lfd f3, -24(r3) 2130; P8LE-NEXT: xxmrghd vs0, vs1, vs0 2131; P8LE-NEXT: xxmrghd vs1, vs3, vs2 2132; P8LE-NEXT: xvcvdpsxws v2, vs0 2133; P8LE-NEXT: xvcvdpsxws v3, vs1 2134; P8LE-NEXT: vmrgew v2, v3, v2 2135; P8LE-NEXT: blr 2136entry: 2137 %idxprom = sext i32 %elem to i64 2138 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 2139 %0 = load double, double* %arrayidx, align 8 2140 %conv = fptosi double %0 to i32 2141 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2142 %sub = add nsw i32 %elem, -1 2143 %idxprom1 = sext i32 %sub to i64 2144 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 2145 %1 = load double, double* %arrayidx2, align 8 2146 %conv3 = fptosi double %1 to i32 2147 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2148 %sub5 = add nsw i32 %elem, -2 2149 %idxprom6 = sext i32 %sub5 to i64 2150 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 2151 %2 = load double, double* %arrayidx7, align 8 2152 %conv8 = fptosi double %2 to i32 2153 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2154 %sub10 = add nsw i32 %elem, -3 2155 %idxprom11 = sext i32 %sub10 to i64 2156 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 2157 %3 = load double, double* %arrayidx12, align 8 2158 %conv13 = fptosi double %3 to i32 2159 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2160 ret <4 x i32> %vecinit14 2161} 2162 2163define <4 x i32> @spltRegValConvdtoi(double %val) { 2164; P9BE-LABEL: spltRegValConvdtoi: 2165; P9BE: # %bb.0: # %entry 2166; P9BE-NEXT: xscvdpsxws f0, f1 2167; P9BE-NEXT: xxspltw v2, vs0, 1 2168; P9BE-NEXT: blr 2169; 2170; P9LE-LABEL: spltRegValConvdtoi: 2171; P9LE: # %bb.0: # %entry 2172; P9LE-NEXT: xscvdpsxws f0, f1 2173; P9LE-NEXT: xxspltw v2, vs0, 1 2174; P9LE-NEXT: blr 2175; 2176; P8BE-LABEL: spltRegValConvdtoi: 2177; P8BE: # %bb.0: # %entry 2178; P8BE-NEXT: xscvdpsxws f0, f1 2179; P8BE-NEXT: xxspltw v2, vs0, 1 2180; P8BE-NEXT: blr 2181; 2182; P8LE-LABEL: spltRegValConvdtoi: 2183; P8LE: # %bb.0: # %entry 2184; P8LE-NEXT: xscvdpsxws f0, f1 2185; P8LE-NEXT: xxspltw v2, vs0, 1 2186; P8LE-NEXT: blr 2187entry: 2188 %conv = fptosi double %val to i32 2189 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2190 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2191 ret <4 x i32> %splat.splat 2192} 2193 2194define <4 x i32> @spltMemValConvdtoi(double* nocapture readonly %ptr) { 2195; P9BE-LABEL: spltMemValConvdtoi: 2196; P9BE: # %bb.0: # %entry 2197; P9BE-NEXT: lfd f0, 0(r3) 2198; P9BE-NEXT: xscvdpsxws f0, f0 2199; P9BE-NEXT: xxspltw v2, vs0, 1 2200; P9BE-NEXT: blr 2201; 2202; P9LE-LABEL: spltMemValConvdtoi: 2203; P9LE: # %bb.0: # %entry 2204; P9LE-NEXT: lfd f0, 0(r3) 2205; P9LE-NEXT: xscvdpsxws f0, f0 2206; P9LE-NEXT: xxspltw v2, vs0, 1 2207; P9LE-NEXT: blr 2208; 2209; P8BE-LABEL: spltMemValConvdtoi: 2210; P8BE: # %bb.0: # %entry 2211; P8BE-NEXT: lfdx f0, 0, r3 2212; P8BE-NEXT: xscvdpsxws f0, f0 2213; P8BE-NEXT: xxspltw v2, vs0, 1 2214; P8BE-NEXT: blr 2215; 2216; P8LE-LABEL: spltMemValConvdtoi: 2217; P8LE: # %bb.0: # %entry 2218; P8LE-NEXT: lfdx f0, 0, r3 2219; P8LE-NEXT: xscvdpsxws f0, f0 2220; P8LE-NEXT: xxspltw v2, vs0, 1 2221; P8LE-NEXT: blr 2222entry: 2223 %0 = load double, double* %ptr, align 8 2224 %conv = fptosi double %0 to i32 2225 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2226 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2227 ret <4 x i32> %splat.splat 2228} 2229 2230define <4 x i32> @allZeroui() { 2231; P9BE-LABEL: allZeroui: 2232; P9BE: # %bb.0: # %entry 2233; P9BE-NEXT: xxlxor v2, v2, v2 2234; P9BE-NEXT: blr 2235; 2236; P9LE-LABEL: allZeroui: 2237; P9LE: # %bb.0: # %entry 2238; P9LE-NEXT: xxlxor v2, v2, v2 2239; P9LE-NEXT: blr 2240; 2241; P8BE-LABEL: allZeroui: 2242; P8BE: # %bb.0: # %entry 2243; P8BE-NEXT: xxlxor v2, v2, v2 2244; P8BE-NEXT: blr 2245; 2246; P8LE-LABEL: allZeroui: 2247; P8LE: # %bb.0: # %entry 2248; P8LE-NEXT: xxlxor v2, v2, v2 2249; P8LE-NEXT: blr 2250entry: 2251 ret <4 x i32> zeroinitializer 2252} 2253 2254define <4 x i32> @spltConst1ui() { 2255; P9BE-LABEL: spltConst1ui: 2256; P9BE: # %bb.0: # %entry 2257; P9BE-NEXT: vspltisw v2, 1 2258; P9BE-NEXT: blr 2259; 2260; P9LE-LABEL: spltConst1ui: 2261; P9LE: # %bb.0: # %entry 2262; P9LE-NEXT: vspltisw v2, 1 2263; P9LE-NEXT: blr 2264; 2265; P8BE-LABEL: spltConst1ui: 2266; P8BE: # %bb.0: # %entry 2267; P8BE-NEXT: vspltisw v2, 1 2268; P8BE-NEXT: blr 2269; 2270; P8LE-LABEL: spltConst1ui: 2271; P8LE: # %bb.0: # %entry 2272; P8LE-NEXT: vspltisw v2, 1 2273; P8LE-NEXT: blr 2274entry: 2275 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2276} 2277 2278define <4 x i32> @spltConst16kui() { 2279; P9BE-LABEL: spltConst16kui: 2280; P9BE: # %bb.0: # %entry 2281; P9BE-NEXT: vspltisw v2, -15 2282; P9BE-NEXT: vsrw v2, v2, v2 2283; P9BE-NEXT: blr 2284; 2285; P9LE-LABEL: spltConst16kui: 2286; P9LE: # %bb.0: # %entry 2287; P9LE-NEXT: vspltisw v2, -15 2288; P9LE-NEXT: vsrw v2, v2, v2 2289; P9LE-NEXT: blr 2290; 2291; P8BE-LABEL: spltConst16kui: 2292; P8BE: # %bb.0: # %entry 2293; P8BE-NEXT: vspltisw v2, -15 2294; P8BE-NEXT: vsrw v2, v2, v2 2295; P8BE-NEXT: blr 2296; 2297; P8LE-LABEL: spltConst16kui: 2298; P8LE: # %bb.0: # %entry 2299; P8LE-NEXT: vspltisw v2, -15 2300; P8LE-NEXT: vsrw v2, v2, v2 2301; P8LE-NEXT: blr 2302entry: 2303 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2304} 2305 2306define <4 x i32> @spltConst32kui() { 2307; P9BE-LABEL: spltConst32kui: 2308; P9BE: # %bb.0: # %entry 2309; P9BE-NEXT: vspltisw v2, -16 2310; P9BE-NEXT: vsrw v2, v2, v2 2311; P9BE-NEXT: blr 2312; 2313; P9LE-LABEL: spltConst32kui: 2314; P9LE: # %bb.0: # %entry 2315; P9LE-NEXT: vspltisw v2, -16 2316; P9LE-NEXT: vsrw v2, v2, v2 2317; P9LE-NEXT: blr 2318; 2319; P8BE-LABEL: spltConst32kui: 2320; P8BE: # %bb.0: # %entry 2321; P8BE-NEXT: vspltisw v2, -16 2322; P8BE-NEXT: vsrw v2, v2, v2 2323; P8BE-NEXT: blr 2324; 2325; P8LE-LABEL: spltConst32kui: 2326; P8LE: # %bb.0: # %entry 2327; P8LE-NEXT: vspltisw v2, -16 2328; P8LE-NEXT: vsrw v2, v2, v2 2329; P8LE-NEXT: blr 2330entry: 2331 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2332} 2333 2334define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2335; P9BE-LABEL: fromRegsui: 2336; P9BE: # %bb.0: # %entry 2337; P9BE-NEXT: rldimi r6, r5, 32, 0 2338; P9BE-NEXT: rldimi r4, r3, 32, 0 2339; P9BE-NEXT: mtvsrdd v2, r4, r6 2340; P9BE-NEXT: blr 2341; 2342; P9LE-LABEL: fromRegsui: 2343; P9LE: # %bb.0: # %entry 2344; P9LE-NEXT: rldimi r3, r4, 32, 0 2345; P9LE-NEXT: rldimi r5, r6, 32, 0 2346; P9LE-NEXT: mtvsrdd v2, r5, r3 2347; P9LE-NEXT: blr 2348; 2349; P8BE-LABEL: fromRegsui: 2350; P8BE: # %bb.0: # %entry 2351; P8BE-NEXT: rldimi r6, r5, 32, 0 2352; P8BE-NEXT: rldimi r4, r3, 32, 0 2353; P8BE-NEXT: mtfprd f0, r6 2354; P8BE-NEXT: mtfprd f1, r4 2355; P8BE-NEXT: xxmrghd v2, vs1, vs0 2356; P8BE-NEXT: blr 2357; 2358; P8LE-LABEL: fromRegsui: 2359; P8LE: # %bb.0: # %entry 2360; P8LE-NEXT: rldimi r3, r4, 32, 0 2361; P8LE-NEXT: rldimi r5, r6, 32, 0 2362; P8LE-NEXT: mtfprd f0, r3 2363; P8LE-NEXT: mtfprd f1, r5 2364; P8LE-NEXT: xxmrghd v2, vs1, vs0 2365; P8LE-NEXT: blr 2366entry: 2367 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2368 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2369 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2370 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2371 ret <4 x i32> %vecinit3 2372} 2373 2374define <4 x i32> @fromDiffConstsui() { 2375; P9BE-LABEL: fromDiffConstsui: 2376; P9BE: # %bb.0: # %entry 2377; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2378; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2379; P9BE-NEXT: lxvx v2, 0, r3 2380; P9BE-NEXT: blr 2381; 2382; P9LE-LABEL: fromDiffConstsui: 2383; P9LE: # %bb.0: # %entry 2384; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2385; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2386; P9LE-NEXT: lxvx v2, 0, r3 2387; P9LE-NEXT: blr 2388; 2389; P8BE-LABEL: fromDiffConstsui: 2390; P8BE: # %bb.0: # %entry 2391; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2392; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2393; P8BE-NEXT: lxvw4x v2, 0, r3 2394; P8BE-NEXT: blr 2395; 2396; P8LE-LABEL: fromDiffConstsui: 2397; P8LE: # %bb.0: # %entry 2398; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2399; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2400; P8LE-NEXT: lvx v2, 0, r3 2401; P8LE-NEXT: blr 2402entry: 2403 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2404} 2405 2406define <4 x i32> @fromDiffMemConsAui(i32* nocapture readonly %arr) { 2407; P9BE-LABEL: fromDiffMemConsAui: 2408; P9BE: # %bb.0: # %entry 2409; P9BE-NEXT: lxv v2, 0(r3) 2410; P9BE-NEXT: blr 2411; 2412; P9LE-LABEL: fromDiffMemConsAui: 2413; P9LE: # %bb.0: # %entry 2414; P9LE-NEXT: lxv v2, 0(r3) 2415; P9LE-NEXT: blr 2416; 2417; P8BE-LABEL: fromDiffMemConsAui: 2418; P8BE: # %bb.0: # %entry 2419; P8BE-NEXT: lxvw4x v2, 0, r3 2420; P8BE-NEXT: blr 2421; 2422; P8LE-LABEL: fromDiffMemConsAui: 2423; P8LE: # %bb.0: # %entry 2424; P8LE-NEXT: lxvd2x vs0, 0, r3 2425; P8LE-NEXT: xxswapd v2, vs0 2426; P8LE-NEXT: blr 2427entry: 2428 %0 = load i32, i32* %arr, align 4 2429 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2430 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 1 2431 %1 = load i32, i32* %arrayidx1, align 4 2432 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2433 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2434 %2 = load i32, i32* %arrayidx3, align 4 2435 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2436 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 3 2437 %3 = load i32, i32* %arrayidx5, align 4 2438 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2439 ret <4 x i32> %vecinit6 2440} 2441 2442define <4 x i32> @fromDiffMemConsDui(i32* nocapture readonly %arr) { 2443; P9BE-LABEL: fromDiffMemConsDui: 2444; P9BE: # %bb.0: # %entry 2445; P9BE-NEXT: lxv v2, 0(r3) 2446; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2447; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2448; P9BE-NEXT: lxvx v3, 0, r3 2449; P9BE-NEXT: vperm v2, v2, v2, v3 2450; P9BE-NEXT: blr 2451; 2452; P9LE-LABEL: fromDiffMemConsDui: 2453; P9LE: # %bb.0: # %entry 2454; P9LE-NEXT: lxvw4x v2, 0, r3 2455; P9LE-NEXT: blr 2456; 2457; P8BE-LABEL: fromDiffMemConsDui: 2458; P8BE: # %bb.0: # %entry 2459; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2460; P8BE-NEXT: lxvw4x v2, 0, r3 2461; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l 2462; P8BE-NEXT: lxvw4x v3, 0, r4 2463; P8BE-NEXT: vperm v2, v2, v2, v3 2464; P8BE-NEXT: blr 2465; 2466; P8LE-LABEL: fromDiffMemConsDui: 2467; P8LE: # %bb.0: # %entry 2468; P8LE-NEXT: lxvd2x vs0, 0, r3 2469; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha 2470; P8LE-NEXT: addi r3, r4, .LCPI39_0@toc@l 2471; P8LE-NEXT: lvx v2, 0, r3 2472; P8LE-NEXT: xxswapd v3, vs0 2473; P8LE-NEXT: vperm v2, v3, v3, v2 2474; P8LE-NEXT: blr 2475entry: 2476 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 3 2477 %0 = load i32, i32* %arrayidx, align 4 2478 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2479 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 2 2480 %1 = load i32, i32* %arrayidx1, align 4 2481 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2482 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 1 2483 %2 = load i32, i32* %arrayidx3, align 4 2484 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2485 %3 = load i32, i32* %arr, align 4 2486 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2487 ret <4 x i32> %vecinit6 2488} 2489 2490define <4 x i32> @fromDiffMemVarAui(i32* nocapture readonly %arr, i32 signext %elem) { 2491; P9BE-LABEL: fromDiffMemVarAui: 2492; P9BE: # %bb.0: # %entry 2493; P9BE-NEXT: sldi r4, r4, 2 2494; P9BE-NEXT: lxvx v2, r3, r4 2495; P9BE-NEXT: blr 2496; 2497; P9LE-LABEL: fromDiffMemVarAui: 2498; P9LE: # %bb.0: # %entry 2499; P9LE-NEXT: sldi r4, r4, 2 2500; P9LE-NEXT: lxvx v2, r3, r4 2501; P9LE-NEXT: blr 2502; 2503; P8BE-LABEL: fromDiffMemVarAui: 2504; P8BE: # %bb.0: # %entry 2505; P8BE-NEXT: sldi r4, r4, 2 2506; P8BE-NEXT: lxvw4x v2, r3, r4 2507; P8BE-NEXT: blr 2508; 2509; P8LE-LABEL: fromDiffMemVarAui: 2510; P8LE: # %bb.0: # %entry 2511; P8LE-NEXT: sldi r4, r4, 2 2512; P8LE-NEXT: lxvd2x vs0, r3, r4 2513; P8LE-NEXT: xxswapd v2, vs0 2514; P8LE-NEXT: blr 2515entry: 2516 %idxprom = sext i32 %elem to i64 2517 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2518 %0 = load i32, i32* %arrayidx, align 4 2519 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2520 %add = add nsw i32 %elem, 1 2521 %idxprom1 = sext i32 %add to i64 2522 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2523 %1 = load i32, i32* %arrayidx2, align 4 2524 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2525 %add4 = add nsw i32 %elem, 2 2526 %idxprom5 = sext i32 %add4 to i64 2527 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2528 %2 = load i32, i32* %arrayidx6, align 4 2529 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2530 %add8 = add nsw i32 %elem, 3 2531 %idxprom9 = sext i32 %add8 to i64 2532 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2533 %3 = load i32, i32* %arrayidx10, align 4 2534 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2535 ret <4 x i32> %vecinit11 2536} 2537 2538define <4 x i32> @fromDiffMemVarDui(i32* nocapture readonly %arr, i32 signext %elem) { 2539; P9BE-LABEL: fromDiffMemVarDui: 2540; P9BE: # %bb.0: # %entry 2541; P9BE-NEXT: sldi r4, r4, 2 2542; P9BE-NEXT: add r3, r3, r4 2543; P9BE-NEXT: addi r3, r3, -12 2544; P9BE-NEXT: lxvx v2, 0, r3 2545; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2546; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2547; P9BE-NEXT: lxvx v3, 0, r3 2548; P9BE-NEXT: vperm v2, v2, v2, v3 2549; P9BE-NEXT: blr 2550; 2551; P9LE-LABEL: fromDiffMemVarDui: 2552; P9LE: # %bb.0: # %entry 2553; P9LE-NEXT: sldi r4, r4, 2 2554; P9LE-NEXT: add r3, r3, r4 2555; P9LE-NEXT: addi r3, r3, -12 2556; P9LE-NEXT: lxvx v2, 0, r3 2557; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2558; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2559; P9LE-NEXT: lxvx v3, 0, r3 2560; P9LE-NEXT: vperm v2, v2, v2, v3 2561; P9LE-NEXT: blr 2562; 2563; P8BE-LABEL: fromDiffMemVarDui: 2564; P8BE: # %bb.0: # %entry 2565; P8BE-NEXT: sldi r4, r4, 2 2566; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2567; P8BE-NEXT: add r3, r3, r4 2568; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l 2569; P8BE-NEXT: addi r3, r3, -12 2570; P8BE-NEXT: lxvw4x v3, 0, r4 2571; P8BE-NEXT: lxvw4x v2, 0, r3 2572; P8BE-NEXT: vperm v2, v2, v2, v3 2573; P8BE-NEXT: blr 2574; 2575; P8LE-LABEL: fromDiffMemVarDui: 2576; P8LE: # %bb.0: # %entry 2577; P8LE-NEXT: sldi r4, r4, 2 2578; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2579; P8LE-NEXT: add r3, r3, r4 2580; P8LE-NEXT: addi r3, r3, -12 2581; P8LE-NEXT: lxvd2x vs0, 0, r3 2582; P8LE-NEXT: addi r3, r5, .LCPI41_0@toc@l 2583; P8LE-NEXT: lvx v3, 0, r3 2584; P8LE-NEXT: xxswapd v2, vs0 2585; P8LE-NEXT: vperm v2, v2, v2, v3 2586; P8LE-NEXT: blr 2587entry: 2588 %idxprom = sext i32 %elem to i64 2589 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2590 %0 = load i32, i32* %arrayidx, align 4 2591 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2592 %sub = add nsw i32 %elem, -1 2593 %idxprom1 = sext i32 %sub to i64 2594 %arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1 2595 %1 = load i32, i32* %arrayidx2, align 4 2596 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2597 %sub4 = add nsw i32 %elem, -2 2598 %idxprom5 = sext i32 %sub4 to i64 2599 %arrayidx6 = getelementptr inbounds i32, i32* %arr, i64 %idxprom5 2600 %2 = load i32, i32* %arrayidx6, align 4 2601 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2602 %sub8 = add nsw i32 %elem, -3 2603 %idxprom9 = sext i32 %sub8 to i64 2604 %arrayidx10 = getelementptr inbounds i32, i32* %arr, i64 %idxprom9 2605 %3 = load i32, i32* %arrayidx10, align 4 2606 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2607 ret <4 x i32> %vecinit11 2608} 2609 2610define <4 x i32> @fromRandMemConsui(i32* nocapture readonly %arr) { 2611; P9BE-LABEL: fromRandMemConsui: 2612; P9BE: # %bb.0: # %entry 2613; P9BE-NEXT: lwz r4, 16(r3) 2614; P9BE-NEXT: lwz r5, 72(r3) 2615; P9BE-NEXT: lwz r6, 8(r3) 2616; P9BE-NEXT: lwz r3, 352(r3) 2617; P9BE-NEXT: rldimi r3, r6, 32, 0 2618; P9BE-NEXT: rldimi r5, r4, 32, 0 2619; P9BE-NEXT: mtvsrdd v2, r5, r3 2620; P9BE-NEXT: blr 2621; 2622; P9LE-LABEL: fromRandMemConsui: 2623; P9LE: # %bb.0: # %entry 2624; P9LE-NEXT: lwz r4, 16(r3) 2625; P9LE-NEXT: lwz r5, 72(r3) 2626; P9LE-NEXT: lwz r6, 8(r3) 2627; P9LE-NEXT: lwz r3, 352(r3) 2628; P9LE-NEXT: rldimi r4, r5, 32, 0 2629; P9LE-NEXT: rldimi r6, r3, 32, 0 2630; P9LE-NEXT: mtvsrdd v2, r6, r4 2631; P9LE-NEXT: blr 2632; 2633; P8BE-LABEL: fromRandMemConsui: 2634; P8BE: # %bb.0: # %entry 2635; P8BE-NEXT: lwz r4, 8(r3) 2636; P8BE-NEXT: lwz r5, 352(r3) 2637; P8BE-NEXT: lwz r6, 16(r3) 2638; P8BE-NEXT: lwz r3, 72(r3) 2639; P8BE-NEXT: rldimi r5, r4, 32, 0 2640; P8BE-NEXT: rldimi r3, r6, 32, 0 2641; P8BE-NEXT: mtfprd f0, r5 2642; P8BE-NEXT: mtfprd f1, r3 2643; P8BE-NEXT: xxmrghd v2, vs1, vs0 2644; P8BE-NEXT: blr 2645; 2646; P8LE-LABEL: fromRandMemConsui: 2647; P8LE: # %bb.0: # %entry 2648; P8LE-NEXT: lwz r4, 16(r3) 2649; P8LE-NEXT: lwz r5, 72(r3) 2650; P8LE-NEXT: lwz r6, 8(r3) 2651; P8LE-NEXT: lwz r3, 352(r3) 2652; P8LE-NEXT: rldimi r4, r5, 32, 0 2653; P8LE-NEXT: rldimi r6, r3, 32, 0 2654; P8LE-NEXT: mtfprd f0, r4 2655; P8LE-NEXT: mtfprd f1, r6 2656; P8LE-NEXT: xxmrghd v2, vs1, vs0 2657; P8LE-NEXT: blr 2658entry: 2659 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 2660 %0 = load i32, i32* %arrayidx, align 4 2661 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2662 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 2663 %1 = load i32, i32* %arrayidx1, align 4 2664 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2665 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 2 2666 %2 = load i32, i32* %arrayidx3, align 4 2667 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2668 %arrayidx5 = getelementptr inbounds i32, i32* %arr, i64 88 2669 %3 = load i32, i32* %arrayidx5, align 4 2670 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2671 ret <4 x i32> %vecinit6 2672} 2673 2674define <4 x i32> @fromRandMemVarui(i32* nocapture readonly %arr, i32 signext %elem) { 2675; P9BE-LABEL: fromRandMemVarui: 2676; P9BE: # %bb.0: # %entry 2677; P9BE-NEXT: sldi r4, r4, 2 2678; P9BE-NEXT: add r3, r3, r4 2679; P9BE-NEXT: lwz r4, 16(r3) 2680; P9BE-NEXT: lwz r5, 4(r3) 2681; P9BE-NEXT: lwz r6, 8(r3) 2682; P9BE-NEXT: lwz r3, 32(r3) 2683; P9BE-NEXT: rldimi r3, r6, 32, 0 2684; P9BE-NEXT: rldimi r5, r4, 32, 0 2685; P9BE-NEXT: mtvsrdd v2, r5, r3 2686; P9BE-NEXT: blr 2687; 2688; P9LE-LABEL: fromRandMemVarui: 2689; P9LE: # %bb.0: # %entry 2690; P9LE-NEXT: sldi r4, r4, 2 2691; P9LE-NEXT: add r3, r3, r4 2692; P9LE-NEXT: lwz r4, 16(r3) 2693; P9LE-NEXT: lwz r5, 4(r3) 2694; P9LE-NEXT: lwz r6, 8(r3) 2695; P9LE-NEXT: lwz r3, 32(r3) 2696; P9LE-NEXT: rldimi r4, r5, 32, 0 2697; P9LE-NEXT: rldimi r6, r3, 32, 0 2698; P9LE-NEXT: mtvsrdd v2, r6, r4 2699; P9LE-NEXT: blr 2700; 2701; P8BE-LABEL: fromRandMemVarui: 2702; P8BE: # %bb.0: # %entry 2703; P8BE-NEXT: sldi r4, r4, 2 2704; P8BE-NEXT: add r3, r3, r4 2705; P8BE-NEXT: lwz r4, 8(r3) 2706; P8BE-NEXT: lwz r5, 32(r3) 2707; P8BE-NEXT: lwz r6, 16(r3) 2708; P8BE-NEXT: lwz r3, 4(r3) 2709; P8BE-NEXT: rldimi r5, r4, 32, 0 2710; P8BE-NEXT: rldimi r3, r6, 32, 0 2711; P8BE-NEXT: mtfprd f0, r5 2712; P8BE-NEXT: mtfprd f1, r3 2713; P8BE-NEXT: xxmrghd v2, vs1, vs0 2714; P8BE-NEXT: blr 2715; 2716; P8LE-LABEL: fromRandMemVarui: 2717; P8LE: # %bb.0: # %entry 2718; P8LE-NEXT: sldi r4, r4, 2 2719; P8LE-NEXT: add r3, r3, r4 2720; P8LE-NEXT: lwz r4, 16(r3) 2721; P8LE-NEXT: lwz r5, 4(r3) 2722; P8LE-NEXT: lwz r6, 8(r3) 2723; P8LE-NEXT: lwz r3, 32(r3) 2724; P8LE-NEXT: rldimi r4, r5, 32, 0 2725; P8LE-NEXT: rldimi r6, r3, 32, 0 2726; P8LE-NEXT: mtfprd f0, r4 2727; P8LE-NEXT: mtfprd f1, r6 2728; P8LE-NEXT: xxmrghd v2, vs1, vs0 2729; P8LE-NEXT: blr 2730entry: 2731 %add = add nsw i32 %elem, 4 2732 %idxprom = sext i32 %add to i64 2733 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom 2734 %0 = load i32, i32* %arrayidx, align 4 2735 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2736 %add1 = add nsw i32 %elem, 1 2737 %idxprom2 = sext i32 %add1 to i64 2738 %arrayidx3 = getelementptr inbounds i32, i32* %arr, i64 %idxprom2 2739 %1 = load i32, i32* %arrayidx3, align 4 2740 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2741 %add5 = add nsw i32 %elem, 2 2742 %idxprom6 = sext i32 %add5 to i64 2743 %arrayidx7 = getelementptr inbounds i32, i32* %arr, i64 %idxprom6 2744 %2 = load i32, i32* %arrayidx7, align 4 2745 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2746 %add9 = add nsw i32 %elem, 8 2747 %idxprom10 = sext i32 %add9 to i64 2748 %arrayidx11 = getelementptr inbounds i32, i32* %arr, i64 %idxprom10 2749 %3 = load i32, i32* %arrayidx11, align 4 2750 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2751 ret <4 x i32> %vecinit12 2752} 2753 2754define <4 x i32> @spltRegValui(i32 zeroext %val) { 2755; P9BE-LABEL: spltRegValui: 2756; P9BE: # %bb.0: # %entry 2757; P9BE-NEXT: mtvsrws v2, r3 2758; P9BE-NEXT: blr 2759; 2760; P9LE-LABEL: spltRegValui: 2761; P9LE: # %bb.0: # %entry 2762; P9LE-NEXT: mtvsrws v2, r3 2763; P9LE-NEXT: blr 2764; 2765; P8BE-LABEL: spltRegValui: 2766; P8BE: # %bb.0: # %entry 2767; P8BE-NEXT: mtfprwz f0, r3 2768; P8BE-NEXT: xxspltw v2, vs0, 1 2769; P8BE-NEXT: blr 2770; 2771; P8LE-LABEL: spltRegValui: 2772; P8LE: # %bb.0: # %entry 2773; P8LE-NEXT: mtfprwz f0, r3 2774; P8LE-NEXT: xxspltw v2, vs0, 1 2775; P8LE-NEXT: blr 2776entry: 2777 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2778 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2779 ret <4 x i32> %splat.splat 2780} 2781 2782define <4 x i32> @spltMemValui(i32* nocapture readonly %ptr) { 2783; P9BE-LABEL: spltMemValui: 2784; P9BE: # %bb.0: # %entry 2785; P9BE-NEXT: lxvwsx v2, 0, r3 2786; P9BE-NEXT: blr 2787; 2788; P9LE-LABEL: spltMemValui: 2789; P9LE: # %bb.0: # %entry 2790; P9LE-NEXT: lxvwsx v2, 0, r3 2791; P9LE-NEXT: blr 2792; 2793; P8BE-LABEL: spltMemValui: 2794; P8BE: # %bb.0: # %entry 2795; P8BE-NEXT: lfiwzx f0, 0, r3 2796; P8BE-NEXT: xxsldwi vs0, f0, f0, 1 2797; P8BE-NEXT: xxspltw v2, vs0, 0 2798; P8BE-NEXT: blr 2799; 2800; P8LE-LABEL: spltMemValui: 2801; P8LE: # %bb.0: # %entry 2802; P8LE-NEXT: lfiwzx f0, 0, r3 2803; P8LE-NEXT: xxspltw v2, vs0, 1 2804; P8LE-NEXT: blr 2805entry: 2806 %0 = load i32, i32* %ptr, align 4 2807 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2808 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2809 ret <4 x i32> %splat.splat 2810} 2811 2812define <4 x i32> @spltCnstConvftoui() { 2813; P9BE-LABEL: spltCnstConvftoui: 2814; P9BE: # %bb.0: # %entry 2815; P9BE-NEXT: vspltisw v2, 4 2816; P9BE-NEXT: blr 2817; 2818; P9LE-LABEL: spltCnstConvftoui: 2819; P9LE: # %bb.0: # %entry 2820; P9LE-NEXT: vspltisw v2, 4 2821; P9LE-NEXT: blr 2822; 2823; P8BE-LABEL: spltCnstConvftoui: 2824; P8BE: # %bb.0: # %entry 2825; P8BE-NEXT: vspltisw v2, 4 2826; P8BE-NEXT: blr 2827; 2828; P8LE-LABEL: spltCnstConvftoui: 2829; P8LE: # %bb.0: # %entry 2830; P8LE-NEXT: vspltisw v2, 4 2831; P8LE-NEXT: blr 2832entry: 2833 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2834} 2835 2836define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2837; P9BE-LABEL: fromRegsConvftoui: 2838; P9BE: # %bb.0: # %entry 2839; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2840; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2841; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2842; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2843; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2844; P9BE-NEXT: xvcvdpuxws v2, vs0 2845; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2846; P9BE-NEXT: xvcvdpuxws v3, vs0 2847; P9BE-NEXT: vmrgew v2, v3, v2 2848; P9BE-NEXT: blr 2849; 2850; P9LE-LABEL: fromRegsConvftoui: 2851; P9LE: # %bb.0: # %entry 2852; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2853; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2854; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2855; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2856; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2857; P9LE-NEXT: xvcvdpuxws v2, vs0 2858; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2859; P9LE-NEXT: xvcvdpuxws v3, vs0 2860; P9LE-NEXT: vmrgew v2, v3, v2 2861; P9LE-NEXT: blr 2862; 2863; P8BE-LABEL: fromRegsConvftoui: 2864; P8BE: # %bb.0: # %entry 2865; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2866; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2867; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2868; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2869; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2870; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2871; P8BE-NEXT: xvcvdpuxws v2, vs0 2872; P8BE-NEXT: xvcvdpuxws v3, vs1 2873; P8BE-NEXT: vmrgew v2, v3, v2 2874; P8BE-NEXT: blr 2875; 2876; P8LE-LABEL: fromRegsConvftoui: 2877; P8LE: # %bb.0: # %entry 2878; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 2879; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 2880; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 2881; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 2882; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2883; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2884; P8LE-NEXT: xvcvdpuxws v2, vs0 2885; P8LE-NEXT: xvcvdpuxws v3, vs1 2886; P8LE-NEXT: vmrgew v2, v3, v2 2887; P8LE-NEXT: blr 2888entry: 2889 %conv = fptoui float %a to i32 2890 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2891 %conv1 = fptoui float %b to i32 2892 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2893 %conv3 = fptoui float %c to i32 2894 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2895 %conv5 = fptoui float %d to i32 2896 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2897 ret <4 x i32> %vecinit6 2898} 2899 2900define <4 x i32> @fromDiffConstsConvftoui() { 2901; P9BE-LABEL: fromDiffConstsConvftoui: 2902; P9BE: # %bb.0: # %entry 2903; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2904; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2905; P9BE-NEXT: lxvx v2, 0, r3 2906; P9BE-NEXT: blr 2907; 2908; P9LE-LABEL: fromDiffConstsConvftoui: 2909; P9LE: # %bb.0: # %entry 2910; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2911; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2912; P9LE-NEXT: lxvx v2, 0, r3 2913; P9LE-NEXT: blr 2914; 2915; P8BE-LABEL: fromDiffConstsConvftoui: 2916; P8BE: # %bb.0: # %entry 2917; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2918; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2919; P8BE-NEXT: lxvw4x v2, 0, r3 2920; P8BE-NEXT: blr 2921; 2922; P8LE-LABEL: fromDiffConstsConvftoui: 2923; P8LE: # %bb.0: # %entry 2924; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2925; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2926; P8LE-NEXT: lvx v2, 0, r3 2927; P8LE-NEXT: blr 2928entry: 2929 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2930} 2931 2932define <4 x i32> @fromDiffMemConsAConvftoui(float* nocapture readonly %ptr) { 2933; P9BE-LABEL: fromDiffMemConsAConvftoui: 2934; P9BE: # %bb.0: # %entry 2935; P9BE-NEXT: lxv vs0, 0(r3) 2936; P9BE-NEXT: xvcvspuxws v2, vs0 2937; P9BE-NEXT: blr 2938; 2939; P9LE-LABEL: fromDiffMemConsAConvftoui: 2940; P9LE: # %bb.0: # %entry 2941; P9LE-NEXT: lxv vs0, 0(r3) 2942; P9LE-NEXT: xvcvspuxws v2, vs0 2943; P9LE-NEXT: blr 2944; 2945; P8BE-LABEL: fromDiffMemConsAConvftoui: 2946; P8BE: # %bb.0: # %entry 2947; P8BE-NEXT: lxvw4x vs0, 0, r3 2948; P8BE-NEXT: xvcvspuxws v2, vs0 2949; P8BE-NEXT: blr 2950; 2951; P8LE-LABEL: fromDiffMemConsAConvftoui: 2952; P8LE: # %bb.0: # %entry 2953; P8LE-NEXT: lxvd2x vs0, 0, r3 2954; P8LE-NEXT: xxswapd v2, vs0 2955; P8LE-NEXT: xvcvspuxws v2, v2 2956; P8LE-NEXT: blr 2957entry: 2958 %0 = bitcast float* %ptr to <4 x float>* 2959 %1 = load <4 x float>, <4 x float>* %0, align 4 2960 %2 = fptoui <4 x float> %1 to <4 x i32> 2961 ret <4 x i32> %2 2962} 2963 2964define <4 x i32> @fromDiffMemConsDConvftoui(float* nocapture readonly %ptr) { 2965; P9BE-LABEL: fromDiffMemConsDConvftoui: 2966; P9BE: # %bb.0: # %entry 2967; P9BE-NEXT: lxv v2, 0(r3) 2968; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2969; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2970; P9BE-NEXT: lxvx v3, 0, r3 2971; P9BE-NEXT: vperm v2, v2, v2, v3 2972; P9BE-NEXT: xvcvspuxws v2, v2 2973; P9BE-NEXT: blr 2974; 2975; P9LE-LABEL: fromDiffMemConsDConvftoui: 2976; P9LE: # %bb.0: # %entry 2977; P9LE-NEXT: lxv v2, 0(r3) 2978; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2979; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2980; P9LE-NEXT: lxvx v3, 0, r3 2981; P9LE-NEXT: vperm v2, v2, v2, v3 2982; P9LE-NEXT: xvcvspuxws v2, v2 2983; P9LE-NEXT: blr 2984; 2985; P8BE-LABEL: fromDiffMemConsDConvftoui: 2986; P8BE: # %bb.0: # %entry 2987; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2988; P8BE-NEXT: lxvw4x v2, 0, r3 2989; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l 2990; P8BE-NEXT: lxvw4x v3, 0, r4 2991; P8BE-NEXT: vperm v2, v2, v2, v3 2992; P8BE-NEXT: xvcvspuxws v2, v2 2993; P8BE-NEXT: blr 2994; 2995; P8LE-LABEL: fromDiffMemConsDConvftoui: 2996; P8LE: # %bb.0: # %entry 2997; P8LE-NEXT: lxvd2x vs0, 0, r3 2998; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2999; P8LE-NEXT: addi r3, r4, .LCPI50_0@toc@l 3000; P8LE-NEXT: lvx v2, 0, r3 3001; P8LE-NEXT: xxswapd v3, vs0 3002; P8LE-NEXT: vperm v2, v3, v3, v2 3003; P8LE-NEXT: xvcvspuxws v2, v2 3004; P8LE-NEXT: blr 3005entry: 3006 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 3007 %0 = load float, float* %arrayidx, align 4 3008 %conv = fptoui float %0 to i32 3009 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3010 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 3011 %1 = load float, float* %arrayidx1, align 4 3012 %conv2 = fptoui float %1 to i32 3013 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3014 %arrayidx4 = getelementptr inbounds float, float* %ptr, i64 1 3015 %2 = load float, float* %arrayidx4, align 4 3016 %conv5 = fptoui float %2 to i32 3017 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3018 %3 = load float, float* %ptr, align 4 3019 %conv8 = fptoui float %3 to i32 3020 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3021 ret <4 x i32> %vecinit9 3022} 3023 3024define <4 x i32> @fromDiffMemVarAConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3025; P9BE-LABEL: fromDiffMemVarAConvftoui: 3026; P9BE: # %bb.0: # %entry 3027; P9BE-NEXT: sldi r4, r4, 2 3028; P9BE-NEXT: lfsux f0, r3, r4 3029; P9BE-NEXT: lfs f1, 12(r3) 3030; P9BE-NEXT: lfs f2, 4(r3) 3031; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3032; P9BE-NEXT: xvcvdpsp v2, vs1 3033; P9BE-NEXT: lfs f1, 8(r3) 3034; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3035; P9BE-NEXT: xvcvdpsp v3, vs0 3036; P9BE-NEXT: vmrgew v2, v3, v2 3037; P9BE-NEXT: xvcvspuxws v2, v2 3038; P9BE-NEXT: blr 3039; 3040; P9LE-LABEL: fromDiffMemVarAConvftoui: 3041; P9LE: # %bb.0: # %entry 3042; P9LE-NEXT: sldi r4, r4, 2 3043; P9LE-NEXT: lfsux f0, r3, r4 3044; P9LE-NEXT: lfs f1, 8(r3) 3045; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3046; P9LE-NEXT: lfs f1, 12(r3) 3047; P9LE-NEXT: xvcvdpsp v2, vs0 3048; P9LE-NEXT: lfs f0, 4(r3) 3049; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3050; P9LE-NEXT: xvcvdpsp v3, vs0 3051; P9LE-NEXT: vmrgew v2, v3, v2 3052; P9LE-NEXT: xvcvspuxws v2, v2 3053; P9LE-NEXT: blr 3054; 3055; P8BE-LABEL: fromDiffMemVarAConvftoui: 3056; P8BE: # %bb.0: # %entry 3057; P8BE-NEXT: sldi r4, r4, 2 3058; P8BE-NEXT: lfsux f0, r3, r4 3059; P8BE-NEXT: lfs f1, 12(r3) 3060; P8BE-NEXT: lfs f2, 4(r3) 3061; P8BE-NEXT: lfs f3, 8(r3) 3062; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3063; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3064; P8BE-NEXT: xvcvdpsp v2, vs1 3065; P8BE-NEXT: xvcvdpsp v3, vs0 3066; P8BE-NEXT: vmrgew v2, v3, v2 3067; P8BE-NEXT: xvcvspuxws v2, v2 3068; P8BE-NEXT: blr 3069; 3070; P8LE-LABEL: fromDiffMemVarAConvftoui: 3071; P8LE: # %bb.0: # %entry 3072; P8LE-NEXT: sldi r4, r4, 2 3073; P8LE-NEXT: lfsux f0, r3, r4 3074; P8LE-NEXT: lfs f1, 8(r3) 3075; P8LE-NEXT: lfs f2, 4(r3) 3076; P8LE-NEXT: lfs f3, 12(r3) 3077; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3078; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3079; P8LE-NEXT: xvcvdpsp v2, vs0 3080; P8LE-NEXT: xvcvdpsp v3, vs1 3081; P8LE-NEXT: vmrgew v2, v3, v2 3082; P8LE-NEXT: xvcvspuxws v2, v2 3083; P8LE-NEXT: blr 3084entry: 3085 %idxprom = sext i32 %elem to i64 3086 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3087 %0 = load float, float* %arrayidx, align 4 3088 %conv = fptoui float %0 to i32 3089 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3090 %add = add nsw i32 %elem, 1 3091 %idxprom1 = sext i32 %add to i64 3092 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3093 %1 = load float, float* %arrayidx2, align 4 3094 %conv3 = fptoui float %1 to i32 3095 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3096 %add5 = add nsw i32 %elem, 2 3097 %idxprom6 = sext i32 %add5 to i64 3098 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3099 %2 = load float, float* %arrayidx7, align 4 3100 %conv8 = fptoui float %2 to i32 3101 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3102 %add10 = add nsw i32 %elem, 3 3103 %idxprom11 = sext i32 %add10 to i64 3104 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3105 %3 = load float, float* %arrayidx12, align 4 3106 %conv13 = fptoui float %3 to i32 3107 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3108 ret <4 x i32> %vecinit14 3109; FIXME: implement finding consecutive loads with pre-inc 3110} 3111 3112define <4 x i32> @fromDiffMemVarDConvftoui(float* nocapture readonly %arr, i32 signext %elem) { 3113; P9BE-LABEL: fromDiffMemVarDConvftoui: 3114; P9BE: # %bb.0: # %entry 3115; P9BE-NEXT: sldi r4, r4, 2 3116; P9BE-NEXT: lfsux f0, r3, r4 3117; P9BE-NEXT: lfs f1, -12(r3) 3118; P9BE-NEXT: lfs f2, -4(r3) 3119; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3120; P9BE-NEXT: xvcvdpsp v2, vs1 3121; P9BE-NEXT: lfs f1, -8(r3) 3122; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3123; P9BE-NEXT: xvcvdpsp v3, vs0 3124; P9BE-NEXT: vmrgew v2, v3, v2 3125; P9BE-NEXT: xvcvspuxws v2, v2 3126; P9BE-NEXT: blr 3127; 3128; P9LE-LABEL: fromDiffMemVarDConvftoui: 3129; P9LE: # %bb.0: # %entry 3130; P9LE-NEXT: sldi r4, r4, 2 3131; P9LE-NEXT: lfsux f0, r3, r4 3132; P9LE-NEXT: lfs f1, -8(r3) 3133; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3134; P9LE-NEXT: lfs f1, -12(r3) 3135; P9LE-NEXT: xvcvdpsp v2, vs0 3136; P9LE-NEXT: lfs f0, -4(r3) 3137; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3138; P9LE-NEXT: xvcvdpsp v3, vs0 3139; P9LE-NEXT: vmrgew v2, v3, v2 3140; P9LE-NEXT: xvcvspuxws v2, v2 3141; P9LE-NEXT: blr 3142; 3143; P8BE-LABEL: fromDiffMemVarDConvftoui: 3144; P8BE: # %bb.0: # %entry 3145; P8BE-NEXT: sldi r4, r4, 2 3146; P8BE-NEXT: lfsux f0, r3, r4 3147; P8BE-NEXT: lfs f1, -12(r3) 3148; P8BE-NEXT: lfs f2, -4(r3) 3149; P8BE-NEXT: lfs f3, -8(r3) 3150; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3151; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3152; P8BE-NEXT: xvcvdpsp v2, vs1 3153; P8BE-NEXT: xvcvdpsp v3, vs0 3154; P8BE-NEXT: vmrgew v2, v3, v2 3155; P8BE-NEXT: xvcvspuxws v2, v2 3156; P8BE-NEXT: blr 3157; 3158; P8LE-LABEL: fromDiffMemVarDConvftoui: 3159; P8LE: # %bb.0: # %entry 3160; P8LE-NEXT: sldi r4, r4, 2 3161; P8LE-NEXT: lfsux f0, r3, r4 3162; P8LE-NEXT: lfs f1, -8(r3) 3163; P8LE-NEXT: lfs f2, -4(r3) 3164; P8LE-NEXT: lfs f3, -12(r3) 3165; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3166; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3167; P8LE-NEXT: xvcvdpsp v2, vs0 3168; P8LE-NEXT: xvcvdpsp v3, vs1 3169; P8LE-NEXT: vmrgew v2, v3, v2 3170; P8LE-NEXT: xvcvspuxws v2, v2 3171; P8LE-NEXT: blr 3172entry: 3173 %idxprom = sext i32 %elem to i64 3174 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 3175 %0 = load float, float* %arrayidx, align 4 3176 %conv = fptoui float %0 to i32 3177 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3178 %sub = add nsw i32 %elem, -1 3179 %idxprom1 = sext i32 %sub to i64 3180 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 3181 %1 = load float, float* %arrayidx2, align 4 3182 %conv3 = fptoui float %1 to i32 3183 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3184 %sub5 = add nsw i32 %elem, -2 3185 %idxprom6 = sext i32 %sub5 to i64 3186 %arrayidx7 = getelementptr inbounds float, float* %arr, i64 %idxprom6 3187 %2 = load float, float* %arrayidx7, align 4 3188 %conv8 = fptoui float %2 to i32 3189 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3190 %sub10 = add nsw i32 %elem, -3 3191 %idxprom11 = sext i32 %sub10 to i64 3192 %arrayidx12 = getelementptr inbounds float, float* %arr, i64 %idxprom11 3193 %3 = load float, float* %arrayidx12, align 4 3194 %conv13 = fptoui float %3 to i32 3195 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3196 ret <4 x i32> %vecinit14 3197; FIXME: implement finding consecutive loads with pre-inc 3198} 3199 3200define <4 x i32> @spltRegValConvftoui(float %val) { 3201; P9BE-LABEL: spltRegValConvftoui: 3202; P9BE: # %bb.0: # %entry 3203; P9BE-NEXT: xscvdpuxws f0, f1 3204; P9BE-NEXT: xxspltw v2, vs0, 1 3205; P9BE-NEXT: blr 3206; 3207; P9LE-LABEL: spltRegValConvftoui: 3208; P9LE: # %bb.0: # %entry 3209; P9LE-NEXT: xscvdpuxws f0, f1 3210; P9LE-NEXT: xxspltw v2, vs0, 1 3211; P9LE-NEXT: blr 3212; 3213; P8BE-LABEL: spltRegValConvftoui: 3214; P8BE: # %bb.0: # %entry 3215; P8BE-NEXT: xscvdpuxws f0, f1 3216; P8BE-NEXT: xxspltw v2, vs0, 1 3217; P8BE-NEXT: blr 3218; 3219; P8LE-LABEL: spltRegValConvftoui: 3220; P8LE: # %bb.0: # %entry 3221; P8LE-NEXT: xscvdpuxws f0, f1 3222; P8LE-NEXT: xxspltw v2, vs0, 1 3223; P8LE-NEXT: blr 3224entry: 3225 %conv = fptoui float %val to i32 3226 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3227 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3228 ret <4 x i32> %splat.splat 3229} 3230 3231define <4 x i32> @spltMemValConvftoui(float* nocapture readonly %ptr) { 3232; P9BE-LABEL: spltMemValConvftoui: 3233; P9BE: # %bb.0: # %entry 3234; P9BE-NEXT: lxvwsx vs0, 0, r3 3235; P9BE-NEXT: xvcvspuxws v2, vs0 3236; P9BE-NEXT: blr 3237; 3238; P9LE-LABEL: spltMemValConvftoui: 3239; P9LE: # %bb.0: # %entry 3240; P9LE-NEXT: lxvwsx vs0, 0, r3 3241; P9LE-NEXT: xvcvspuxws v2, vs0 3242; P9LE-NEXT: blr 3243; 3244; P8BE-LABEL: spltMemValConvftoui: 3245; P8BE: # %bb.0: # %entry 3246; P8BE-NEXT: lfsx f0, 0, r3 3247; P8BE-NEXT: xscvdpuxws f0, f0 3248; P8BE-NEXT: xxspltw v2, vs0, 1 3249; P8BE-NEXT: blr 3250; 3251; P8LE-LABEL: spltMemValConvftoui: 3252; P8LE: # %bb.0: # %entry 3253; P8LE-NEXT: lfsx f0, 0, r3 3254; P8LE-NEXT: xscvdpuxws f0, f0 3255; P8LE-NEXT: xxspltw v2, vs0, 1 3256; P8LE-NEXT: blr 3257entry: 3258 %0 = load float, float* %ptr, align 4 3259 %conv = fptoui float %0 to i32 3260 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3261 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3262 ret <4 x i32> %splat.splat 3263} 3264 3265define <4 x i32> @spltCnstConvdtoui() { 3266; P9BE-LABEL: spltCnstConvdtoui: 3267; P9BE: # %bb.0: # %entry 3268; P9BE-NEXT: vspltisw v2, 4 3269; P9BE-NEXT: blr 3270; 3271; P9LE-LABEL: spltCnstConvdtoui: 3272; P9LE: # %bb.0: # %entry 3273; P9LE-NEXT: vspltisw v2, 4 3274; P9LE-NEXT: blr 3275; 3276; P8BE-LABEL: spltCnstConvdtoui: 3277; P8BE: # %bb.0: # %entry 3278; P8BE-NEXT: vspltisw v2, 4 3279; P8BE-NEXT: blr 3280; 3281; P8LE-LABEL: spltCnstConvdtoui: 3282; P8LE: # %bb.0: # %entry 3283; P8LE-NEXT: vspltisw v2, 4 3284; P8LE-NEXT: blr 3285entry: 3286 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3287} 3288 3289define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3290; P9BE-LABEL: fromRegsConvdtoui: 3291; P9BE: # %bb.0: # %entry 3292; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3293; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3294; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3295; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3296; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3297; P9BE-NEXT: xvcvdpuxws v2, vs0 3298; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3299; P9BE-NEXT: xvcvdpuxws v3, vs0 3300; P9BE-NEXT: vmrgew v2, v3, v2 3301; P9BE-NEXT: blr 3302; 3303; P9LE-LABEL: fromRegsConvdtoui: 3304; P9LE: # %bb.0: # %entry 3305; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3306; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3307; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3308; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3309; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3310; P9LE-NEXT: xvcvdpuxws v2, vs0 3311; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3312; P9LE-NEXT: xvcvdpuxws v3, vs0 3313; P9LE-NEXT: vmrgew v2, v3, v2 3314; P9LE-NEXT: blr 3315; 3316; P8BE-LABEL: fromRegsConvdtoui: 3317; P8BE: # %bb.0: # %entry 3318; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3319; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3320; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3321; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3322; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3323; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3324; P8BE-NEXT: xvcvdpuxws v2, vs0 3325; P8BE-NEXT: xvcvdpuxws v3, vs1 3326; P8BE-NEXT: vmrgew v2, v3, v2 3327; P8BE-NEXT: blr 3328; 3329; P8LE-LABEL: fromRegsConvdtoui: 3330; P8LE: # %bb.0: # %entry 3331; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 3332; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4 3333; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3 3334; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 3335; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3336; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3337; P8LE-NEXT: xvcvdpuxws v2, vs0 3338; P8LE-NEXT: xvcvdpuxws v3, vs1 3339; P8LE-NEXT: vmrgew v2, v3, v2 3340; P8LE-NEXT: blr 3341entry: 3342 %conv = fptoui double %a to i32 3343 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3344 %conv1 = fptoui double %b to i32 3345 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3346 %conv3 = fptoui double %c to i32 3347 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3348 %conv5 = fptoui double %d to i32 3349 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3350 ret <4 x i32> %vecinit6 3351} 3352 3353define <4 x i32> @fromDiffConstsConvdtoui() { 3354; P9BE-LABEL: fromDiffConstsConvdtoui: 3355; P9BE: # %bb.0: # %entry 3356; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3357; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3358; P9BE-NEXT: lxvx v2, 0, r3 3359; P9BE-NEXT: blr 3360; 3361; P9LE-LABEL: fromDiffConstsConvdtoui: 3362; P9LE: # %bb.0: # %entry 3363; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3364; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3365; P9LE-NEXT: lxvx v2, 0, r3 3366; P9LE-NEXT: blr 3367; 3368; P8BE-LABEL: fromDiffConstsConvdtoui: 3369; P8BE: # %bb.0: # %entry 3370; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3371; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3372; P8BE-NEXT: lxvw4x v2, 0, r3 3373; P8BE-NEXT: blr 3374; 3375; P8LE-LABEL: fromDiffConstsConvdtoui: 3376; P8LE: # %bb.0: # %entry 3377; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3378; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3379; P8LE-NEXT: lvx v2, 0, r3 3380; P8LE-NEXT: blr 3381entry: 3382 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3383} 3384 3385define <4 x i32> @fromDiffMemConsAConvdtoui(double* nocapture readonly %ptr) { 3386; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3387; P9BE: # %bb.0: # %entry 3388; P9BE-NEXT: lxv vs0, 0(r3) 3389; P9BE-NEXT: lxv vs1, 16(r3) 3390; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3391; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3392; P9BE-NEXT: xvcvdpuxws v2, vs2 3393; P9BE-NEXT: xvcvdpuxws v3, vs0 3394; P9BE-NEXT: vmrgew v2, v3, v2 3395; P9BE-NEXT: blr 3396; 3397; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3398; P9LE: # %bb.0: # %entry 3399; P9LE-NEXT: lxv vs0, 0(r3) 3400; P9LE-NEXT: lxv vs1, 16(r3) 3401; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3402; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3403; P9LE-NEXT: xvcvdpuxws v2, vs2 3404; P9LE-NEXT: xvcvdpuxws v3, vs0 3405; P9LE-NEXT: vmrgew v2, v3, v2 3406; P9LE-NEXT: blr 3407; 3408; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3409; P8BE: # %bb.0: # %entry 3410; P8BE-NEXT: li r4, 16 3411; P8BE-NEXT: lxvd2x vs0, 0, r3 3412; P8BE-NEXT: lxvd2x vs1, r3, r4 3413; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3414; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3415; P8BE-NEXT: xvcvdpuxws v2, vs2 3416; P8BE-NEXT: xvcvdpuxws v3, vs0 3417; P8BE-NEXT: vmrgew v2, v3, v2 3418; P8BE-NEXT: blr 3419; 3420; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3421; P8LE: # %bb.0: # %entry 3422; P8LE-NEXT: li r4, 16 3423; P8LE-NEXT: lxvd2x vs0, 0, r3 3424; P8LE-NEXT: lxvd2x vs1, r3, r4 3425; P8LE-NEXT: xxswapd vs0, vs0 3426; P8LE-NEXT: xxswapd vs1, vs1 3427; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3428; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3429; P8LE-NEXT: xvcvdpuxws v2, vs2 3430; P8LE-NEXT: xvcvdpuxws v3, vs0 3431; P8LE-NEXT: vmrgew v2, v3, v2 3432; P8LE-NEXT: blr 3433entry: 3434 %0 = bitcast double* %ptr to <2 x double>* 3435 %1 = load <2 x double>, <2 x double>* %0, align 8 3436 %2 = fptoui <2 x double> %1 to <2 x i32> 3437 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 2 3438 %3 = bitcast double* %arrayidx4 to <2 x double>* 3439 %4 = load <2 x double>, <2 x double>* %3, align 8 3440 %5 = fptoui <2 x double> %4 to <2 x i32> 3441 %vecinit9 = shufflevector <2 x i32> %2, <2 x i32> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3442 ret <4 x i32> %vecinit9 3443} 3444 3445define <4 x i32> @fromDiffMemConsDConvdtoui(double* nocapture readonly %ptr) { 3446; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3447; P9BE: # %bb.0: # %entry 3448; P9BE-NEXT: lfd f0, 24(r3) 3449; P9BE-NEXT: lfd f1, 16(r3) 3450; P9BE-NEXT: lfd f2, 8(r3) 3451; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3452; P9BE-NEXT: lfd f3, 0(r3) 3453; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3454; P9BE-NEXT: xvcvdpuxws v2, vs1 3455; P9BE-NEXT: xvcvdpuxws v3, vs0 3456; P9BE-NEXT: vmrgew v2, v3, v2 3457; P9BE-NEXT: blr 3458; 3459; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3460; P9LE: # %bb.0: # %entry 3461; P9LE-NEXT: lfd f0, 24(r3) 3462; P9LE-NEXT: lfd f2, 8(r3) 3463; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3464; P9LE-NEXT: lfd f1, 16(r3) 3465; P9LE-NEXT: lfd f3, 0(r3) 3466; P9LE-NEXT: xvcvdpuxws v2, vs0 3467; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3468; P9LE-NEXT: xvcvdpuxws v3, vs0 3469; P9LE-NEXT: vmrgew v2, v3, v2 3470; P9LE-NEXT: blr 3471; 3472; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3473; P8BE: # %bb.0: # %entry 3474; P8BE-NEXT: lfdx f3, 0, r3 3475; P8BE-NEXT: lfd f0, 24(r3) 3476; P8BE-NEXT: lfd f1, 8(r3) 3477; P8BE-NEXT: lfd f2, 16(r3) 3478; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3479; P8BE-NEXT: xxmrghd vs1, vs2, vs3 3480; P8BE-NEXT: xvcvdpuxws v2, vs0 3481; P8BE-NEXT: xvcvdpuxws v3, vs1 3482; P8BE-NEXT: vmrgew v2, v2, v3 3483; P8BE-NEXT: blr 3484; 3485; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3486; P8LE: # %bb.0: # %entry 3487; P8LE-NEXT: lfdx f3, 0, r3 3488; P8LE-NEXT: lfd f0, 24(r3) 3489; P8LE-NEXT: lfd f1, 8(r3) 3490; P8LE-NEXT: lfd f2, 16(r3) 3491; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3492; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3493; P8LE-NEXT: xvcvdpuxws v2, vs0 3494; P8LE-NEXT: xvcvdpuxws v3, vs1 3495; P8LE-NEXT: vmrgew v2, v3, v2 3496; P8LE-NEXT: blr 3497entry: 3498 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 3499 %0 = load double, double* %arrayidx, align 8 3500 %conv = fptoui double %0 to i32 3501 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3502 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 3503 %1 = load double, double* %arrayidx1, align 8 3504 %conv2 = fptoui double %1 to i32 3505 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3506 %arrayidx4 = getelementptr inbounds double, double* %ptr, i64 1 3507 %2 = load double, double* %arrayidx4, align 8 3508 %conv5 = fptoui double %2 to i32 3509 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3510 %3 = load double, double* %ptr, align 8 3511 %conv8 = fptoui double %3 to i32 3512 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3513 ret <4 x i32> %vecinit9 3514} 3515 3516define <4 x i32> @fromDiffMemVarAConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3517; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3518; P9BE: # %bb.0: # %entry 3519; P9BE-NEXT: sldi r4, r4, 3 3520; P9BE-NEXT: lfdux f0, r3, r4 3521; P9BE-NEXT: lfd f1, 8(r3) 3522; P9BE-NEXT: lfd f2, 16(r3) 3523; P9BE-NEXT: lfd f3, 24(r3) 3524; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3525; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3526; P9BE-NEXT: xvcvdpuxws v2, vs1 3527; P9BE-NEXT: xvcvdpuxws v3, vs0 3528; P9BE-NEXT: vmrgew v2, v3, v2 3529; P9BE-NEXT: blr 3530; 3531; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3532; P9LE: # %bb.0: # %entry 3533; P9LE-NEXT: sldi r4, r4, 3 3534; P9LE-NEXT: lfdux f0, r3, r4 3535; P9LE-NEXT: lfd f2, 16(r3) 3536; P9LE-NEXT: lfd f1, 8(r3) 3537; P9LE-NEXT: lfd f3, 24(r3) 3538; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3539; P9LE-NEXT: xvcvdpuxws v2, vs0 3540; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3541; P9LE-NEXT: xvcvdpuxws v3, vs0 3542; P9LE-NEXT: vmrgew v2, v3, v2 3543; P9LE-NEXT: blr 3544; 3545; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3546; P8BE: # %bb.0: # %entry 3547; P8BE-NEXT: sldi r4, r4, 3 3548; P8BE-NEXT: lfdux f0, r3, r4 3549; P8BE-NEXT: lfd f1, 8(r3) 3550; P8BE-NEXT: lfd f2, 24(r3) 3551; P8BE-NEXT: lfd f3, 16(r3) 3552; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3553; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3554; P8BE-NEXT: xvcvdpuxws v2, vs1 3555; P8BE-NEXT: xvcvdpuxws v3, vs0 3556; P8BE-NEXT: vmrgew v2, v3, v2 3557; P8BE-NEXT: blr 3558; 3559; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3560; P8LE: # %bb.0: # %entry 3561; P8LE-NEXT: sldi r4, r4, 3 3562; P8LE-NEXT: lfdux f0, r3, r4 3563; P8LE-NEXT: lfd f1, 16(r3) 3564; P8LE-NEXT: lfd f2, 8(r3) 3565; P8LE-NEXT: lfd f3, 24(r3) 3566; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3567; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3568; P8LE-NEXT: xvcvdpuxws v2, vs0 3569; P8LE-NEXT: xvcvdpuxws v3, vs1 3570; P8LE-NEXT: vmrgew v2, v3, v2 3571; P8LE-NEXT: blr 3572entry: 3573 %idxprom = sext i32 %elem to i64 3574 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3575 %0 = load double, double* %arrayidx, align 8 3576 %conv = fptoui double %0 to i32 3577 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3578 %add = add nsw i32 %elem, 1 3579 %idxprom1 = sext i32 %add to i64 3580 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3581 %1 = load double, double* %arrayidx2, align 8 3582 %conv3 = fptoui double %1 to i32 3583 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3584 %add5 = add nsw i32 %elem, 2 3585 %idxprom6 = sext i32 %add5 to i64 3586 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3587 %2 = load double, double* %arrayidx7, align 8 3588 %conv8 = fptoui double %2 to i32 3589 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3590 %add10 = add nsw i32 %elem, 3 3591 %idxprom11 = sext i32 %add10 to i64 3592 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3593 %3 = load double, double* %arrayidx12, align 8 3594 %conv13 = fptoui double %3 to i32 3595 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3596 ret <4 x i32> %vecinit14 3597} 3598 3599define <4 x i32> @fromDiffMemVarDConvdtoui(double* nocapture readonly %arr, i32 signext %elem) { 3600; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3601; P9BE: # %bb.0: # %entry 3602; P9BE-NEXT: sldi r4, r4, 3 3603; P9BE-NEXT: lfdux f0, r3, r4 3604; P9BE-NEXT: lfd f1, -8(r3) 3605; P9BE-NEXT: lfd f2, -16(r3) 3606; P9BE-NEXT: lfd f3, -24(r3) 3607; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3608; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3609; P9BE-NEXT: xvcvdpuxws v2, vs1 3610; P9BE-NEXT: xvcvdpuxws v3, vs0 3611; P9BE-NEXT: vmrgew v2, v3, v2 3612; P9BE-NEXT: blr 3613; 3614; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3615; P9LE: # %bb.0: # %entry 3616; P9LE-NEXT: sldi r4, r4, 3 3617; P9LE-NEXT: lfdux f0, r3, r4 3618; P9LE-NEXT: lfd f2, -16(r3) 3619; P9LE-NEXT: lfd f1, -8(r3) 3620; P9LE-NEXT: lfd f3, -24(r3) 3621; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3622; P9LE-NEXT: xvcvdpuxws v2, vs0 3623; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3624; P9LE-NEXT: xvcvdpuxws v3, vs0 3625; P9LE-NEXT: vmrgew v2, v3, v2 3626; P9LE-NEXT: blr 3627; 3628; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3629; P8BE: # %bb.0: # %entry 3630; P8BE-NEXT: sldi r4, r4, 3 3631; P8BE-NEXT: lfdux f0, r3, r4 3632; P8BE-NEXT: lfd f1, -8(r3) 3633; P8BE-NEXT: lfd f2, -24(r3) 3634; P8BE-NEXT: lfd f3, -16(r3) 3635; P8BE-NEXT: xxmrghd vs1, vs1, vs2 3636; P8BE-NEXT: xxmrghd vs0, vs0, vs3 3637; P8BE-NEXT: xvcvdpuxws v2, vs1 3638; P8BE-NEXT: xvcvdpuxws v3, vs0 3639; P8BE-NEXT: vmrgew v2, v3, v2 3640; P8BE-NEXT: blr 3641; 3642; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3643; P8LE: # %bb.0: # %entry 3644; P8LE-NEXT: sldi r4, r4, 3 3645; P8LE-NEXT: lfdux f0, r3, r4 3646; P8LE-NEXT: lfd f1, -16(r3) 3647; P8LE-NEXT: lfd f2, -8(r3) 3648; P8LE-NEXT: lfd f3, -24(r3) 3649; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3650; P8LE-NEXT: xxmrghd vs1, vs3, vs2 3651; P8LE-NEXT: xvcvdpuxws v2, vs0 3652; P8LE-NEXT: xvcvdpuxws v3, vs1 3653; P8LE-NEXT: vmrgew v2, v3, v2 3654; P8LE-NEXT: blr 3655entry: 3656 %idxprom = sext i32 %elem to i64 3657 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 3658 %0 = load double, double* %arrayidx, align 8 3659 %conv = fptoui double %0 to i32 3660 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3661 %sub = add nsw i32 %elem, -1 3662 %idxprom1 = sext i32 %sub to i64 3663 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 3664 %1 = load double, double* %arrayidx2, align 8 3665 %conv3 = fptoui double %1 to i32 3666 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3667 %sub5 = add nsw i32 %elem, -2 3668 %idxprom6 = sext i32 %sub5 to i64 3669 %arrayidx7 = getelementptr inbounds double, double* %arr, i64 %idxprom6 3670 %2 = load double, double* %arrayidx7, align 8 3671 %conv8 = fptoui double %2 to i32 3672 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3673 %sub10 = add nsw i32 %elem, -3 3674 %idxprom11 = sext i32 %sub10 to i64 3675 %arrayidx12 = getelementptr inbounds double, double* %arr, i64 %idxprom11 3676 %3 = load double, double* %arrayidx12, align 8 3677 %conv13 = fptoui double %3 to i32 3678 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3679 ret <4 x i32> %vecinit14 3680} 3681 3682define <4 x i32> @spltRegValConvdtoui(double %val) { 3683; P9BE-LABEL: spltRegValConvdtoui: 3684; P9BE: # %bb.0: # %entry 3685; P9BE-NEXT: xscvdpuxws f0, f1 3686; P9BE-NEXT: xxspltw v2, vs0, 1 3687; P9BE-NEXT: blr 3688; 3689; P9LE-LABEL: spltRegValConvdtoui: 3690; P9LE: # %bb.0: # %entry 3691; P9LE-NEXT: xscvdpuxws f0, f1 3692; P9LE-NEXT: xxspltw v2, vs0, 1 3693; P9LE-NEXT: blr 3694; 3695; P8BE-LABEL: spltRegValConvdtoui: 3696; P8BE: # %bb.0: # %entry 3697; P8BE-NEXT: xscvdpuxws f0, f1 3698; P8BE-NEXT: xxspltw v2, vs0, 1 3699; P8BE-NEXT: blr 3700; 3701; P8LE-LABEL: spltRegValConvdtoui: 3702; P8LE: # %bb.0: # %entry 3703; P8LE-NEXT: xscvdpuxws f0, f1 3704; P8LE-NEXT: xxspltw v2, vs0, 1 3705; P8LE-NEXT: blr 3706entry: 3707 %conv = fptoui double %val to i32 3708 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3709 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3710 ret <4 x i32> %splat.splat 3711} 3712 3713define <4 x i32> @spltMemValConvdtoui(double* nocapture readonly %ptr) { 3714; P9BE-LABEL: spltMemValConvdtoui: 3715; P9BE: # %bb.0: # %entry 3716; P9BE-NEXT: lfd f0, 0(r3) 3717; P9BE-NEXT: xscvdpuxws f0, f0 3718; P9BE-NEXT: xxspltw v2, vs0, 1 3719; P9BE-NEXT: blr 3720; 3721; P9LE-LABEL: spltMemValConvdtoui: 3722; P9LE: # %bb.0: # %entry 3723; P9LE-NEXT: lfd f0, 0(r3) 3724; P9LE-NEXT: xscvdpuxws f0, f0 3725; P9LE-NEXT: xxspltw v2, vs0, 1 3726; P9LE-NEXT: blr 3727; 3728; P8BE-LABEL: spltMemValConvdtoui: 3729; P8BE: # %bb.0: # %entry 3730; P8BE-NEXT: lfdx f0, 0, r3 3731; P8BE-NEXT: xscvdpuxws f0, f0 3732; P8BE-NEXT: xxspltw v2, vs0, 1 3733; P8BE-NEXT: blr 3734; 3735; P8LE-LABEL: spltMemValConvdtoui: 3736; P8LE: # %bb.0: # %entry 3737; P8LE-NEXT: lfdx f0, 0, r3 3738; P8LE-NEXT: xscvdpuxws f0, f0 3739; P8LE-NEXT: xxspltw v2, vs0, 1 3740; P8LE-NEXT: blr 3741entry: 3742 %0 = load double, double* %ptr, align 8 3743 %conv = fptoui double %0 to i32 3744 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3745 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3746 ret <4 x i32> %splat.splat 3747} 3748 3749define <2 x i64> @allZeroll() { 3750; P9BE-LABEL: allZeroll: 3751; P9BE: # %bb.0: # %entry 3752; P9BE-NEXT: xxlxor v2, v2, v2 3753; P9BE-NEXT: blr 3754; 3755; P9LE-LABEL: allZeroll: 3756; P9LE: # %bb.0: # %entry 3757; P9LE-NEXT: xxlxor v2, v2, v2 3758; P9LE-NEXT: blr 3759; 3760; P8BE-LABEL: allZeroll: 3761; P8BE: # %bb.0: # %entry 3762; P8BE-NEXT: xxlxor v2, v2, v2 3763; P8BE-NEXT: blr 3764; 3765; P8LE-LABEL: allZeroll: 3766; P8LE: # %bb.0: # %entry 3767; P8LE-NEXT: xxlxor v2, v2, v2 3768; P8LE-NEXT: blr 3769entry: 3770 ret <2 x i64> zeroinitializer 3771} 3772 3773define <2 x i64> @spltConst1ll() { 3774; P9BE-LABEL: spltConst1ll: 3775; P9BE: # %bb.0: # %entry 3776; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3777; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3778; P9BE-NEXT: lxvx v2, 0, r3 3779; P9BE-NEXT: blr 3780; 3781; P9LE-LABEL: spltConst1ll: 3782; P9LE: # %bb.0: # %entry 3783; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3784; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3785; P9LE-NEXT: lxvx v2, 0, r3 3786; P9LE-NEXT: blr 3787; 3788; P8BE-LABEL: spltConst1ll: 3789; P8BE: # %bb.0: # %entry 3790; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3791; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3792; P8BE-NEXT: lxvd2x v2, 0, r3 3793; P8BE-NEXT: blr 3794; 3795; P8LE-LABEL: spltConst1ll: 3796; P8LE: # %bb.0: # %entry 3797; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3798; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3799; P8LE-NEXT: lxvd2x vs0, 0, r3 3800; P8LE-NEXT: xxswapd v2, vs0 3801; P8LE-NEXT: blr 3802entry: 3803 ret <2 x i64> <i64 1, i64 1> 3804} 3805 3806define <2 x i64> @spltConst16kll() { 3807; P9BE-LABEL: spltConst16kll: 3808; P9BE: # %bb.0: # %entry 3809; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3810; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3811; P9BE-NEXT: lxvx v2, 0, r3 3812; P9BE-NEXT: blr 3813; 3814; P9LE-LABEL: spltConst16kll: 3815; P9LE: # %bb.0: # %entry 3816; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3817; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3818; P9LE-NEXT: lxvx v2, 0, r3 3819; P9LE-NEXT: blr 3820; 3821; P8BE-LABEL: spltConst16kll: 3822; P8BE: # %bb.0: # %entry 3823; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3824; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3825; P8BE-NEXT: lxvd2x v2, 0, r3 3826; P8BE-NEXT: blr 3827; 3828; P8LE-LABEL: spltConst16kll: 3829; P8LE: # %bb.0: # %entry 3830; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3831; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3832; P8LE-NEXT: lxvd2x vs0, 0, r3 3833; P8LE-NEXT: xxswapd v2, vs0 3834; P8LE-NEXT: blr 3835entry: 3836 ret <2 x i64> <i64 32767, i64 32767> 3837} 3838 3839define <2 x i64> @spltConst32kll() { 3840; P9BE-LABEL: spltConst32kll: 3841; P9BE: # %bb.0: # %entry 3842; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3843; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3844; P9BE-NEXT: lxvx v2, 0, r3 3845; P9BE-NEXT: blr 3846; 3847; P9LE-LABEL: spltConst32kll: 3848; P9LE: # %bb.0: # %entry 3849; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3850; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3851; P9LE-NEXT: lxvx v2, 0, r3 3852; P9LE-NEXT: blr 3853; 3854; P8BE-LABEL: spltConst32kll: 3855; P8BE: # %bb.0: # %entry 3856; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3857; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3858; P8BE-NEXT: lxvd2x v2, 0, r3 3859; P8BE-NEXT: blr 3860; 3861; P8LE-LABEL: spltConst32kll: 3862; P8LE: # %bb.0: # %entry 3863; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3864; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3865; P8LE-NEXT: lxvd2x vs0, 0, r3 3866; P8LE-NEXT: xxswapd v2, vs0 3867; P8LE-NEXT: blr 3868entry: 3869 ret <2 x i64> <i64 65535, i64 65535> 3870} 3871 3872define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3873; P9BE-LABEL: fromRegsll: 3874; P9BE: # %bb.0: # %entry 3875; P9BE-NEXT: mtvsrdd v2, r3, r4 3876; P9BE-NEXT: blr 3877; 3878; P9LE-LABEL: fromRegsll: 3879; P9LE: # %bb.0: # %entry 3880; P9LE-NEXT: mtvsrdd v2, r4, r3 3881; P9LE-NEXT: blr 3882; 3883; P8BE-LABEL: fromRegsll: 3884; P8BE: # %bb.0: # %entry 3885; P8BE-NEXT: mtfprd f0, r4 3886; P8BE-NEXT: mtfprd f1, r3 3887; P8BE-NEXT: xxmrghd v2, vs1, vs0 3888; P8BE-NEXT: blr 3889; 3890; P8LE-LABEL: fromRegsll: 3891; P8LE: # %bb.0: # %entry 3892; P8LE-NEXT: mtfprd f0, r3 3893; P8LE-NEXT: mtfprd f1, r4 3894; P8LE-NEXT: xxmrghd v2, vs1, vs0 3895; P8LE-NEXT: blr 3896entry: 3897 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3898 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3899 ret <2 x i64> %vecinit1 3900} 3901 3902define <2 x i64> @fromDiffConstsll() { 3903; P9BE-LABEL: fromDiffConstsll: 3904; P9BE: # %bb.0: # %entry 3905; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3906; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3907; P9BE-NEXT: lxvx v2, 0, r3 3908; P9BE-NEXT: blr 3909; 3910; P9LE-LABEL: fromDiffConstsll: 3911; P9LE: # %bb.0: # %entry 3912; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3913; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3914; P9LE-NEXT: lxvx v2, 0, r3 3915; P9LE-NEXT: blr 3916; 3917; P8BE-LABEL: fromDiffConstsll: 3918; P8BE: # %bb.0: # %entry 3919; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3920; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3921; P8BE-NEXT: lxvd2x v2, 0, r3 3922; P8BE-NEXT: blr 3923; 3924; P8LE-LABEL: fromDiffConstsll: 3925; P8LE: # %bb.0: # %entry 3926; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3927; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3928; P8LE-NEXT: lxvd2x vs0, 0, r3 3929; P8LE-NEXT: xxswapd v2, vs0 3930; P8LE-NEXT: blr 3931entry: 3932 ret <2 x i64> <i64 242, i64 -113> 3933} 3934 3935define <2 x i64> @fromDiffMemConsAll(i64* nocapture readonly %arr) { 3936; P9BE-LABEL: fromDiffMemConsAll: 3937; P9BE: # %bb.0: # %entry 3938; P9BE-NEXT: lxv v2, 0(r3) 3939; P9BE-NEXT: blr 3940; 3941; P9LE-LABEL: fromDiffMemConsAll: 3942; P9LE: # %bb.0: # %entry 3943; P9LE-NEXT: lxv v2, 0(r3) 3944; P9LE-NEXT: blr 3945; 3946; P8BE-LABEL: fromDiffMemConsAll: 3947; P8BE: # %bb.0: # %entry 3948; P8BE-NEXT: lxvd2x v2, 0, r3 3949; P8BE-NEXT: blr 3950; 3951; P8LE-LABEL: fromDiffMemConsAll: 3952; P8LE: # %bb.0: # %entry 3953; P8LE-NEXT: lxvd2x vs0, 0, r3 3954; P8LE-NEXT: xxswapd v2, vs0 3955; P8LE-NEXT: blr 3956entry: 3957 %0 = load i64, i64* %arr, align 8 3958 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3959 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 3960 %1 = load i64, i64* %arrayidx1, align 8 3961 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3962 ret <2 x i64> %vecinit2 3963} 3964 3965define <2 x i64> @fromDiffMemConsDll(i64* nocapture readonly %arr) { 3966; P9BE-LABEL: fromDiffMemConsDll: 3967; P9BE: # %bb.0: # %entry 3968; P9BE-NEXT: lxv v2, 16(r3) 3969; P9BE-NEXT: xxswapd v2, v2 3970; P9BE-NEXT: blr 3971; 3972; P9LE-LABEL: fromDiffMemConsDll: 3973; P9LE: # %bb.0: # %entry 3974; P9LE-NEXT: addi r3, r3, 16 3975; P9LE-NEXT: lxvd2x v2, 0, r3 3976; P9LE-NEXT: blr 3977; 3978; P8BE-LABEL: fromDiffMemConsDll: 3979; P8BE: # %bb.0: # %entry 3980; P8BE-NEXT: addi r3, r3, 16 3981; P8BE-NEXT: lxvd2x v2, 0, r3 3982; P8BE-NEXT: xxswapd v2, v2 3983; P8BE-NEXT: blr 3984; 3985; P8LE-LABEL: fromDiffMemConsDll: 3986; P8LE: # %bb.0: # %entry 3987; P8LE-NEXT: addi r3, r3, 16 3988; P8LE-NEXT: lxvd2x v2, 0, r3 3989; P8LE-NEXT: blr 3990entry: 3991 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 3992 %0 = load i64, i64* %arrayidx, align 8 3993 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3994 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 3995 %1 = load i64, i64* %arrayidx1, align 8 3996 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3997 ret <2 x i64> %vecinit2 3998} 3999 4000define <2 x i64> @fromDiffMemVarAll(i64* nocapture readonly %arr, i32 signext %elem) { 4001; P9BE-LABEL: fromDiffMemVarAll: 4002; P9BE: # %bb.0: # %entry 4003; P9BE-NEXT: sldi r4, r4, 3 4004; P9BE-NEXT: lxvx v2, r3, r4 4005; P9BE-NEXT: blr 4006; 4007; P9LE-LABEL: fromDiffMemVarAll: 4008; P9LE: # %bb.0: # %entry 4009; P9LE-NEXT: sldi r4, r4, 3 4010; P9LE-NEXT: lxvx v2, r3, r4 4011; P9LE-NEXT: blr 4012; 4013; P8BE-LABEL: fromDiffMemVarAll: 4014; P8BE: # %bb.0: # %entry 4015; P8BE-NEXT: sldi r4, r4, 3 4016; P8BE-NEXT: lxvd2x v2, r3, r4 4017; P8BE-NEXT: blr 4018; 4019; P8LE-LABEL: fromDiffMemVarAll: 4020; P8LE: # %bb.0: # %entry 4021; P8LE-NEXT: sldi r4, r4, 3 4022; P8LE-NEXT: lxvd2x vs0, r3, r4 4023; P8LE-NEXT: xxswapd v2, vs0 4024; P8LE-NEXT: blr 4025entry: 4026 %idxprom = sext i32 %elem to i64 4027 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4028 %0 = load i64, i64* %arrayidx, align 8 4029 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4030 %add = add nsw i32 %elem, 1 4031 %idxprom1 = sext i32 %add to i64 4032 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4033 %1 = load i64, i64* %arrayidx2, align 8 4034 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4035 ret <2 x i64> %vecinit3 4036} 4037 4038define <2 x i64> @fromDiffMemVarDll(i64* nocapture readonly %arr, i32 signext %elem) { 4039; P9BE-LABEL: fromDiffMemVarDll: 4040; P9BE: # %bb.0: # %entry 4041; P9BE-NEXT: sldi r4, r4, 3 4042; P9BE-NEXT: add r3, r3, r4 4043; P9BE-NEXT: li r4, -8 4044; P9BE-NEXT: lxvx v2, r3, r4 4045; P9BE-NEXT: xxswapd v2, v2 4046; P9BE-NEXT: blr 4047; 4048; P9LE-LABEL: fromDiffMemVarDll: 4049; P9LE: # %bb.0: # %entry 4050; P9LE-NEXT: sldi r4, r4, 3 4051; P9LE-NEXT: add r3, r3, r4 4052; P9LE-NEXT: addi r3, r3, -8 4053; P9LE-NEXT: lxvd2x v2, 0, r3 4054; P9LE-NEXT: blr 4055; 4056; P8BE-LABEL: fromDiffMemVarDll: 4057; P8BE: # %bb.0: # %entry 4058; P8BE-NEXT: sldi r4, r4, 3 4059; P8BE-NEXT: add r3, r3, r4 4060; P8BE-NEXT: addi r3, r3, -8 4061; P8BE-NEXT: lxvd2x v2, 0, r3 4062; P8BE-NEXT: xxswapd v2, v2 4063; P8BE-NEXT: blr 4064; 4065; P8LE-LABEL: fromDiffMemVarDll: 4066; P8LE: # %bb.0: # %entry 4067; P8LE-NEXT: sldi r4, r4, 3 4068; P8LE-NEXT: add r3, r3, r4 4069; P8LE-NEXT: addi r3, r3, -8 4070; P8LE-NEXT: lxvd2x v2, 0, r3 4071; P8LE-NEXT: blr 4072entry: 4073 %idxprom = sext i32 %elem to i64 4074 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4075 %0 = load i64, i64* %arrayidx, align 8 4076 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4077 %sub = add nsw i32 %elem, -1 4078 %idxprom1 = sext i32 %sub to i64 4079 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 4080 %1 = load i64, i64* %arrayidx2, align 8 4081 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4082 ret <2 x i64> %vecinit3 4083} 4084 4085define <2 x i64> @fromRandMemConsll(i64* nocapture readonly %arr) { 4086; P9BE-LABEL: fromRandMemConsll: 4087; P9BE: # %bb.0: # %entry 4088; P9BE-NEXT: ld r4, 32(r3) 4089; P9BE-NEXT: ld r3, 144(r3) 4090; P9BE-NEXT: mtvsrdd v2, r4, r3 4091; P9BE-NEXT: blr 4092; 4093; P9LE-LABEL: fromRandMemConsll: 4094; P9LE: # %bb.0: # %entry 4095; P9LE-NEXT: ld r4, 32(r3) 4096; P9LE-NEXT: ld r3, 144(r3) 4097; P9LE-NEXT: mtvsrdd v2, r3, r4 4098; P9LE-NEXT: blr 4099; 4100; P8BE-LABEL: fromRandMemConsll: 4101; P8BE: # %bb.0: # %entry 4102; P8BE-NEXT: ld r4, 144(r3) 4103; P8BE-NEXT: ld r3, 32(r3) 4104; P8BE-NEXT: mtfprd f0, r4 4105; P8BE-NEXT: mtfprd f1, r3 4106; P8BE-NEXT: xxmrghd v2, vs1, vs0 4107; P8BE-NEXT: blr 4108; 4109; P8LE-LABEL: fromRandMemConsll: 4110; P8LE: # %bb.0: # %entry 4111; P8LE-NEXT: ld r4, 32(r3) 4112; P8LE-NEXT: ld r3, 144(r3) 4113; P8LE-NEXT: mtfprd f0, r4 4114; P8LE-NEXT: mtfprd f1, r3 4115; P8LE-NEXT: xxmrghd v2, vs1, vs0 4116; P8LE-NEXT: blr 4117entry: 4118 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 4119 %0 = load i64, i64* %arrayidx, align 8 4120 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4121 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 4122 %1 = load i64, i64* %arrayidx1, align 8 4123 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4124 ret <2 x i64> %vecinit2 4125} 4126 4127define <2 x i64> @fromRandMemVarll(i64* nocapture readonly %arr, i32 signext %elem) { 4128; P9BE-LABEL: fromRandMemVarll: 4129; P9BE: # %bb.0: # %entry 4130; P9BE-NEXT: sldi r4, r4, 3 4131; P9BE-NEXT: add r3, r3, r4 4132; P9BE-NEXT: ld r4, 32(r3) 4133; P9BE-NEXT: ld r3, 8(r3) 4134; P9BE-NEXT: mtvsrdd v2, r4, r3 4135; P9BE-NEXT: blr 4136; 4137; P9LE-LABEL: fromRandMemVarll: 4138; P9LE: # %bb.0: # %entry 4139; P9LE-NEXT: sldi r4, r4, 3 4140; P9LE-NEXT: add r3, r3, r4 4141; P9LE-NEXT: ld r4, 32(r3) 4142; P9LE-NEXT: ld r3, 8(r3) 4143; P9LE-NEXT: mtvsrdd v2, r3, r4 4144; P9LE-NEXT: blr 4145; 4146; P8BE-LABEL: fromRandMemVarll: 4147; P8BE: # %bb.0: # %entry 4148; P8BE-NEXT: sldi r4, r4, 3 4149; P8BE-NEXT: add r3, r3, r4 4150; P8BE-NEXT: ld r4, 8(r3) 4151; P8BE-NEXT: ld r3, 32(r3) 4152; P8BE-NEXT: mtfprd f0, r4 4153; P8BE-NEXT: mtfprd f1, r3 4154; P8BE-NEXT: xxmrghd v2, vs1, vs0 4155; P8BE-NEXT: blr 4156; 4157; P8LE-LABEL: fromRandMemVarll: 4158; P8LE: # %bb.0: # %entry 4159; P8LE-NEXT: sldi r4, r4, 3 4160; P8LE-NEXT: add r3, r3, r4 4161; P8LE-NEXT: ld r4, 32(r3) 4162; P8LE-NEXT: ld r3, 8(r3) 4163; P8LE-NEXT: mtfprd f0, r4 4164; P8LE-NEXT: mtfprd f1, r3 4165; P8LE-NEXT: xxmrghd v2, vs1, vs0 4166; P8LE-NEXT: blr 4167entry: 4168 %add = add nsw i32 %elem, 4 4169 %idxprom = sext i32 %add to i64 4170 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 4171 %0 = load i64, i64* %arrayidx, align 8 4172 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4173 %add1 = add nsw i32 %elem, 1 4174 %idxprom2 = sext i32 %add1 to i64 4175 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 4176 %1 = load i64, i64* %arrayidx3, align 8 4177 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4178 ret <2 x i64> %vecinit4 4179} 4180 4181define <2 x i64> @spltRegValll(i64 %val) { 4182; P9BE-LABEL: spltRegValll: 4183; P9BE: # %bb.0: # %entry 4184; P9BE-NEXT: mtvsrdd v2, r3, r3 4185; P9BE-NEXT: blr 4186; 4187; P9LE-LABEL: spltRegValll: 4188; P9LE: # %bb.0: # %entry 4189; P9LE-NEXT: mtvsrdd v2, r3, r3 4190; P9LE-NEXT: blr 4191; 4192; P8BE-LABEL: spltRegValll: 4193; P8BE: # %bb.0: # %entry 4194; P8BE-NEXT: mtfprd f0, r3 4195; P8BE-NEXT: xxspltd v2, vs0, 0 4196; P8BE-NEXT: blr 4197; 4198; P8LE-LABEL: spltRegValll: 4199; P8LE: # %bb.0: # %entry 4200; P8LE-NEXT: mtfprd f0, r3 4201; P8LE-NEXT: xxspltd v2, vs0, 0 4202; P8LE-NEXT: blr 4203entry: 4204 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4205 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4206 ret <2 x i64> %splat.splat 4207} 4208 4209define <2 x i64> @spltMemValll(i64* nocapture readonly %ptr) { 4210; P9BE-LABEL: spltMemValll: 4211; P9BE: # %bb.0: # %entry 4212; P9BE-NEXT: lxvdsx v2, 0, r3 4213; P9BE-NEXT: blr 4214; 4215; P9LE-LABEL: spltMemValll: 4216; P9LE: # %bb.0: # %entry 4217; P9LE-NEXT: lxvdsx v2, 0, r3 4218; P9LE-NEXT: blr 4219; 4220; P8BE-LABEL: spltMemValll: 4221; P8BE: # %bb.0: # %entry 4222; P8BE-NEXT: lxvdsx v2, 0, r3 4223; P8BE-NEXT: blr 4224; 4225; P8LE-LABEL: spltMemValll: 4226; P8LE: # %bb.0: # %entry 4227; P8LE-NEXT: lxvdsx v2, 0, r3 4228; P8LE-NEXT: blr 4229entry: 4230 %0 = load i64, i64* %ptr, align 8 4231 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4232 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4233 ret <2 x i64> %splat.splat 4234} 4235 4236define <2 x i64> @spltCnstConvftoll() { 4237; P9BE-LABEL: spltCnstConvftoll: 4238; P9BE: # %bb.0: # %entry 4239; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4240; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4241; P9BE-NEXT: lxvx v2, 0, r3 4242; P9BE-NEXT: blr 4243; 4244; P9LE-LABEL: spltCnstConvftoll: 4245; P9LE: # %bb.0: # %entry 4246; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4247; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4248; P9LE-NEXT: lxvx v2, 0, r3 4249; P9LE-NEXT: blr 4250; 4251; P8BE-LABEL: spltCnstConvftoll: 4252; P8BE: # %bb.0: # %entry 4253; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4254; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4255; P8BE-NEXT: lxvd2x v2, 0, r3 4256; P8BE-NEXT: blr 4257; 4258; P8LE-LABEL: spltCnstConvftoll: 4259; P8LE: # %bb.0: # %entry 4260; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4261; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4262; P8LE-NEXT: lxvd2x vs0, 0, r3 4263; P8LE-NEXT: xxswapd v2, vs0 4264; P8LE-NEXT: blr 4265entry: 4266 ret <2 x i64> <i64 4, i64 4> 4267} 4268 4269define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4270; P9BE-LABEL: fromRegsConvftoll: 4271; P9BE: # %bb.0: # %entry 4272; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4273; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4274; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4275; P9BE-NEXT: xvcvdpsxds v2, vs0 4276; P9BE-NEXT: blr 4277; 4278; P9LE-LABEL: fromRegsConvftoll: 4279; P9LE: # %bb.0: # %entry 4280; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4281; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4282; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4283; P9LE-NEXT: xvcvdpsxds v2, vs0 4284; P9LE-NEXT: blr 4285; 4286; P8BE-LABEL: fromRegsConvftoll: 4287; P8BE: # %bb.0: # %entry 4288; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4289; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4290; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4291; P8BE-NEXT: xvcvdpsxds v2, vs0 4292; P8BE-NEXT: blr 4293; 4294; P8LE-LABEL: fromRegsConvftoll: 4295; P8LE: # %bb.0: # %entry 4296; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4297; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4298; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4299; P8LE-NEXT: xvcvdpsxds v2, vs0 4300; P8LE-NEXT: blr 4301entry: 4302 %conv = fptosi float %a to i64 4303 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4304 %conv1 = fptosi float %b to i64 4305 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4306 ret <2 x i64> %vecinit2 4307} 4308 4309define <2 x i64> @fromDiffConstsConvftoll() { 4310; P9BE-LABEL: fromDiffConstsConvftoll: 4311; P9BE: # %bb.0: # %entry 4312; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4313; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4314; P9BE-NEXT: lxvx v2, 0, r3 4315; P9BE-NEXT: blr 4316; 4317; P9LE-LABEL: fromDiffConstsConvftoll: 4318; P9LE: # %bb.0: # %entry 4319; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4320; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4321; P9LE-NEXT: lxvx v2, 0, r3 4322; P9LE-NEXT: blr 4323; 4324; P8BE-LABEL: fromDiffConstsConvftoll: 4325; P8BE: # %bb.0: # %entry 4326; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4327; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4328; P8BE-NEXT: lxvd2x v2, 0, r3 4329; P8BE-NEXT: blr 4330; 4331; P8LE-LABEL: fromDiffConstsConvftoll: 4332; P8LE: # %bb.0: # %entry 4333; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4334; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4335; P8LE-NEXT: lxvd2x vs0, 0, r3 4336; P8LE-NEXT: xxswapd v2, vs0 4337; P8LE-NEXT: blr 4338entry: 4339 ret <2 x i64> <i64 24, i64 234> 4340} 4341 4342define <2 x i64> @fromDiffMemConsAConvftoll(float* nocapture readonly %ptr) { 4343; P9BE-LABEL: fromDiffMemConsAConvftoll: 4344; P9BE: # %bb.0: # %entry 4345; P9BE-NEXT: lfs f0, 0(r3) 4346; P9BE-NEXT: lfs f1, 4(r3) 4347; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4348; P9BE-NEXT: xvcvdpsxds v2, vs0 4349; P9BE-NEXT: blr 4350; 4351; P9LE-LABEL: fromDiffMemConsAConvftoll: 4352; P9LE: # %bb.0: # %entry 4353; P9LE-NEXT: lfs f0, 0(r3) 4354; P9LE-NEXT: lfs f1, 4(r3) 4355; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4356; P9LE-NEXT: xvcvdpsxds v2, vs0 4357; P9LE-NEXT: blr 4358; 4359; P8BE-LABEL: fromDiffMemConsAConvftoll: 4360; P8BE: # %bb.0: # %entry 4361; P8BE-NEXT: lfsx f0, 0, r3 4362; P8BE-NEXT: lfs f1, 4(r3) 4363; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4364; P8BE-NEXT: xvcvdpsxds v2, vs0 4365; P8BE-NEXT: blr 4366; 4367; P8LE-LABEL: fromDiffMemConsAConvftoll: 4368; P8LE: # %bb.0: # %entry 4369; P8LE-NEXT: lfsx f0, 0, r3 4370; P8LE-NEXT: lfs f1, 4(r3) 4371; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4372; P8LE-NEXT: xvcvdpsxds v2, vs0 4373; P8LE-NEXT: blr 4374entry: 4375 %0 = load float, float* %ptr, align 4 4376 %conv = fptosi float %0 to i64 4377 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4378 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 4379 %1 = load float, float* %arrayidx1, align 4 4380 %conv2 = fptosi float %1 to i64 4381 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4382 ret <2 x i64> %vecinit3 4383} 4384 4385define <2 x i64> @fromDiffMemConsDConvftoll(float* nocapture readonly %ptr) { 4386; P9BE-LABEL: fromDiffMemConsDConvftoll: 4387; P9BE: # %bb.0: # %entry 4388; P9BE-NEXT: lfs f0, 12(r3) 4389; P9BE-NEXT: lfs f1, 8(r3) 4390; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4391; P9BE-NEXT: xvcvdpsxds v2, vs0 4392; P9BE-NEXT: blr 4393; 4394; P9LE-LABEL: fromDiffMemConsDConvftoll: 4395; P9LE: # %bb.0: # %entry 4396; P9LE-NEXT: lfs f0, 12(r3) 4397; P9LE-NEXT: lfs f1, 8(r3) 4398; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4399; P9LE-NEXT: xvcvdpsxds v2, vs0 4400; P9LE-NEXT: blr 4401; 4402; P8BE-LABEL: fromDiffMemConsDConvftoll: 4403; P8BE: # %bb.0: # %entry 4404; P8BE-NEXT: lfs f0, 12(r3) 4405; P8BE-NEXT: lfs f1, 8(r3) 4406; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4407; P8BE-NEXT: xvcvdpsxds v2, vs0 4408; P8BE-NEXT: blr 4409; 4410; P8LE-LABEL: fromDiffMemConsDConvftoll: 4411; P8LE: # %bb.0: # %entry 4412; P8LE-NEXT: lfs f0, 12(r3) 4413; P8LE-NEXT: lfs f1, 8(r3) 4414; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4415; P8LE-NEXT: xvcvdpsxds v2, vs0 4416; P8LE-NEXT: blr 4417entry: 4418 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 4419 %0 = load float, float* %arrayidx, align 4 4420 %conv = fptosi float %0 to i64 4421 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4422 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 4423 %1 = load float, float* %arrayidx1, align 4 4424 %conv2 = fptosi float %1 to i64 4425 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4426 ret <2 x i64> %vecinit3 4427} 4428 4429define <2 x i64> @fromDiffMemVarAConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4430; P9BE-LABEL: fromDiffMemVarAConvftoll: 4431; P9BE: # %bb.0: # %entry 4432; P9BE-NEXT: sldi r4, r4, 2 4433; P9BE-NEXT: lfsux f0, r3, r4 4434; P9BE-NEXT: lfs f1, 4(r3) 4435; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4436; P9BE-NEXT: xvcvdpsxds v2, vs0 4437; P9BE-NEXT: blr 4438; 4439; P9LE-LABEL: fromDiffMemVarAConvftoll: 4440; P9LE: # %bb.0: # %entry 4441; P9LE-NEXT: sldi r4, r4, 2 4442; P9LE-NEXT: lfsux f0, r3, r4 4443; P9LE-NEXT: lfs f1, 4(r3) 4444; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4445; P9LE-NEXT: xvcvdpsxds v2, vs0 4446; P9LE-NEXT: blr 4447; 4448; P8BE-LABEL: fromDiffMemVarAConvftoll: 4449; P8BE: # %bb.0: # %entry 4450; P8BE-NEXT: sldi r4, r4, 2 4451; P8BE-NEXT: lfsux f0, r3, r4 4452; P8BE-NEXT: lfs f1, 4(r3) 4453; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4454; P8BE-NEXT: xvcvdpsxds v2, vs0 4455; P8BE-NEXT: blr 4456; 4457; P8LE-LABEL: fromDiffMemVarAConvftoll: 4458; P8LE: # %bb.0: # %entry 4459; P8LE-NEXT: sldi r4, r4, 2 4460; P8LE-NEXT: lfsux f0, r3, r4 4461; P8LE-NEXT: lfs f1, 4(r3) 4462; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4463; P8LE-NEXT: xvcvdpsxds v2, vs0 4464; P8LE-NEXT: blr 4465entry: 4466 %idxprom = sext i32 %elem to i64 4467 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4468 %0 = load float, float* %arrayidx, align 4 4469 %conv = fptosi float %0 to i64 4470 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4471 %add = add nsw i32 %elem, 1 4472 %idxprom1 = sext i32 %add to i64 4473 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4474 %1 = load float, float* %arrayidx2, align 4 4475 %conv3 = fptosi float %1 to i64 4476 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4477 ret <2 x i64> %vecinit4 4478} 4479 4480define <2 x i64> @fromDiffMemVarDConvftoll(float* nocapture readonly %arr, i32 signext %elem) { 4481; P9BE-LABEL: fromDiffMemVarDConvftoll: 4482; P9BE: # %bb.0: # %entry 4483; P9BE-NEXT: sldi r4, r4, 2 4484; P9BE-NEXT: lfsux f0, r3, r4 4485; P9BE-NEXT: lfs f1, -4(r3) 4486; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4487; P9BE-NEXT: xvcvdpsxds v2, vs0 4488; P9BE-NEXT: blr 4489; 4490; P9LE-LABEL: fromDiffMemVarDConvftoll: 4491; P9LE: # %bb.0: # %entry 4492; P9LE-NEXT: sldi r4, r4, 2 4493; P9LE-NEXT: lfsux f0, r3, r4 4494; P9LE-NEXT: lfs f1, -4(r3) 4495; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4496; P9LE-NEXT: xvcvdpsxds v2, vs0 4497; P9LE-NEXT: blr 4498; 4499; P8BE-LABEL: fromDiffMemVarDConvftoll: 4500; P8BE: # %bb.0: # %entry 4501; P8BE-NEXT: sldi r4, r4, 2 4502; P8BE-NEXT: lfsux f0, r3, r4 4503; P8BE-NEXT: lfs f1, -4(r3) 4504; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4505; P8BE-NEXT: xvcvdpsxds v2, vs0 4506; P8BE-NEXT: blr 4507; 4508; P8LE-LABEL: fromDiffMemVarDConvftoll: 4509; P8LE: # %bb.0: # %entry 4510; P8LE-NEXT: sldi r4, r4, 2 4511; P8LE-NEXT: lfsux f0, r3, r4 4512; P8LE-NEXT: lfs f1, -4(r3) 4513; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4514; P8LE-NEXT: xvcvdpsxds v2, vs0 4515; P8LE-NEXT: blr 4516entry: 4517 %idxprom = sext i32 %elem to i64 4518 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 4519 %0 = load float, float* %arrayidx, align 4 4520 %conv = fptosi float %0 to i64 4521 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4522 %sub = add nsw i32 %elem, -1 4523 %idxprom1 = sext i32 %sub to i64 4524 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 4525 %1 = load float, float* %arrayidx2, align 4 4526 %conv3 = fptosi float %1 to i64 4527 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4528 ret <2 x i64> %vecinit4 4529} 4530 4531define <2 x i64> @spltRegValConvftoll(float %val) { 4532; P9BE-LABEL: spltRegValConvftoll: 4533; P9BE: # %bb.0: # %entry 4534; P9BE-NEXT: xscvdpsxds f0, f1 4535; P9BE-NEXT: xxspltd v2, f0, 0 4536; P9BE-NEXT: blr 4537; 4538; P9LE-LABEL: spltRegValConvftoll: 4539; P9LE: # %bb.0: # %entry 4540; P9LE-NEXT: xscvdpsxds f0, f1 4541; P9LE-NEXT: xxspltd v2, f0, 0 4542; P9LE-NEXT: blr 4543; 4544; P8BE-LABEL: spltRegValConvftoll: 4545; P8BE: # %bb.0: # %entry 4546; P8BE-NEXT: xscvdpsxds f0, f1 4547; P8BE-NEXT: xxspltd v2, f0, 0 4548; P8BE-NEXT: blr 4549; 4550; P8LE-LABEL: spltRegValConvftoll: 4551; P8LE: # %bb.0: # %entry 4552; P8LE-NEXT: xscvdpsxds f0, f1 4553; P8LE-NEXT: xxspltd v2, f0, 0 4554; P8LE-NEXT: blr 4555entry: 4556 %conv = fptosi float %val to i64 4557 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4558 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4559 ret <2 x i64> %splat.splat 4560} 4561 4562define <2 x i64> @spltMemValConvftoll(float* nocapture readonly %ptr) { 4563; P9BE-LABEL: spltMemValConvftoll: 4564; P9BE: # %bb.0: # %entry 4565; P9BE-NEXT: lfs f0, 0(r3) 4566; P9BE-NEXT: xscvdpsxds f0, f0 4567; P9BE-NEXT: xxspltd v2, f0, 0 4568; P9BE-NEXT: blr 4569; 4570; P9LE-LABEL: spltMemValConvftoll: 4571; P9LE: # %bb.0: # %entry 4572; P9LE-NEXT: lfs f0, 0(r3) 4573; P9LE-NEXT: xscvdpsxds f0, f0 4574; P9LE-NEXT: xxspltd v2, vs0, 0 4575; P9LE-NEXT: blr 4576; 4577; P8BE-LABEL: spltMemValConvftoll: 4578; P8BE: # %bb.0: # %entry 4579; P8BE-NEXT: lfsx f0, 0, r3 4580; P8BE-NEXT: xscvdpsxds f0, f0 4581; P8BE-NEXT: xxspltd v2, f0, 0 4582; P8BE-NEXT: blr 4583; 4584; P8LE-LABEL: spltMemValConvftoll: 4585; P8LE: # %bb.0: # %entry 4586; P8LE-NEXT: lfsx f0, 0, r3 4587; P8LE-NEXT: xscvdpsxds f0, f0 4588; P8LE-NEXT: xxspltd v2, vs0, 0 4589; P8LE-NEXT: blr 4590entry: 4591 %0 = load float, float* %ptr, align 4 4592 %conv = fptosi float %0 to i64 4593 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4594 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4595 ret <2 x i64> %splat.splat 4596} 4597 4598define <2 x i64> @spltCnstConvdtoll() { 4599; P9BE-LABEL: spltCnstConvdtoll: 4600; P9BE: # %bb.0: # %entry 4601; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4602; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4603; P9BE-NEXT: lxvx v2, 0, r3 4604; P9BE-NEXT: blr 4605; 4606; P9LE-LABEL: spltCnstConvdtoll: 4607; P9LE: # %bb.0: # %entry 4608; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4609; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4610; P9LE-NEXT: lxvx v2, 0, r3 4611; P9LE-NEXT: blr 4612; 4613; P8BE-LABEL: spltCnstConvdtoll: 4614; P8BE: # %bb.0: # %entry 4615; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4616; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4617; P8BE-NEXT: lxvd2x v2, 0, r3 4618; P8BE-NEXT: blr 4619; 4620; P8LE-LABEL: spltCnstConvdtoll: 4621; P8LE: # %bb.0: # %entry 4622; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4623; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4624; P8LE-NEXT: lxvd2x vs0, 0, r3 4625; P8LE-NEXT: xxswapd v2, vs0 4626; P8LE-NEXT: blr 4627entry: 4628 ret <2 x i64> <i64 4, i64 4> 4629} 4630 4631define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4632; P9BE-LABEL: fromRegsConvdtoll: 4633; P9BE: # %bb.0: # %entry 4634; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4635; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4636; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4637; P9BE-NEXT: xvcvdpsxds v2, vs0 4638; P9BE-NEXT: blr 4639; 4640; P9LE-LABEL: fromRegsConvdtoll: 4641; P9LE: # %bb.0: # %entry 4642; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4643; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4644; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4645; P9LE-NEXT: xvcvdpsxds v2, vs0 4646; P9LE-NEXT: blr 4647; 4648; P8BE-LABEL: fromRegsConvdtoll: 4649; P8BE: # %bb.0: # %entry 4650; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4651; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4652; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4653; P8BE-NEXT: xvcvdpsxds v2, vs0 4654; P8BE-NEXT: blr 4655; 4656; P8LE-LABEL: fromRegsConvdtoll: 4657; P8LE: # %bb.0: # %entry 4658; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 4659; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 4660; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4661; P8LE-NEXT: xvcvdpsxds v2, vs0 4662; P8LE-NEXT: blr 4663entry: 4664 %conv = fptosi double %a to i64 4665 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4666 %conv1 = fptosi double %b to i64 4667 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4668 ret <2 x i64> %vecinit2 4669} 4670 4671define <2 x i64> @fromDiffConstsConvdtoll() { 4672; P9BE-LABEL: fromDiffConstsConvdtoll: 4673; P9BE: # %bb.0: # %entry 4674; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4675; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4676; P9BE-NEXT: lxvx v2, 0, r3 4677; P9BE-NEXT: blr 4678; 4679; P9LE-LABEL: fromDiffConstsConvdtoll: 4680; P9LE: # %bb.0: # %entry 4681; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4682; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4683; P9LE-NEXT: lxvx v2, 0, r3 4684; P9LE-NEXT: blr 4685; 4686; P8BE-LABEL: fromDiffConstsConvdtoll: 4687; P8BE: # %bb.0: # %entry 4688; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4689; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4690; P8BE-NEXT: lxvd2x v2, 0, r3 4691; P8BE-NEXT: blr 4692; 4693; P8LE-LABEL: fromDiffConstsConvdtoll: 4694; P8LE: # %bb.0: # %entry 4695; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4696; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4697; P8LE-NEXT: lxvd2x vs0, 0, r3 4698; P8LE-NEXT: xxswapd v2, vs0 4699; P8LE-NEXT: blr 4700entry: 4701 ret <2 x i64> <i64 24, i64 234> 4702} 4703 4704define <2 x i64> @fromDiffMemConsAConvdtoll(double* nocapture readonly %ptr) { 4705; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4706; P9BE: # %bb.0: # %entry 4707; P9BE-NEXT: lxv vs0, 0(r3) 4708; P9BE-NEXT: xvcvdpsxds v2, vs0 4709; P9BE-NEXT: blr 4710; 4711; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4712; P9LE: # %bb.0: # %entry 4713; P9LE-NEXT: lxv vs0, 0(r3) 4714; P9LE-NEXT: xvcvdpsxds v2, vs0 4715; P9LE-NEXT: blr 4716; 4717; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4718; P8BE: # %bb.0: # %entry 4719; P8BE-NEXT: lxvd2x vs0, 0, r3 4720; P8BE-NEXT: xvcvdpsxds v2, vs0 4721; P8BE-NEXT: blr 4722; 4723; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4724; P8LE: # %bb.0: # %entry 4725; P8LE-NEXT: lxvd2x vs0, 0, r3 4726; P8LE-NEXT: xxswapd vs0, vs0 4727; P8LE-NEXT: xvcvdpsxds v2, vs0 4728; P8LE-NEXT: blr 4729entry: 4730 %0 = bitcast double* %ptr to <2 x double>* 4731 %1 = load <2 x double>, <2 x double>* %0, align 8 4732 %2 = fptosi <2 x double> %1 to <2 x i64> 4733 ret <2 x i64> %2 4734} 4735 4736define <2 x i64> @fromDiffMemConsDConvdtoll(double* nocapture readonly %ptr) { 4737; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4738; P9BE: # %bb.0: # %entry 4739; P9BE-NEXT: lxv vs0, 16(r3) 4740; P9BE-NEXT: xxswapd vs0, vs0 4741; P9BE-NEXT: xvcvdpsxds v2, vs0 4742; P9BE-NEXT: blr 4743; 4744; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4745; P9LE: # %bb.0: # %entry 4746; P9LE-NEXT: addi r3, r3, 16 4747; P9LE-NEXT: lxvd2x vs0, 0, r3 4748; P9LE-NEXT: xvcvdpsxds v2, vs0 4749; P9LE-NEXT: blr 4750; 4751; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4752; P8BE: # %bb.0: # %entry 4753; P8BE-NEXT: addi r3, r3, 16 4754; P8BE-NEXT: lxvd2x vs0, 0, r3 4755; P8BE-NEXT: xxswapd vs0, vs0 4756; P8BE-NEXT: xvcvdpsxds v2, vs0 4757; P8BE-NEXT: blr 4758; 4759; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4760; P8LE: # %bb.0: # %entry 4761; P8LE-NEXT: addi r3, r3, 16 4762; P8LE-NEXT: lxvd2x vs0, 0, r3 4763; P8LE-NEXT: xvcvdpsxds v2, vs0 4764; P8LE-NEXT: blr 4765entry: 4766 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 4767 %0 = load double, double* %arrayidx, align 8 4768 %conv = fptosi double %0 to i64 4769 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4770 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 4771 %1 = load double, double* %arrayidx1, align 8 4772 %conv2 = fptosi double %1 to i64 4773 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4774 ret <2 x i64> %vecinit3 4775} 4776 4777define <2 x i64> @fromDiffMemVarAConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4778; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4779; P9BE: # %bb.0: # %entry 4780; P9BE-NEXT: sldi r4, r4, 3 4781; P9BE-NEXT: lxvx vs0, r3, r4 4782; P9BE-NEXT: xvcvdpsxds v2, vs0 4783; P9BE-NEXT: blr 4784; 4785; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4786; P9LE: # %bb.0: # %entry 4787; P9LE-NEXT: sldi r4, r4, 3 4788; P9LE-NEXT: lxvx vs0, r3, r4 4789; P9LE-NEXT: xvcvdpsxds v2, vs0 4790; P9LE-NEXT: blr 4791; 4792; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4793; P8BE: # %bb.0: # %entry 4794; P8BE-NEXT: sldi r4, r4, 3 4795; P8BE-NEXT: lxvd2x vs0, r3, r4 4796; P8BE-NEXT: xvcvdpsxds v2, vs0 4797; P8BE-NEXT: blr 4798; 4799; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4800; P8LE: # %bb.0: # %entry 4801; P8LE-NEXT: sldi r4, r4, 3 4802; P8LE-NEXT: lxvd2x vs0, r3, r4 4803; P8LE-NEXT: xxswapd vs0, vs0 4804; P8LE-NEXT: xvcvdpsxds v2, vs0 4805; P8LE-NEXT: blr 4806entry: 4807 %idxprom = sext i32 %elem to i64 4808 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4809 %0 = load double, double* %arrayidx, align 8 4810 %conv = fptosi double %0 to i64 4811 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4812 %add = add nsw i32 %elem, 1 4813 %idxprom1 = sext i32 %add to i64 4814 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4815 %1 = load double, double* %arrayidx2, align 8 4816 %conv3 = fptosi double %1 to i64 4817 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4818 ret <2 x i64> %vecinit4 4819} 4820 4821define <2 x i64> @fromDiffMemVarDConvdtoll(double* nocapture readonly %arr, i32 signext %elem) { 4822; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4823; P9BE: # %bb.0: # %entry 4824; P9BE-NEXT: sldi r4, r4, 3 4825; P9BE-NEXT: add r3, r3, r4 4826; P9BE-NEXT: li r4, -8 4827; P9BE-NEXT: lxvx vs0, r3, r4 4828; P9BE-NEXT: xxswapd vs0, vs0 4829; P9BE-NEXT: xvcvdpsxds v2, vs0 4830; P9BE-NEXT: blr 4831; 4832; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4833; P9LE: # %bb.0: # %entry 4834; P9LE-NEXT: sldi r4, r4, 3 4835; P9LE-NEXT: add r3, r3, r4 4836; P9LE-NEXT: addi r3, r3, -8 4837; P9LE-NEXT: lxvd2x vs0, 0, r3 4838; P9LE-NEXT: xvcvdpsxds v2, vs0 4839; P9LE-NEXT: blr 4840; 4841; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4842; P8BE: # %bb.0: # %entry 4843; P8BE-NEXT: sldi r4, r4, 3 4844; P8BE-NEXT: add r3, r3, r4 4845; P8BE-NEXT: addi r3, r3, -8 4846; P8BE-NEXT: lxvd2x vs0, 0, r3 4847; P8BE-NEXT: xxswapd vs0, vs0 4848; P8BE-NEXT: xvcvdpsxds v2, vs0 4849; P8BE-NEXT: blr 4850; 4851; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4852; P8LE: # %bb.0: # %entry 4853; P8LE-NEXT: sldi r4, r4, 3 4854; P8LE-NEXT: add r3, r3, r4 4855; P8LE-NEXT: addi r3, r3, -8 4856; P8LE-NEXT: lxvd2x vs0, 0, r3 4857; P8LE-NEXT: xvcvdpsxds v2, vs0 4858; P8LE-NEXT: blr 4859entry: 4860 %idxprom = sext i32 %elem to i64 4861 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 4862 %0 = load double, double* %arrayidx, align 8 4863 %conv = fptosi double %0 to i64 4864 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4865 %sub = add nsw i32 %elem, -1 4866 %idxprom1 = sext i32 %sub to i64 4867 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 4868 %1 = load double, double* %arrayidx2, align 8 4869 %conv3 = fptosi double %1 to i64 4870 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4871 ret <2 x i64> %vecinit4 4872} 4873 4874define <2 x i64> @spltRegValConvdtoll(double %val) { 4875; P9BE-LABEL: spltRegValConvdtoll: 4876; P9BE: # %bb.0: # %entry 4877; P9BE-NEXT: xscvdpsxds f0, f1 4878; P9BE-NEXT: xxspltd v2, vs0, 0 4879; P9BE-NEXT: blr 4880; 4881; P9LE-LABEL: spltRegValConvdtoll: 4882; P9LE: # %bb.0: # %entry 4883; P9LE-NEXT: xscvdpsxds f0, f1 4884; P9LE-NEXT: xxspltd v2, vs0, 0 4885; P9LE-NEXT: blr 4886; 4887; P8BE-LABEL: spltRegValConvdtoll: 4888; P8BE: # %bb.0: # %entry 4889; P8BE-NEXT: xscvdpsxds f0, f1 4890; P8BE-NEXT: xxspltd v2, vs0, 0 4891; P8BE-NEXT: blr 4892; 4893; P8LE-LABEL: spltRegValConvdtoll: 4894; P8LE: # %bb.0: # %entry 4895; P8LE-NEXT: xscvdpsxds f0, f1 4896; P8LE-NEXT: xxspltd v2, vs0, 0 4897; P8LE-NEXT: blr 4898entry: 4899 %conv = fptosi double %val to i64 4900 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4901 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4902 ret <2 x i64> %splat.splat 4903} 4904 4905define <2 x i64> @spltMemValConvdtoll(double* nocapture readonly %ptr) { 4906; P9BE-LABEL: spltMemValConvdtoll: 4907; P9BE: # %bb.0: # %entry 4908; P9BE-NEXT: lxvdsx vs0, 0, r3 4909; P9BE-NEXT: xvcvdpsxds v2, vs0 4910; P9BE-NEXT: blr 4911; 4912; P9LE-LABEL: spltMemValConvdtoll: 4913; P9LE: # %bb.0: # %entry 4914; P9LE-NEXT: lxvdsx vs0, 0, r3 4915; P9LE-NEXT: xvcvdpsxds v2, vs0 4916; P9LE-NEXT: blr 4917; 4918; P8BE-LABEL: spltMemValConvdtoll: 4919; P8BE: # %bb.0: # %entry 4920; P8BE-NEXT: lxvdsx vs0, 0, r3 4921; P8BE-NEXT: xvcvdpsxds v2, vs0 4922; P8BE-NEXT: blr 4923; 4924; P8LE-LABEL: spltMemValConvdtoll: 4925; P8LE: # %bb.0: # %entry 4926; P8LE-NEXT: lxvdsx vs0, 0, r3 4927; P8LE-NEXT: xvcvdpsxds v2, vs0 4928; P8LE-NEXT: blr 4929entry: 4930 %0 = load double, double* %ptr, align 8 4931 %conv = fptosi double %0 to i64 4932 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4933 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4934 ret <2 x i64> %splat.splat 4935} 4936 4937define <2 x i64> @allZeroull() { 4938; P9BE-LABEL: allZeroull: 4939; P9BE: # %bb.0: # %entry 4940; P9BE-NEXT: xxlxor v2, v2, v2 4941; P9BE-NEXT: blr 4942; 4943; P9LE-LABEL: allZeroull: 4944; P9LE: # %bb.0: # %entry 4945; P9LE-NEXT: xxlxor v2, v2, v2 4946; P9LE-NEXT: blr 4947; 4948; P8BE-LABEL: allZeroull: 4949; P8BE: # %bb.0: # %entry 4950; P8BE-NEXT: xxlxor v2, v2, v2 4951; P8BE-NEXT: blr 4952; 4953; P8LE-LABEL: allZeroull: 4954; P8LE: # %bb.0: # %entry 4955; P8LE-NEXT: xxlxor v2, v2, v2 4956; P8LE-NEXT: blr 4957entry: 4958 ret <2 x i64> zeroinitializer 4959} 4960 4961define <2 x i64> @spltConst1ull() { 4962; P9BE-LABEL: spltConst1ull: 4963; P9BE: # %bb.0: # %entry 4964; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4965; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4966; P9BE-NEXT: lxvx v2, 0, r3 4967; P9BE-NEXT: blr 4968; 4969; P9LE-LABEL: spltConst1ull: 4970; P9LE: # %bb.0: # %entry 4971; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4972; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4973; P9LE-NEXT: lxvx v2, 0, r3 4974; P9LE-NEXT: blr 4975; 4976; P8BE-LABEL: spltConst1ull: 4977; P8BE: # %bb.0: # %entry 4978; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4979; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4980; P8BE-NEXT: lxvd2x v2, 0, r3 4981; P8BE-NEXT: blr 4982; 4983; P8LE-LABEL: spltConst1ull: 4984; P8LE: # %bb.0: # %entry 4985; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4986; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4987; P8LE-NEXT: lxvd2x vs0, 0, r3 4988; P8LE-NEXT: xxswapd v2, vs0 4989; P8LE-NEXT: blr 4990entry: 4991 ret <2 x i64> <i64 1, i64 1> 4992} 4993 4994define <2 x i64> @spltConst16kull() { 4995; P9BE-LABEL: spltConst16kull: 4996; P9BE: # %bb.0: # %entry 4997; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 4998; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 4999; P9BE-NEXT: lxvx v2, 0, r3 5000; P9BE-NEXT: blr 5001; 5002; P9LE-LABEL: spltConst16kull: 5003; P9LE: # %bb.0: # %entry 5004; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5005; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5006; P9LE-NEXT: lxvx v2, 0, r3 5007; P9LE-NEXT: blr 5008; 5009; P8BE-LABEL: spltConst16kull: 5010; P8BE: # %bb.0: # %entry 5011; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5012; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5013; P8BE-NEXT: lxvd2x v2, 0, r3 5014; P8BE-NEXT: blr 5015; 5016; P8LE-LABEL: spltConst16kull: 5017; P8LE: # %bb.0: # %entry 5018; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 5019; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 5020; P8LE-NEXT: lxvd2x vs0, 0, r3 5021; P8LE-NEXT: xxswapd v2, vs0 5022; P8LE-NEXT: blr 5023entry: 5024 ret <2 x i64> <i64 32767, i64 32767> 5025} 5026 5027define <2 x i64> @spltConst32kull() { 5028; P9BE-LABEL: spltConst32kull: 5029; P9BE: # %bb.0: # %entry 5030; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5031; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5032; P9BE-NEXT: lxvx v2, 0, r3 5033; P9BE-NEXT: blr 5034; 5035; P9LE-LABEL: spltConst32kull: 5036; P9LE: # %bb.0: # %entry 5037; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5038; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5039; P9LE-NEXT: lxvx v2, 0, r3 5040; P9LE-NEXT: blr 5041; 5042; P8BE-LABEL: spltConst32kull: 5043; P8BE: # %bb.0: # %entry 5044; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5045; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5046; P8BE-NEXT: lxvd2x v2, 0, r3 5047; P8BE-NEXT: blr 5048; 5049; P8LE-LABEL: spltConst32kull: 5050; P8LE: # %bb.0: # %entry 5051; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 5052; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 5053; P8LE-NEXT: lxvd2x vs0, 0, r3 5054; P8LE-NEXT: xxswapd v2, vs0 5055; P8LE-NEXT: blr 5056entry: 5057 ret <2 x i64> <i64 65535, i64 65535> 5058} 5059 5060define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 5061; P9BE-LABEL: fromRegsull: 5062; P9BE: # %bb.0: # %entry 5063; P9BE-NEXT: mtvsrdd v2, r3, r4 5064; P9BE-NEXT: blr 5065; 5066; P9LE-LABEL: fromRegsull: 5067; P9LE: # %bb.0: # %entry 5068; P9LE-NEXT: mtvsrdd v2, r4, r3 5069; P9LE-NEXT: blr 5070; 5071; P8BE-LABEL: fromRegsull: 5072; P8BE: # %bb.0: # %entry 5073; P8BE-NEXT: mtfprd f0, r4 5074; P8BE-NEXT: mtfprd f1, r3 5075; P8BE-NEXT: xxmrghd v2, vs1, vs0 5076; P8BE-NEXT: blr 5077; 5078; P8LE-LABEL: fromRegsull: 5079; P8LE: # %bb.0: # %entry 5080; P8LE-NEXT: mtfprd f0, r3 5081; P8LE-NEXT: mtfprd f1, r4 5082; P8LE-NEXT: xxmrghd v2, vs1, vs0 5083; P8LE-NEXT: blr 5084entry: 5085 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5086 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5087 ret <2 x i64> %vecinit1 5088} 5089 5090define <2 x i64> @fromDiffConstsull() { 5091; P9BE-LABEL: fromDiffConstsull: 5092; P9BE: # %bb.0: # %entry 5093; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5094; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5095; P9BE-NEXT: lxvx v2, 0, r3 5096; P9BE-NEXT: blr 5097; 5098; P9LE-LABEL: fromDiffConstsull: 5099; P9LE: # %bb.0: # %entry 5100; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5101; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5102; P9LE-NEXT: lxvx v2, 0, r3 5103; P9LE-NEXT: blr 5104; 5105; P8BE-LABEL: fromDiffConstsull: 5106; P8BE: # %bb.0: # %entry 5107; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5108; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5109; P8BE-NEXT: lxvd2x v2, 0, r3 5110; P8BE-NEXT: blr 5111; 5112; P8LE-LABEL: fromDiffConstsull: 5113; P8LE: # %bb.0: # %entry 5114; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5115; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5116; P8LE-NEXT: lxvd2x vs0, 0, r3 5117; P8LE-NEXT: xxswapd v2, vs0 5118; P8LE-NEXT: blr 5119entry: 5120 ret <2 x i64> <i64 242, i64 -113> 5121} 5122 5123define <2 x i64> @fromDiffMemConsAull(i64* nocapture readonly %arr) { 5124; P9BE-LABEL: fromDiffMemConsAull: 5125; P9BE: # %bb.0: # %entry 5126; P9BE-NEXT: lxv v2, 0(r3) 5127; P9BE-NEXT: blr 5128; 5129; P9LE-LABEL: fromDiffMemConsAull: 5130; P9LE: # %bb.0: # %entry 5131; P9LE-NEXT: lxv v2, 0(r3) 5132; P9LE-NEXT: blr 5133; 5134; P8BE-LABEL: fromDiffMemConsAull: 5135; P8BE: # %bb.0: # %entry 5136; P8BE-NEXT: lxvd2x v2, 0, r3 5137; P8BE-NEXT: blr 5138; 5139; P8LE-LABEL: fromDiffMemConsAull: 5140; P8LE: # %bb.0: # %entry 5141; P8LE-NEXT: lxvd2x vs0, 0, r3 5142; P8LE-NEXT: xxswapd v2, vs0 5143; P8LE-NEXT: blr 5144entry: 5145 %0 = load i64, i64* %arr, align 8 5146 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5147 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 1 5148 %1 = load i64, i64* %arrayidx1, align 8 5149 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5150 ret <2 x i64> %vecinit2 5151} 5152 5153define <2 x i64> @fromDiffMemConsDull(i64* nocapture readonly %arr) { 5154; P9BE-LABEL: fromDiffMemConsDull: 5155; P9BE: # %bb.0: # %entry 5156; P9BE-NEXT: lxv v2, 16(r3) 5157; P9BE-NEXT: xxswapd v2, v2 5158; P9BE-NEXT: blr 5159; 5160; P9LE-LABEL: fromDiffMemConsDull: 5161; P9LE: # %bb.0: # %entry 5162; P9LE-NEXT: addi r3, r3, 16 5163; P9LE-NEXT: lxvd2x v2, 0, r3 5164; P9LE-NEXT: blr 5165; 5166; P8BE-LABEL: fromDiffMemConsDull: 5167; P8BE: # %bb.0: # %entry 5168; P8BE-NEXT: addi r3, r3, 16 5169; P8BE-NEXT: lxvd2x v2, 0, r3 5170; P8BE-NEXT: xxswapd v2, v2 5171; P8BE-NEXT: blr 5172; 5173; P8LE-LABEL: fromDiffMemConsDull: 5174; P8LE: # %bb.0: # %entry 5175; P8LE-NEXT: addi r3, r3, 16 5176; P8LE-NEXT: lxvd2x v2, 0, r3 5177; P8LE-NEXT: blr 5178entry: 5179 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 3 5180 %0 = load i64, i64* %arrayidx, align 8 5181 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5182 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 2 5183 %1 = load i64, i64* %arrayidx1, align 8 5184 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5185 ret <2 x i64> %vecinit2 5186} 5187 5188define <2 x i64> @fromDiffMemVarAull(i64* nocapture readonly %arr, i32 signext %elem) { 5189; P9BE-LABEL: fromDiffMemVarAull: 5190; P9BE: # %bb.0: # %entry 5191; P9BE-NEXT: sldi r4, r4, 3 5192; P9BE-NEXT: lxvx v2, r3, r4 5193; P9BE-NEXT: blr 5194; 5195; P9LE-LABEL: fromDiffMemVarAull: 5196; P9LE: # %bb.0: # %entry 5197; P9LE-NEXT: sldi r4, r4, 3 5198; P9LE-NEXT: lxvx v2, r3, r4 5199; P9LE-NEXT: blr 5200; 5201; P8BE-LABEL: fromDiffMemVarAull: 5202; P8BE: # %bb.0: # %entry 5203; P8BE-NEXT: sldi r4, r4, 3 5204; P8BE-NEXT: lxvd2x v2, r3, r4 5205; P8BE-NEXT: blr 5206; 5207; P8LE-LABEL: fromDiffMemVarAull: 5208; P8LE: # %bb.0: # %entry 5209; P8LE-NEXT: sldi r4, r4, 3 5210; P8LE-NEXT: lxvd2x vs0, r3, r4 5211; P8LE-NEXT: xxswapd v2, vs0 5212; P8LE-NEXT: blr 5213entry: 5214 %idxprom = sext i32 %elem to i64 5215 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5216 %0 = load i64, i64* %arrayidx, align 8 5217 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5218 %add = add nsw i32 %elem, 1 5219 %idxprom1 = sext i32 %add to i64 5220 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5221 %1 = load i64, i64* %arrayidx2, align 8 5222 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5223 ret <2 x i64> %vecinit3 5224} 5225 5226define <2 x i64> @fromDiffMemVarDull(i64* nocapture readonly %arr, i32 signext %elem) { 5227; P9BE-LABEL: fromDiffMemVarDull: 5228; P9BE: # %bb.0: # %entry 5229; P9BE-NEXT: sldi r4, r4, 3 5230; P9BE-NEXT: add r3, r3, r4 5231; P9BE-NEXT: li r4, -8 5232; P9BE-NEXT: lxvx v2, r3, r4 5233; P9BE-NEXT: xxswapd v2, v2 5234; P9BE-NEXT: blr 5235; 5236; P9LE-LABEL: fromDiffMemVarDull: 5237; P9LE: # %bb.0: # %entry 5238; P9LE-NEXT: sldi r4, r4, 3 5239; P9LE-NEXT: add r3, r3, r4 5240; P9LE-NEXT: addi r3, r3, -8 5241; P9LE-NEXT: lxvd2x v2, 0, r3 5242; P9LE-NEXT: blr 5243; 5244; P8BE-LABEL: fromDiffMemVarDull: 5245; P8BE: # %bb.0: # %entry 5246; P8BE-NEXT: sldi r4, r4, 3 5247; P8BE-NEXT: add r3, r3, r4 5248; P8BE-NEXT: addi r3, r3, -8 5249; P8BE-NEXT: lxvd2x v2, 0, r3 5250; P8BE-NEXT: xxswapd v2, v2 5251; P8BE-NEXT: blr 5252; 5253; P8LE-LABEL: fromDiffMemVarDull: 5254; P8LE: # %bb.0: # %entry 5255; P8LE-NEXT: sldi r4, r4, 3 5256; P8LE-NEXT: add r3, r3, r4 5257; P8LE-NEXT: addi r3, r3, -8 5258; P8LE-NEXT: lxvd2x v2, 0, r3 5259; P8LE-NEXT: blr 5260entry: 5261 %idxprom = sext i32 %elem to i64 5262 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5263 %0 = load i64, i64* %arrayidx, align 8 5264 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5265 %sub = add nsw i32 %elem, -1 5266 %idxprom1 = sext i32 %sub to i64 5267 %arrayidx2 = getelementptr inbounds i64, i64* %arr, i64 %idxprom1 5268 %1 = load i64, i64* %arrayidx2, align 8 5269 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5270 ret <2 x i64> %vecinit3 5271} 5272 5273define <2 x i64> @fromRandMemConsull(i64* nocapture readonly %arr) { 5274; P9BE-LABEL: fromRandMemConsull: 5275; P9BE: # %bb.0: # %entry 5276; P9BE-NEXT: ld r4, 32(r3) 5277; P9BE-NEXT: ld r3, 144(r3) 5278; P9BE-NEXT: mtvsrdd v2, r4, r3 5279; P9BE-NEXT: blr 5280; 5281; P9LE-LABEL: fromRandMemConsull: 5282; P9LE: # %bb.0: # %entry 5283; P9LE-NEXT: ld r4, 32(r3) 5284; P9LE-NEXT: ld r3, 144(r3) 5285; P9LE-NEXT: mtvsrdd v2, r3, r4 5286; P9LE-NEXT: blr 5287; 5288; P8BE-LABEL: fromRandMemConsull: 5289; P8BE: # %bb.0: # %entry 5290; P8BE-NEXT: ld r4, 144(r3) 5291; P8BE-NEXT: ld r3, 32(r3) 5292; P8BE-NEXT: mtfprd f0, r4 5293; P8BE-NEXT: mtfprd f1, r3 5294; P8BE-NEXT: xxmrghd v2, vs1, vs0 5295; P8BE-NEXT: blr 5296; 5297; P8LE-LABEL: fromRandMemConsull: 5298; P8LE: # %bb.0: # %entry 5299; P8LE-NEXT: ld r4, 32(r3) 5300; P8LE-NEXT: ld r3, 144(r3) 5301; P8LE-NEXT: mtfprd f0, r4 5302; P8LE-NEXT: mtfprd f1, r3 5303; P8LE-NEXT: xxmrghd v2, vs1, vs0 5304; P8LE-NEXT: blr 5305entry: 5306 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 5307 %0 = load i64, i64* %arrayidx, align 8 5308 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5309 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 5310 %1 = load i64, i64* %arrayidx1, align 8 5311 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5312 ret <2 x i64> %vecinit2 5313} 5314 5315define <2 x i64> @fromRandMemVarull(i64* nocapture readonly %arr, i32 signext %elem) { 5316; P9BE-LABEL: fromRandMemVarull: 5317; P9BE: # %bb.0: # %entry 5318; P9BE-NEXT: sldi r4, r4, 3 5319; P9BE-NEXT: add r3, r3, r4 5320; P9BE-NEXT: ld r4, 32(r3) 5321; P9BE-NEXT: ld r3, 8(r3) 5322; P9BE-NEXT: mtvsrdd v2, r4, r3 5323; P9BE-NEXT: blr 5324; 5325; P9LE-LABEL: fromRandMemVarull: 5326; P9LE: # %bb.0: # %entry 5327; P9LE-NEXT: sldi r4, r4, 3 5328; P9LE-NEXT: add r3, r3, r4 5329; P9LE-NEXT: ld r4, 32(r3) 5330; P9LE-NEXT: ld r3, 8(r3) 5331; P9LE-NEXT: mtvsrdd v2, r3, r4 5332; P9LE-NEXT: blr 5333; 5334; P8BE-LABEL: fromRandMemVarull: 5335; P8BE: # %bb.0: # %entry 5336; P8BE-NEXT: sldi r4, r4, 3 5337; P8BE-NEXT: add r3, r3, r4 5338; P8BE-NEXT: ld r4, 8(r3) 5339; P8BE-NEXT: ld r3, 32(r3) 5340; P8BE-NEXT: mtfprd f0, r4 5341; P8BE-NEXT: mtfprd f1, r3 5342; P8BE-NEXT: xxmrghd v2, vs1, vs0 5343; P8BE-NEXT: blr 5344; 5345; P8LE-LABEL: fromRandMemVarull: 5346; P8LE: # %bb.0: # %entry 5347; P8LE-NEXT: sldi r4, r4, 3 5348; P8LE-NEXT: add r3, r3, r4 5349; P8LE-NEXT: ld r4, 32(r3) 5350; P8LE-NEXT: ld r3, 8(r3) 5351; P8LE-NEXT: mtfprd f0, r4 5352; P8LE-NEXT: mtfprd f1, r3 5353; P8LE-NEXT: xxmrghd v2, vs1, vs0 5354; P8LE-NEXT: blr 5355entry: 5356 %add = add nsw i32 %elem, 4 5357 %idxprom = sext i32 %add to i64 5358 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom 5359 %0 = load i64, i64* %arrayidx, align 8 5360 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5361 %add1 = add nsw i32 %elem, 1 5362 %idxprom2 = sext i32 %add1 to i64 5363 %arrayidx3 = getelementptr inbounds i64, i64* %arr, i64 %idxprom2 5364 %1 = load i64, i64* %arrayidx3, align 8 5365 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5366 ret <2 x i64> %vecinit4 5367} 5368 5369define <2 x i64> @spltRegValull(i64 %val) { 5370; P9BE-LABEL: spltRegValull: 5371; P9BE: # %bb.0: # %entry 5372; P9BE-NEXT: mtvsrdd v2, r3, r3 5373; P9BE-NEXT: blr 5374; 5375; P9LE-LABEL: spltRegValull: 5376; P9LE: # %bb.0: # %entry 5377; P9LE-NEXT: mtvsrdd v2, r3, r3 5378; P9LE-NEXT: blr 5379; 5380; P8BE-LABEL: spltRegValull: 5381; P8BE: # %bb.0: # %entry 5382; P8BE-NEXT: mtfprd f0, r3 5383; P8BE-NEXT: xxspltd v2, vs0, 0 5384; P8BE-NEXT: blr 5385; 5386; P8LE-LABEL: spltRegValull: 5387; P8LE: # %bb.0: # %entry 5388; P8LE-NEXT: mtfprd f0, r3 5389; P8LE-NEXT: xxspltd v2, vs0, 0 5390; P8LE-NEXT: blr 5391entry: 5392 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5393 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5394 ret <2 x i64> %splat.splat 5395} 5396 5397define <2 x i64> @spltMemValull(i64* nocapture readonly %ptr) { 5398; P9BE-LABEL: spltMemValull: 5399; P9BE: # %bb.0: # %entry 5400; P9BE-NEXT: lxvdsx v2, 0, r3 5401; P9BE-NEXT: blr 5402; 5403; P9LE-LABEL: spltMemValull: 5404; P9LE: # %bb.0: # %entry 5405; P9LE-NEXT: lxvdsx v2, 0, r3 5406; P9LE-NEXT: blr 5407; 5408; P8BE-LABEL: spltMemValull: 5409; P8BE: # %bb.0: # %entry 5410; P8BE-NEXT: lxvdsx v2, 0, r3 5411; P8BE-NEXT: blr 5412; 5413; P8LE-LABEL: spltMemValull: 5414; P8LE: # %bb.0: # %entry 5415; P8LE-NEXT: lxvdsx v2, 0, r3 5416; P8LE-NEXT: blr 5417entry: 5418 %0 = load i64, i64* %ptr, align 8 5419 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5420 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5421 ret <2 x i64> %splat.splat 5422} 5423 5424define <2 x i64> @spltCnstConvftoull() { 5425; P9BE-LABEL: spltCnstConvftoull: 5426; P9BE: # %bb.0: # %entry 5427; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5428; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5429; P9BE-NEXT: lxvx v2, 0, r3 5430; P9BE-NEXT: blr 5431; 5432; P9LE-LABEL: spltCnstConvftoull: 5433; P9LE: # %bb.0: # %entry 5434; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5435; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5436; P9LE-NEXT: lxvx v2, 0, r3 5437; P9LE-NEXT: blr 5438; 5439; P8BE-LABEL: spltCnstConvftoull: 5440; P8BE: # %bb.0: # %entry 5441; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5442; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5443; P8BE-NEXT: lxvd2x v2, 0, r3 5444; P8BE-NEXT: blr 5445; 5446; P8LE-LABEL: spltCnstConvftoull: 5447; P8LE: # %bb.0: # %entry 5448; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5449; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5450; P8LE-NEXT: lxvd2x vs0, 0, r3 5451; P8LE-NEXT: xxswapd v2, vs0 5452; P8LE-NEXT: blr 5453entry: 5454 ret <2 x i64> <i64 4, i64 4> 5455} 5456 5457define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5458; P9BE-LABEL: fromRegsConvftoull: 5459; P9BE: # %bb.0: # %entry 5460; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5461; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5462; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5463; P9BE-NEXT: xvcvdpuxds v2, vs0 5464; P9BE-NEXT: blr 5465; 5466; P9LE-LABEL: fromRegsConvftoull: 5467; P9LE: # %bb.0: # %entry 5468; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5469; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5470; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5471; P9LE-NEXT: xvcvdpuxds v2, vs0 5472; P9LE-NEXT: blr 5473; 5474; P8BE-LABEL: fromRegsConvftoull: 5475; P8BE: # %bb.0: # %entry 5476; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5477; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5478; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5479; P8BE-NEXT: xvcvdpuxds v2, vs0 5480; P8BE-NEXT: blr 5481; 5482; P8LE-LABEL: fromRegsConvftoull: 5483; P8LE: # %bb.0: # %entry 5484; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5485; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5486; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5487; P8LE-NEXT: xvcvdpuxds v2, vs0 5488; P8LE-NEXT: blr 5489entry: 5490 %conv = fptoui float %a to i64 5491 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5492 %conv1 = fptoui float %b to i64 5493 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5494 ret <2 x i64> %vecinit2 5495} 5496 5497define <2 x i64> @fromDiffConstsConvftoull() { 5498; P9BE-LABEL: fromDiffConstsConvftoull: 5499; P9BE: # %bb.0: # %entry 5500; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5501; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5502; P9BE-NEXT: lxvx v2, 0, r3 5503; P9BE-NEXT: blr 5504; 5505; P9LE-LABEL: fromDiffConstsConvftoull: 5506; P9LE: # %bb.0: # %entry 5507; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5508; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5509; P9LE-NEXT: lxvx v2, 0, r3 5510; P9LE-NEXT: blr 5511; 5512; P8BE-LABEL: fromDiffConstsConvftoull: 5513; P8BE: # %bb.0: # %entry 5514; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5515; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5516; P8BE-NEXT: lxvd2x v2, 0, r3 5517; P8BE-NEXT: blr 5518; 5519; P8LE-LABEL: fromDiffConstsConvftoull: 5520; P8LE: # %bb.0: # %entry 5521; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5522; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5523; P8LE-NEXT: lxvd2x vs0, 0, r3 5524; P8LE-NEXT: xxswapd v2, vs0 5525; P8LE-NEXT: blr 5526entry: 5527 ret <2 x i64> <i64 24, i64 234> 5528} 5529 5530define <2 x i64> @fromDiffMemConsAConvftoull(float* nocapture readonly %ptr) { 5531; P9BE-LABEL: fromDiffMemConsAConvftoull: 5532; P9BE: # %bb.0: # %entry 5533; P9BE-NEXT: lfs f0, 0(r3) 5534; P9BE-NEXT: lfs f1, 4(r3) 5535; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5536; P9BE-NEXT: xvcvdpuxds v2, vs0 5537; P9BE-NEXT: blr 5538; 5539; P9LE-LABEL: fromDiffMemConsAConvftoull: 5540; P9LE: # %bb.0: # %entry 5541; P9LE-NEXT: lfs f0, 0(r3) 5542; P9LE-NEXT: lfs f1, 4(r3) 5543; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5544; P9LE-NEXT: xvcvdpuxds v2, vs0 5545; P9LE-NEXT: blr 5546; 5547; P8BE-LABEL: fromDiffMemConsAConvftoull: 5548; P8BE: # %bb.0: # %entry 5549; P8BE-NEXT: lfsx f0, 0, r3 5550; P8BE-NEXT: lfs f1, 4(r3) 5551; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5552; P8BE-NEXT: xvcvdpuxds v2, vs0 5553; P8BE-NEXT: blr 5554; 5555; P8LE-LABEL: fromDiffMemConsAConvftoull: 5556; P8LE: # %bb.0: # %entry 5557; P8LE-NEXT: lfsx f0, 0, r3 5558; P8LE-NEXT: lfs f1, 4(r3) 5559; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5560; P8LE-NEXT: xvcvdpuxds v2, vs0 5561; P8LE-NEXT: blr 5562entry: 5563 %0 = load float, float* %ptr, align 4 5564 %conv = fptoui float %0 to i64 5565 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5566 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 1 5567 %1 = load float, float* %arrayidx1, align 4 5568 %conv2 = fptoui float %1 to i64 5569 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5570 ret <2 x i64> %vecinit3 5571} 5572 5573define <2 x i64> @fromDiffMemConsDConvftoull(float* nocapture readonly %ptr) { 5574; P9BE-LABEL: fromDiffMemConsDConvftoull: 5575; P9BE: # %bb.0: # %entry 5576; P9BE-NEXT: lfs f0, 12(r3) 5577; P9BE-NEXT: lfs f1, 8(r3) 5578; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5579; P9BE-NEXT: xvcvdpuxds v2, vs0 5580; P9BE-NEXT: blr 5581; 5582; P9LE-LABEL: fromDiffMemConsDConvftoull: 5583; P9LE: # %bb.0: # %entry 5584; P9LE-NEXT: lfs f0, 12(r3) 5585; P9LE-NEXT: lfs f1, 8(r3) 5586; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5587; P9LE-NEXT: xvcvdpuxds v2, vs0 5588; P9LE-NEXT: blr 5589; 5590; P8BE-LABEL: fromDiffMemConsDConvftoull: 5591; P8BE: # %bb.0: # %entry 5592; P8BE-NEXT: lfs f0, 12(r3) 5593; P8BE-NEXT: lfs f1, 8(r3) 5594; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5595; P8BE-NEXT: xvcvdpuxds v2, vs0 5596; P8BE-NEXT: blr 5597; 5598; P8LE-LABEL: fromDiffMemConsDConvftoull: 5599; P8LE: # %bb.0: # %entry 5600; P8LE-NEXT: lfs f0, 12(r3) 5601; P8LE-NEXT: lfs f1, 8(r3) 5602; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5603; P8LE-NEXT: xvcvdpuxds v2, vs0 5604; P8LE-NEXT: blr 5605entry: 5606 %arrayidx = getelementptr inbounds float, float* %ptr, i64 3 5607 %0 = load float, float* %arrayidx, align 4 5608 %conv = fptoui float %0 to i64 5609 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5610 %arrayidx1 = getelementptr inbounds float, float* %ptr, i64 2 5611 %1 = load float, float* %arrayidx1, align 4 5612 %conv2 = fptoui float %1 to i64 5613 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5614 ret <2 x i64> %vecinit3 5615} 5616 5617define <2 x i64> @fromDiffMemVarAConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5618; P9BE-LABEL: fromDiffMemVarAConvftoull: 5619; P9BE: # %bb.0: # %entry 5620; P9BE-NEXT: sldi r4, r4, 2 5621; P9BE-NEXT: lfsux f0, r3, r4 5622; P9BE-NEXT: lfs f1, 4(r3) 5623; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5624; P9BE-NEXT: xvcvdpuxds v2, vs0 5625; P9BE-NEXT: blr 5626; 5627; P9LE-LABEL: fromDiffMemVarAConvftoull: 5628; P9LE: # %bb.0: # %entry 5629; P9LE-NEXT: sldi r4, r4, 2 5630; P9LE-NEXT: lfsux f0, r3, r4 5631; P9LE-NEXT: lfs f1, 4(r3) 5632; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5633; P9LE-NEXT: xvcvdpuxds v2, vs0 5634; P9LE-NEXT: blr 5635; 5636; P8BE-LABEL: fromDiffMemVarAConvftoull: 5637; P8BE: # %bb.0: # %entry 5638; P8BE-NEXT: sldi r4, r4, 2 5639; P8BE-NEXT: lfsux f0, r3, r4 5640; P8BE-NEXT: lfs f1, 4(r3) 5641; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5642; P8BE-NEXT: xvcvdpuxds v2, vs0 5643; P8BE-NEXT: blr 5644; 5645; P8LE-LABEL: fromDiffMemVarAConvftoull: 5646; P8LE: # %bb.0: # %entry 5647; P8LE-NEXT: sldi r4, r4, 2 5648; P8LE-NEXT: lfsux f0, r3, r4 5649; P8LE-NEXT: lfs f1, 4(r3) 5650; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5651; P8LE-NEXT: xvcvdpuxds v2, vs0 5652; P8LE-NEXT: blr 5653entry: 5654 %idxprom = sext i32 %elem to i64 5655 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5656 %0 = load float, float* %arrayidx, align 4 5657 %conv = fptoui float %0 to i64 5658 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5659 %add = add nsw i32 %elem, 1 5660 %idxprom1 = sext i32 %add to i64 5661 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5662 %1 = load float, float* %arrayidx2, align 4 5663 %conv3 = fptoui float %1 to i64 5664 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5665 ret <2 x i64> %vecinit4 5666} 5667 5668define <2 x i64> @fromDiffMemVarDConvftoull(float* nocapture readonly %arr, i32 signext %elem) { 5669; P9BE-LABEL: fromDiffMemVarDConvftoull: 5670; P9BE: # %bb.0: # %entry 5671; P9BE-NEXT: sldi r4, r4, 2 5672; P9BE-NEXT: lfsux f0, r3, r4 5673; P9BE-NEXT: lfs f1, -4(r3) 5674; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5675; P9BE-NEXT: xvcvdpuxds v2, vs0 5676; P9BE-NEXT: blr 5677; 5678; P9LE-LABEL: fromDiffMemVarDConvftoull: 5679; P9LE: # %bb.0: # %entry 5680; P9LE-NEXT: sldi r4, r4, 2 5681; P9LE-NEXT: lfsux f0, r3, r4 5682; P9LE-NEXT: lfs f1, -4(r3) 5683; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5684; P9LE-NEXT: xvcvdpuxds v2, vs0 5685; P9LE-NEXT: blr 5686; 5687; P8BE-LABEL: fromDiffMemVarDConvftoull: 5688; P8BE: # %bb.0: # %entry 5689; P8BE-NEXT: sldi r4, r4, 2 5690; P8BE-NEXT: lfsux f0, r3, r4 5691; P8BE-NEXT: lfs f1, -4(r3) 5692; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5693; P8BE-NEXT: xvcvdpuxds v2, vs0 5694; P8BE-NEXT: blr 5695; 5696; P8LE-LABEL: fromDiffMemVarDConvftoull: 5697; P8LE: # %bb.0: # %entry 5698; P8LE-NEXT: sldi r4, r4, 2 5699; P8LE-NEXT: lfsux f0, r3, r4 5700; P8LE-NEXT: lfs f1, -4(r3) 5701; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5702; P8LE-NEXT: xvcvdpuxds v2, vs0 5703; P8LE-NEXT: blr 5704entry: 5705 %idxprom = sext i32 %elem to i64 5706 %arrayidx = getelementptr inbounds float, float* %arr, i64 %idxprom 5707 %0 = load float, float* %arrayidx, align 4 5708 %conv = fptoui float %0 to i64 5709 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5710 %sub = add nsw i32 %elem, -1 5711 %idxprom1 = sext i32 %sub to i64 5712 %arrayidx2 = getelementptr inbounds float, float* %arr, i64 %idxprom1 5713 %1 = load float, float* %arrayidx2, align 4 5714 %conv3 = fptoui float %1 to i64 5715 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5716 ret <2 x i64> %vecinit4 5717} 5718 5719define <2 x i64> @spltRegValConvftoull(float %val) { 5720; P9BE-LABEL: spltRegValConvftoull: 5721; P9BE: # %bb.0: # %entry 5722; P9BE-NEXT: xscvdpuxds f0, f1 5723; P9BE-NEXT: xxspltd v2, f0, 0 5724; P9BE-NEXT: blr 5725; 5726; P9LE-LABEL: spltRegValConvftoull: 5727; P9LE: # %bb.0: # %entry 5728; P9LE-NEXT: xscvdpuxds f0, f1 5729; P9LE-NEXT: xxspltd v2, f0, 0 5730; P9LE-NEXT: blr 5731; 5732; P8BE-LABEL: spltRegValConvftoull: 5733; P8BE: # %bb.0: # %entry 5734; P8BE-NEXT: xscvdpuxds f0, f1 5735; P8BE-NEXT: xxspltd v2, f0, 0 5736; P8BE-NEXT: blr 5737; 5738; P8LE-LABEL: spltRegValConvftoull: 5739; P8LE: # %bb.0: # %entry 5740; P8LE-NEXT: xscvdpuxds f0, f1 5741; P8LE-NEXT: xxspltd v2, f0, 0 5742; P8LE-NEXT: blr 5743entry: 5744 %conv = fptoui float %val to i64 5745 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5746 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5747 ret <2 x i64> %splat.splat 5748} 5749 5750define <2 x i64> @spltMemValConvftoull(float* nocapture readonly %ptr) { 5751; P9BE-LABEL: spltMemValConvftoull: 5752; P9BE: # %bb.0: # %entry 5753; P9BE-NEXT: lfs f0, 0(r3) 5754; P9BE-NEXT: xscvdpuxds f0, f0 5755; P9BE-NEXT: xxspltd v2, f0, 0 5756; P9BE-NEXT: blr 5757; 5758; P9LE-LABEL: spltMemValConvftoull: 5759; P9LE: # %bb.0: # %entry 5760; P9LE-NEXT: lfs f0, 0(r3) 5761; P9LE-NEXT: xscvdpuxds f0, f0 5762; P9LE-NEXT: xxspltd v2, vs0, 0 5763; P9LE-NEXT: blr 5764; 5765; P8BE-LABEL: spltMemValConvftoull: 5766; P8BE: # %bb.0: # %entry 5767; P8BE-NEXT: lfsx f0, 0, r3 5768; P8BE-NEXT: xscvdpuxds f0, f0 5769; P8BE-NEXT: xxspltd v2, f0, 0 5770; P8BE-NEXT: blr 5771; 5772; P8LE-LABEL: spltMemValConvftoull: 5773; P8LE: # %bb.0: # %entry 5774; P8LE-NEXT: lfsx f0, 0, r3 5775; P8LE-NEXT: xscvdpuxds f0, f0 5776; P8LE-NEXT: xxspltd v2, vs0, 0 5777; P8LE-NEXT: blr 5778entry: 5779 %0 = load float, float* %ptr, align 4 5780 %conv = fptoui float %0 to i64 5781 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5782 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5783 ret <2 x i64> %splat.splat 5784} 5785 5786define <2 x i64> @spltCnstConvdtoull() { 5787; P9BE-LABEL: spltCnstConvdtoull: 5788; P9BE: # %bb.0: # %entry 5789; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5790; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5791; P9BE-NEXT: lxvx v2, 0, r3 5792; P9BE-NEXT: blr 5793; 5794; P9LE-LABEL: spltCnstConvdtoull: 5795; P9LE: # %bb.0: # %entry 5796; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5797; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5798; P9LE-NEXT: lxvx v2, 0, r3 5799; P9LE-NEXT: blr 5800; 5801; P8BE-LABEL: spltCnstConvdtoull: 5802; P8BE: # %bb.0: # %entry 5803; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5804; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5805; P8BE-NEXT: lxvd2x v2, 0, r3 5806; P8BE-NEXT: blr 5807; 5808; P8LE-LABEL: spltCnstConvdtoull: 5809; P8LE: # %bb.0: # %entry 5810; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5811; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5812; P8LE-NEXT: lxvd2x vs0, 0, r3 5813; P8LE-NEXT: xxswapd v2, vs0 5814; P8LE-NEXT: blr 5815entry: 5816 ret <2 x i64> <i64 4, i64 4> 5817} 5818 5819define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5820; P9BE-LABEL: fromRegsConvdtoull: 5821; P9BE: # %bb.0: # %entry 5822; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5823; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5824; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5825; P9BE-NEXT: xvcvdpuxds v2, vs0 5826; P9BE-NEXT: blr 5827; 5828; P9LE-LABEL: fromRegsConvdtoull: 5829; P9LE: # %bb.0: # %entry 5830; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5831; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5832; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5833; P9LE-NEXT: xvcvdpuxds v2, vs0 5834; P9LE-NEXT: blr 5835; 5836; P8BE-LABEL: fromRegsConvdtoull: 5837; P8BE: # %bb.0: # %entry 5838; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5839; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5840; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5841; P8BE-NEXT: xvcvdpuxds v2, vs0 5842; P8BE-NEXT: blr 5843; 5844; P8LE-LABEL: fromRegsConvdtoull: 5845; P8LE: # %bb.0: # %entry 5846; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2 5847; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 5848; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5849; P8LE-NEXT: xvcvdpuxds v2, vs0 5850; P8LE-NEXT: blr 5851entry: 5852 %conv = fptoui double %a to i64 5853 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5854 %conv1 = fptoui double %b to i64 5855 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5856 ret <2 x i64> %vecinit2 5857} 5858 5859define <2 x i64> @fromDiffConstsConvdtoull() { 5860; P9BE-LABEL: fromDiffConstsConvdtoull: 5861; P9BE: # %bb.0: # %entry 5862; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5863; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5864; P9BE-NEXT: lxvx v2, 0, r3 5865; P9BE-NEXT: blr 5866; 5867; P9LE-LABEL: fromDiffConstsConvdtoull: 5868; P9LE: # %bb.0: # %entry 5869; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5870; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5871; P9LE-NEXT: lxvx v2, 0, r3 5872; P9LE-NEXT: blr 5873; 5874; P8BE-LABEL: fromDiffConstsConvdtoull: 5875; P8BE: # %bb.0: # %entry 5876; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5877; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5878; P8BE-NEXT: lxvd2x v2, 0, r3 5879; P8BE-NEXT: blr 5880; 5881; P8LE-LABEL: fromDiffConstsConvdtoull: 5882; P8LE: # %bb.0: # %entry 5883; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5884; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5885; P8LE-NEXT: lxvd2x vs0, 0, r3 5886; P8LE-NEXT: xxswapd v2, vs0 5887; P8LE-NEXT: blr 5888entry: 5889 ret <2 x i64> <i64 24, i64 234> 5890} 5891 5892define <2 x i64> @fromDiffMemConsAConvdtoull(double* nocapture readonly %ptr) { 5893; P9BE-LABEL: fromDiffMemConsAConvdtoull: 5894; P9BE: # %bb.0: # %entry 5895; P9BE-NEXT: lxv vs0, 0(r3) 5896; P9BE-NEXT: xvcvdpuxds v2, vs0 5897; P9BE-NEXT: blr 5898; 5899; P9LE-LABEL: fromDiffMemConsAConvdtoull: 5900; P9LE: # %bb.0: # %entry 5901; P9LE-NEXT: lxv vs0, 0(r3) 5902; P9LE-NEXT: xvcvdpuxds v2, vs0 5903; P9LE-NEXT: blr 5904; 5905; P8BE-LABEL: fromDiffMemConsAConvdtoull: 5906; P8BE: # %bb.0: # %entry 5907; P8BE-NEXT: lxvd2x vs0, 0, r3 5908; P8BE-NEXT: xvcvdpuxds v2, vs0 5909; P8BE-NEXT: blr 5910; 5911; P8LE-LABEL: fromDiffMemConsAConvdtoull: 5912; P8LE: # %bb.0: # %entry 5913; P8LE-NEXT: lxvd2x vs0, 0, r3 5914; P8LE-NEXT: xxswapd vs0, vs0 5915; P8LE-NEXT: xvcvdpuxds v2, vs0 5916; P8LE-NEXT: blr 5917entry: 5918 %0 = bitcast double* %ptr to <2 x double>* 5919 %1 = load <2 x double>, <2 x double>* %0, align 8 5920 %2 = fptoui <2 x double> %1 to <2 x i64> 5921 ret <2 x i64> %2 5922} 5923 5924define <2 x i64> @fromDiffMemConsDConvdtoull(double* nocapture readonly %ptr) { 5925; P9BE-LABEL: fromDiffMemConsDConvdtoull: 5926; P9BE: # %bb.0: # %entry 5927; P9BE-NEXT: lxv vs0, 16(r3) 5928; P9BE-NEXT: xxswapd vs0, vs0 5929; P9BE-NEXT: xvcvdpuxds v2, vs0 5930; P9BE-NEXT: blr 5931; 5932; P9LE-LABEL: fromDiffMemConsDConvdtoull: 5933; P9LE: # %bb.0: # %entry 5934; P9LE-NEXT: addi r3, r3, 16 5935; P9LE-NEXT: lxvd2x vs0, 0, r3 5936; P9LE-NEXT: xvcvdpuxds v2, vs0 5937; P9LE-NEXT: blr 5938; 5939; P8BE-LABEL: fromDiffMemConsDConvdtoull: 5940; P8BE: # %bb.0: # %entry 5941; P8BE-NEXT: addi r3, r3, 16 5942; P8BE-NEXT: lxvd2x vs0, 0, r3 5943; P8BE-NEXT: xxswapd vs0, vs0 5944; P8BE-NEXT: xvcvdpuxds v2, vs0 5945; P8BE-NEXT: blr 5946; 5947; P8LE-LABEL: fromDiffMemConsDConvdtoull: 5948; P8LE: # %bb.0: # %entry 5949; P8LE-NEXT: addi r3, r3, 16 5950; P8LE-NEXT: lxvd2x vs0, 0, r3 5951; P8LE-NEXT: xvcvdpuxds v2, vs0 5952; P8LE-NEXT: blr 5953entry: 5954 %arrayidx = getelementptr inbounds double, double* %ptr, i64 3 5955 %0 = load double, double* %arrayidx, align 8 5956 %conv = fptoui double %0 to i64 5957 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5958 %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 2 5959 %1 = load double, double* %arrayidx1, align 8 5960 %conv2 = fptoui double %1 to i64 5961 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5962 ret <2 x i64> %vecinit3 5963} 5964 5965define <2 x i64> @fromDiffMemVarAConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 5966; P9BE-LABEL: fromDiffMemVarAConvdtoull: 5967; P9BE: # %bb.0: # %entry 5968; P9BE-NEXT: sldi r4, r4, 3 5969; P9BE-NEXT: lxvx vs0, r3, r4 5970; P9BE-NEXT: xvcvdpuxds v2, vs0 5971; P9BE-NEXT: blr 5972; 5973; P9LE-LABEL: fromDiffMemVarAConvdtoull: 5974; P9LE: # %bb.0: # %entry 5975; P9LE-NEXT: sldi r4, r4, 3 5976; P9LE-NEXT: lxvx vs0, r3, r4 5977; P9LE-NEXT: xvcvdpuxds v2, vs0 5978; P9LE-NEXT: blr 5979; 5980; P8BE-LABEL: fromDiffMemVarAConvdtoull: 5981; P8BE: # %bb.0: # %entry 5982; P8BE-NEXT: sldi r4, r4, 3 5983; P8BE-NEXT: lxvd2x vs0, r3, r4 5984; P8BE-NEXT: xvcvdpuxds v2, vs0 5985; P8BE-NEXT: blr 5986; 5987; P8LE-LABEL: fromDiffMemVarAConvdtoull: 5988; P8LE: # %bb.0: # %entry 5989; P8LE-NEXT: sldi r4, r4, 3 5990; P8LE-NEXT: lxvd2x vs0, r3, r4 5991; P8LE-NEXT: xxswapd vs0, vs0 5992; P8LE-NEXT: xvcvdpuxds v2, vs0 5993; P8LE-NEXT: blr 5994entry: 5995 %idxprom = sext i32 %elem to i64 5996 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 5997 %0 = load double, double* %arrayidx, align 8 5998 %conv = fptoui double %0 to i64 5999 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6000 %add = add nsw i32 %elem, 1 6001 %idxprom1 = sext i32 %add to i64 6002 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6003 %1 = load double, double* %arrayidx2, align 8 6004 %conv3 = fptoui double %1 to i64 6005 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6006 ret <2 x i64> %vecinit4 6007} 6008 6009define <2 x i64> @fromDiffMemVarDConvdtoull(double* nocapture readonly %arr, i32 signext %elem) { 6010; P9BE-LABEL: fromDiffMemVarDConvdtoull: 6011; P9BE: # %bb.0: # %entry 6012; P9BE-NEXT: sldi r4, r4, 3 6013; P9BE-NEXT: add r3, r3, r4 6014; P9BE-NEXT: li r4, -8 6015; P9BE-NEXT: lxvx vs0, r3, r4 6016; P9BE-NEXT: xxswapd vs0, vs0 6017; P9BE-NEXT: xvcvdpuxds v2, vs0 6018; P9BE-NEXT: blr 6019; 6020; P9LE-LABEL: fromDiffMemVarDConvdtoull: 6021; P9LE: # %bb.0: # %entry 6022; P9LE-NEXT: sldi r4, r4, 3 6023; P9LE-NEXT: add r3, r3, r4 6024; P9LE-NEXT: addi r3, r3, -8 6025; P9LE-NEXT: lxvd2x vs0, 0, r3 6026; P9LE-NEXT: xvcvdpuxds v2, vs0 6027; P9LE-NEXT: blr 6028; 6029; P8BE-LABEL: fromDiffMemVarDConvdtoull: 6030; P8BE: # %bb.0: # %entry 6031; P8BE-NEXT: sldi r4, r4, 3 6032; P8BE-NEXT: add r3, r3, r4 6033; P8BE-NEXT: addi r3, r3, -8 6034; P8BE-NEXT: lxvd2x vs0, 0, r3 6035; P8BE-NEXT: xxswapd vs0, vs0 6036; P8BE-NEXT: xvcvdpuxds v2, vs0 6037; P8BE-NEXT: blr 6038; 6039; P8LE-LABEL: fromDiffMemVarDConvdtoull: 6040; P8LE: # %bb.0: # %entry 6041; P8LE-NEXT: sldi r4, r4, 3 6042; P8LE-NEXT: add r3, r3, r4 6043; P8LE-NEXT: addi r3, r3, -8 6044; P8LE-NEXT: lxvd2x vs0, 0, r3 6045; P8LE-NEXT: xvcvdpuxds v2, vs0 6046; P8LE-NEXT: blr 6047entry: 6048 %idxprom = sext i32 %elem to i64 6049 %arrayidx = getelementptr inbounds double, double* %arr, i64 %idxprom 6050 %0 = load double, double* %arrayidx, align 8 6051 %conv = fptoui double %0 to i64 6052 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6053 %sub = add nsw i32 %elem, -1 6054 %idxprom1 = sext i32 %sub to i64 6055 %arrayidx2 = getelementptr inbounds double, double* %arr, i64 %idxprom1 6056 %1 = load double, double* %arrayidx2, align 8 6057 %conv3 = fptoui double %1 to i64 6058 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 6059 ret <2 x i64> %vecinit4 6060} 6061 6062define <2 x i64> @spltRegValConvdtoull(double %val) { 6063; P9BE-LABEL: spltRegValConvdtoull: 6064; P9BE: # %bb.0: # %entry 6065; P9BE-NEXT: xscvdpuxds f0, f1 6066; P9BE-NEXT: xxspltd v2, vs0, 0 6067; P9BE-NEXT: blr 6068; 6069; P9LE-LABEL: spltRegValConvdtoull: 6070; P9LE: # %bb.0: # %entry 6071; P9LE-NEXT: xscvdpuxds f0, f1 6072; P9LE-NEXT: xxspltd v2, vs0, 0 6073; P9LE-NEXT: blr 6074; 6075; P8BE-LABEL: spltRegValConvdtoull: 6076; P8BE: # %bb.0: # %entry 6077; P8BE-NEXT: xscvdpuxds f0, f1 6078; P8BE-NEXT: xxspltd v2, vs0, 0 6079; P8BE-NEXT: blr 6080; 6081; P8LE-LABEL: spltRegValConvdtoull: 6082; P8LE: # %bb.0: # %entry 6083; P8LE-NEXT: xscvdpuxds f0, f1 6084; P8LE-NEXT: xxspltd v2, vs0, 0 6085; P8LE-NEXT: blr 6086entry: 6087 %conv = fptoui double %val to i64 6088 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6089 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6090 ret <2 x i64> %splat.splat 6091} 6092 6093define <2 x i64> @spltMemValConvdtoull(double* nocapture readonly %ptr) { 6094; P9BE-LABEL: spltMemValConvdtoull: 6095; P9BE: # %bb.0: # %entry 6096; P9BE-NEXT: lxvdsx vs0, 0, r3 6097; P9BE-NEXT: xvcvdpuxds v2, vs0 6098; P9BE-NEXT: blr 6099; 6100; P9LE-LABEL: spltMemValConvdtoull: 6101; P9LE: # %bb.0: # %entry 6102; P9LE-NEXT: lxvdsx vs0, 0, r3 6103; P9LE-NEXT: xvcvdpuxds v2, vs0 6104; P9LE-NEXT: blr 6105; 6106; P8BE-LABEL: spltMemValConvdtoull: 6107; P8BE: # %bb.0: # %entry 6108; P8BE-NEXT: lxvdsx vs0, 0, r3 6109; P8BE-NEXT: xvcvdpuxds v2, vs0 6110; P8BE-NEXT: blr 6111; 6112; P8LE-LABEL: spltMemValConvdtoull: 6113; P8LE: # %bb.0: # %entry 6114; P8LE-NEXT: lxvdsx vs0, 0, r3 6115; P8LE-NEXT: xvcvdpuxds v2, vs0 6116; P8LE-NEXT: blr 6117entry: 6118 %0 = load double, double* %ptr, align 8 6119 %conv = fptoui double %0 to i64 6120 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6121 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6122 ret <2 x i64> %splat.splat 6123} 6124 6125; Some additional patterns that come up in real code. 6126define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) { 6127; P9BE-LABEL: sint_to_fp_widen02: 6128; P9BE: # %bb.0: # %entry 6129; P9BE-NEXT: xvcvsxwdp v2, v2 6130; P9BE-NEXT: blr 6131; 6132; P9LE-LABEL: sint_to_fp_widen02: 6133; P9LE: # %bb.0: # %entry 6134; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6135; P9LE-NEXT: xvcvsxwdp v2, vs0 6136; P9LE-NEXT: blr 6137; 6138; P8BE-LABEL: sint_to_fp_widen02: 6139; P8BE: # %bb.0: # %entry 6140; P8BE-NEXT: xvcvsxwdp v2, v2 6141; P8BE-NEXT: blr 6142; 6143; P8LE-LABEL: sint_to_fp_widen02: 6144; P8LE: # %bb.0: # %entry 6145; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6146; P8LE-NEXT: xvcvsxwdp v2, vs0 6147; P8LE-NEXT: blr 6148entry: 6149 %vecext = extractelement <4 x i32> %a, i32 0 6150 %conv = sitofp i32 %vecext to double 6151 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6152 %vecext1 = extractelement <4 x i32> %a, i32 2 6153 %conv2 = sitofp i32 %vecext1 to double 6154 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6155 ret <2 x double> %vecinit3 6156} 6157 6158define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) { 6159; P9BE-LABEL: sint_to_fp_widen13: 6160; P9BE: # %bb.0: # %entry 6161; P9BE-NEXT: xxsldwi vs0, v2, v2, 3 6162; P9BE-NEXT: xvcvsxwdp v2, vs0 6163; P9BE-NEXT: blr 6164; 6165; P9LE-LABEL: sint_to_fp_widen13: 6166; P9LE: # %bb.0: # %entry 6167; P9LE-NEXT: xvcvsxwdp v2, v2 6168; P9LE-NEXT: blr 6169; 6170; P8BE-LABEL: sint_to_fp_widen13: 6171; P8BE: # %bb.0: # %entry 6172; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 6173; P8BE-NEXT: xvcvsxwdp v2, vs0 6174; P8BE-NEXT: blr 6175; 6176; P8LE-LABEL: sint_to_fp_widen13: 6177; P8LE: # %bb.0: # %entry 6178; P8LE-NEXT: xvcvsxwdp v2, v2 6179; P8LE-NEXT: blr 6180entry: 6181 %vecext = extractelement <4 x i32> %a, i32 1 6182 %conv = sitofp i32 %vecext to double 6183 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6184 %vecext1 = extractelement <4 x i32> %a, i32 3 6185 %conv2 = sitofp i32 %vecext1 to double 6186 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6187 ret <2 x double> %vecinit3 6188} 6189 6190define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) { 6191; P9BE-LABEL: uint_to_fp_widen02: 6192; P9BE: # %bb.0: # %entry 6193; P9BE-NEXT: xvcvuxwdp v2, v2 6194; P9BE-NEXT: blr 6195; 6196; P9LE-LABEL: uint_to_fp_widen02: 6197; P9LE: # %bb.0: # %entry 6198; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6199; P9LE-NEXT: xvcvuxwdp v2, vs0 6200; P9LE-NEXT: blr 6201; 6202; P8BE-LABEL: uint_to_fp_widen02: 6203; P8BE: # %bb.0: # %entry 6204; P8BE-NEXT: xvcvuxwdp v2, v2 6205; P8BE-NEXT: blr 6206; 6207; P8LE-LABEL: uint_to_fp_widen02: 6208; P8LE: # %bb.0: # %entry 6209; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6210; P8LE-NEXT: xvcvuxwdp v2, vs0 6211; P8LE-NEXT: blr 6212entry: 6213 %vecext = extractelement <4 x i32> %a, i32 0 6214 %conv = uitofp i32 %vecext to double 6215 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6216 %vecext1 = extractelement <4 x i32> %a, i32 2 6217 %conv2 = uitofp i32 %vecext1 to double 6218 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6219 ret <2 x double> %vecinit3 6220} 6221 6222define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) { 6223; P9BE-LABEL: uint_to_fp_widen13: 6224; P9BE: # %bb.0: # %entry 6225; P9BE-NEXT: xxsldwi vs0, v2, v2, 3 6226; P9BE-NEXT: xvcvuxwdp v2, vs0 6227; P9BE-NEXT: blr 6228; 6229; P9LE-LABEL: uint_to_fp_widen13: 6230; P9LE: # %bb.0: # %entry 6231; P9LE-NEXT: xvcvuxwdp v2, v2 6232; P9LE-NEXT: blr 6233; 6234; P8BE-LABEL: uint_to_fp_widen13: 6235; P8BE: # %bb.0: # %entry 6236; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 6237; P8BE-NEXT: xvcvuxwdp v2, vs0 6238; P8BE-NEXT: blr 6239; 6240; P8LE-LABEL: uint_to_fp_widen13: 6241; P8LE: # %bb.0: # %entry 6242; P8LE-NEXT: xvcvuxwdp v2, v2 6243; P8LE-NEXT: blr 6244entry: 6245 %vecext = extractelement <4 x i32> %a, i32 1 6246 %conv = uitofp i32 %vecext to double 6247 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6248 %vecext1 = extractelement <4 x i32> %a, i32 3 6249 %conv2 = uitofp i32 %vecext1 to double 6250 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6251 ret <2 x double> %vecinit3 6252} 6253 6254define dso_local <2 x double> @fp_extend01(<4 x float> %a) { 6255; P9BE-LABEL: fp_extend01: 6256; P9BE: # %bb.0: # %entry 6257; P9BE-NEXT: xxmrghw vs0, v2, v2 6258; P9BE-NEXT: xvcvspdp v2, vs0 6259; P9BE-NEXT: blr 6260; 6261; P9LE-LABEL: fp_extend01: 6262; P9LE: # %bb.0: # %entry 6263; P9LE-NEXT: xxmrglw vs0, v2, v2 6264; P9LE-NEXT: xvcvspdp v2, vs0 6265; P9LE-NEXT: blr 6266; 6267; P8BE-LABEL: fp_extend01: 6268; P8BE: # %bb.0: # %entry 6269; P8BE-NEXT: xxmrghw vs0, v2, v2 6270; P8BE-NEXT: xvcvspdp v2, vs0 6271; P8BE-NEXT: blr 6272; 6273; P8LE-LABEL: fp_extend01: 6274; P8LE: # %bb.0: # %entry 6275; P8LE-NEXT: xxmrglw vs0, v2, v2 6276; P8LE-NEXT: xvcvspdp v2, vs0 6277; P8LE-NEXT: blr 6278entry: 6279 %vecext = extractelement <4 x float> %a, i32 0 6280 %conv = fpext float %vecext to double 6281 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6282 %vecext1 = extractelement <4 x float> %a, i32 1 6283 %conv2 = fpext float %vecext1 to double 6284 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6285 ret <2 x double> %vecinit3 6286} 6287 6288define dso_local <2 x double> @fp_extend10(<4 x float> %a) { 6289; P9BE-LABEL: fp_extend10: 6290; P9BE: # %bb.0: # %entry 6291; P9BE-NEXT: xxmrghw vs0, v2, v2 6292; P9BE-NEXT: xvcvspdp vs0, vs0 6293; P9BE-NEXT: xxswapd v2, vs0 6294; P9BE-NEXT: blr 6295; 6296; P9LE-LABEL: fp_extend10: 6297; P9LE: # %bb.0: # %entry 6298; P9LE-NEXT: xxmrglw vs0, v2, v2 6299; P9LE-NEXT: xvcvspdp vs0, vs0 6300; P9LE-NEXT: xxswapd v2, vs0 6301; P9LE-NEXT: blr 6302; 6303; P8BE-LABEL: fp_extend10: 6304; P8BE: # %bb.0: # %entry 6305; P8BE-NEXT: xxmrghw vs0, v2, v2 6306; P8BE-NEXT: xvcvspdp vs0, vs0 6307; P8BE-NEXT: xxswapd v2, vs0 6308; P8BE-NEXT: blr 6309; 6310; P8LE-LABEL: fp_extend10: 6311; P8LE: # %bb.0: # %entry 6312; P8LE-NEXT: xxmrglw vs0, v2, v2 6313; P8LE-NEXT: xvcvspdp vs0, vs0 6314; P8LE-NEXT: xxswapd v2, vs0 6315; P8LE-NEXT: blr 6316entry: 6317 %vecext = extractelement <4 x float> %a, i32 1 6318 %conv = fpext float %vecext to double 6319 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6320 %vecext1 = extractelement <4 x float> %a, i32 0 6321 %conv2 = fpext float %vecext1 to double 6322 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6323 ret <2 x double> %vecinit3 6324} 6325 6326define dso_local <2 x double> @fp_extend02(<4 x float> %a) { 6327; P9BE-LABEL: fp_extend02: 6328; P9BE: # %bb.0: # %entry 6329; P9BE-NEXT: xvcvspdp v2, v2 6330; P9BE-NEXT: blr 6331; 6332; P9LE-LABEL: fp_extend02: 6333; P9LE: # %bb.0: # %entry 6334; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6335; P9LE-NEXT: xvcvspdp v2, vs0 6336; P9LE-NEXT: blr 6337; 6338; P8BE-LABEL: fp_extend02: 6339; P8BE: # %bb.0: # %entry 6340; P8BE-NEXT: xvcvspdp v2, v2 6341; P8BE-NEXT: blr 6342; 6343; P8LE-LABEL: fp_extend02: 6344; P8LE: # %bb.0: # %entry 6345; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6346; P8LE-NEXT: xvcvspdp v2, vs0 6347; P8LE-NEXT: blr 6348entry: 6349 %vecext = extractelement <4 x float> %a, i32 0 6350 %conv = fpext float %vecext to double 6351 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6352 %vecext1 = extractelement <4 x float> %a, i32 2 6353 %conv2 = fpext float %vecext1 to double 6354 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6355 ret <2 x double> %vecinit3 6356} 6357 6358define dso_local <2 x double> @fp_extend13(<4 x float> %a) { 6359; P9BE-LABEL: fp_extend13: 6360; P9BE: # %bb.0: # %entry 6361; P9BE-NEXT: xxsldwi vs0, v2, v2, 3 6362; P9BE-NEXT: xvcvspdp v2, vs0 6363; P9BE-NEXT: blr 6364; 6365; P9LE-LABEL: fp_extend13: 6366; P9LE: # %bb.0: # %entry 6367; P9LE-NEXT: xvcvspdp v2, v2 6368; P9LE-NEXT: blr 6369; 6370; P8BE-LABEL: fp_extend13: 6371; P8BE: # %bb.0: # %entry 6372; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 6373; P8BE-NEXT: xvcvspdp v2, vs0 6374; P8BE-NEXT: blr 6375; 6376; P8LE-LABEL: fp_extend13: 6377; P8LE: # %bb.0: # %entry 6378; P8LE-NEXT: xvcvspdp v2, v2 6379; P8LE-NEXT: blr 6380entry: 6381 %vecext = extractelement <4 x float> %a, i32 1 6382 %conv = fpext float %vecext to double 6383 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6384 %vecext1 = extractelement <4 x float> %a, i32 3 6385 %conv2 = fpext float %vecext1 to double 6386 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6387 ret <2 x double> %vecinit3 6388} 6389 6390define dso_local <2 x double> @fp_extend23(<4 x float> %a) { 6391; P9BE-LABEL: fp_extend23: 6392; P9BE: # %bb.0: # %entry 6393; P9BE-NEXT: xxmrglw vs0, v2, v2 6394; P9BE-NEXT: xvcvspdp v2, vs0 6395; P9BE-NEXT: blr 6396; 6397; P9LE-LABEL: fp_extend23: 6398; P9LE: # %bb.0: # %entry 6399; P9LE-NEXT: xxmrghw vs0, v2, v2 6400; P9LE-NEXT: xvcvspdp v2, vs0 6401; P9LE-NEXT: blr 6402; 6403; P8BE-LABEL: fp_extend23: 6404; P8BE: # %bb.0: # %entry 6405; P8BE-NEXT: xxmrglw vs0, v2, v2 6406; P8BE-NEXT: xvcvspdp v2, vs0 6407; P8BE-NEXT: blr 6408; 6409; P8LE-LABEL: fp_extend23: 6410; P8LE: # %bb.0: # %entry 6411; P8LE-NEXT: xxmrghw vs0, v2, v2 6412; P8LE-NEXT: xvcvspdp v2, vs0 6413; P8LE-NEXT: blr 6414entry: 6415 %vecext = extractelement <4 x float> %a, i32 2 6416 %conv = fpext float %vecext to double 6417 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6418 %vecext1 = extractelement <4 x float> %a, i32 3 6419 %conv2 = fpext float %vecext1 to double 6420 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6421 ret <2 x double> %vecinit3 6422} 6423 6424define dso_local <2 x double> @fp_extend32(<4 x float> %a) { 6425; P9BE-LABEL: fp_extend32: 6426; P9BE: # %bb.0: # %entry 6427; P9BE-NEXT: xxmrglw vs0, v2, v2 6428; P9BE-NEXT: xvcvspdp vs0, vs0 6429; P9BE-NEXT: xxswapd v2, vs0 6430; P9BE-NEXT: blr 6431; 6432; P9LE-LABEL: fp_extend32: 6433; P9LE: # %bb.0: # %entry 6434; P9LE-NEXT: xxmrghw vs0, v2, v2 6435; P9LE-NEXT: xvcvspdp vs0, vs0 6436; P9LE-NEXT: xxswapd v2, vs0 6437; P9LE-NEXT: blr 6438; 6439; P8BE-LABEL: fp_extend32: 6440; P8BE: # %bb.0: # %entry 6441; P8BE-NEXT: xxmrglw vs0, v2, v2 6442; P8BE-NEXT: xvcvspdp vs0, vs0 6443; P8BE-NEXT: xxswapd v2, vs0 6444; P8BE-NEXT: blr 6445; 6446; P8LE-LABEL: fp_extend32: 6447; P8LE: # %bb.0: # %entry 6448; P8LE-NEXT: xxmrghw vs0, v2, v2 6449; P8LE-NEXT: xvcvspdp vs0, vs0 6450; P8LE-NEXT: xxswapd v2, vs0 6451; P8LE-NEXT: blr 6452entry: 6453 %vecext = extractelement <4 x float> %a, i32 3 6454 %conv = fpext float %vecext to double 6455 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6456 %vecext1 = extractelement <4 x float> %a, i32 2 6457 %conv2 = fpext float %vecext1 to double 6458 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6459 ret <2 x double> %vecinit3 6460} 6461 6462define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) { 6463; P9BE-LABEL: fp_extend_two00: 6464; P9BE: # %bb.0: # %entry 6465; P9BE-NEXT: xxmrghd vs0, v2, v3 6466; P9BE-NEXT: xvcvspdp v2, vs0 6467; P9BE-NEXT: blr 6468; 6469; P9LE-LABEL: fp_extend_two00: 6470; P9LE: # %bb.0: # %entry 6471; P9LE-NEXT: xxmrgld vs0, v3, v2 6472; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6473; P9LE-NEXT: xvcvspdp v2, vs0 6474; P9LE-NEXT: blr 6475; 6476; P8BE-LABEL: fp_extend_two00: 6477; P8BE: # %bb.0: # %entry 6478; P8BE-NEXT: xxmrghd vs0, v2, v3 6479; P8BE-NEXT: xvcvspdp v2, vs0 6480; P8BE-NEXT: blr 6481; 6482; P8LE-LABEL: fp_extend_two00: 6483; P8LE: # %bb.0: # %entry 6484; P8LE-NEXT: xxmrgld vs0, v3, v2 6485; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6486; P8LE-NEXT: xvcvspdp v2, vs0 6487; P8LE-NEXT: blr 6488entry: 6489 %vecext = extractelement <4 x float> %a, i32 0 6490 %conv = fpext float %vecext to double 6491 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6492 %vecext1 = extractelement <4 x float> %b, i32 0 6493 %conv2 = fpext float %vecext1 to double 6494 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6495 ret <2 x double> %vecinit3 6496} 6497 6498define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) { 6499; P9BE-LABEL: fp_extend_two33: 6500; P9BE: # %bb.0: # %entry 6501; P9BE-NEXT: xxmrgld vs0, v2, v3 6502; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6503; P9BE-NEXT: xvcvspdp v2, vs0 6504; P9BE-NEXT: blr 6505; 6506; P9LE-LABEL: fp_extend_two33: 6507; P9LE: # %bb.0: # %entry 6508; P9LE-NEXT: xxmrghd vs0, v3, v2 6509; P9LE-NEXT: xvcvspdp v2, vs0 6510; P9LE-NEXT: blr 6511; 6512; P8BE-LABEL: fp_extend_two33: 6513; P8BE: # %bb.0: # %entry 6514; P8BE-NEXT: xxmrgld vs0, v2, v3 6515; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6516; P8BE-NEXT: xvcvspdp v2, vs0 6517; P8BE-NEXT: blr 6518; 6519; P8LE-LABEL: fp_extend_two33: 6520; P8LE: # %bb.0: # %entry 6521; P8LE-NEXT: xxmrghd vs0, v3, v2 6522; P8LE-NEXT: xvcvspdp v2, vs0 6523; P8LE-NEXT: blr 6524entry: 6525 %vecext = extractelement <4 x float> %a, i32 3 6526 %conv = fpext float %vecext to double 6527 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6528 %vecext1 = extractelement <4 x float> %b, i32 3 6529 %conv2 = fpext float %vecext1 to double 6530 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6531 ret <2 x double> %vecinit3 6532} 6533